feature
800 V Avalanche Rugged Power Stage Low Frequency Jitter pwm Operation EMI Operating Frequency:
– Type L is 60 kHz
– Type H is 115 kHz
Standby power < 50 MW at 265 VAC Adjustable set point limit Current adjustable Accurate overvoltage protection On-board soft start Safe automatic restart after fault Hysteresis Thermal shutdown Delay overload protection Applications Home and household auxiliary power equipment
ATX Auxiliary Power Low/Medium Power AC-DC Adapter for Set Top Boxes, DVD Players and Recorders, White Product Description This unit is an 800 volt off-line converter Rugged power stage, a pwm control, two levels of overcurrent protection, overvoltage and Overload protection, hysteretic thermal protection, soft-start and safe auto-restart eliminate any fault conditions. Burst mode operation with very low consumption of the device helps meet backup power saving regulations. Prepaid frequency jitter reduces the cost of emi filters. This additional power timer allows managing the output peak power for the design time window. The high voltage start-up circuit is embedded in the device.
Typical topology

block diagram

thermal shutdown

Typical circuit

Rewind Application (Basic)

Flyback application

Instructions
viper28 is a high performance low voltage pwm controller chip with 800v avalanche voltage rugged power section.
The controller includes: oscillator with jitter characteristics, start-up circuit characteristics with soft-start function, pulse width modulation logic, current limit circuit, adjustable setting value, second overcurrent circuit, burst mode management circuit, EPT circuit, UV low level circuit, auto restart circuit and thermal protection circuit. The current limit setpoint is set by the control pin. Burst mode operation guarantees high operation in standby mode, contributing to the achievement of power saving specifications. All fault protection uses an auto-restart mode with a very low repetition rate to prevent the IC from overheating.
Avalanche rugged n-channel MOSFETs are used in the power section and gate driver power section to ensure safe operation within the specified energy ratings and high dv/dt. The BVDSS minimum for the power section is 800 V, with a typical RD(on) of 7Ω at 25°C.
The integrated sensor mesh structure allows for nearly lossless current sensing.
Gate drivers are designed to provide controlled gate current during switching to minimize common-mode electromagnetic interference. During UVLO conditions, an internal pull-down circuit holds the gate low to ensure that the power section cannot be turned on accidentally.
High Voltage Starter Generator The high voltage current generator is powered through the DRAIN pin only if the input bulk capacitor voltage is above the vdrain_start threshold, typically 80vdc. when? The high voltage current generator turns on and the IDDCH current (3 mA typical) is delivered to the capacitor on the VDD pin. In auto-restart mode after a fault event, the IDDCH current is reduced to 0.6 mA, typical. in order to have a slow duty cycle during the restart phase.

Power-Up Soft Start If the input voltage rises to the device start-up level (vdrain_start), the vdd voltage begins to increase due to the IDDCH current generated by the internal high voltage (see Table 6 on page 7) to the voltage start circuit. If the vdd voltage reaches the vddon threshold (~14v), the power mosfet starts switching and the high voltage current generator turns off.
The IC is powered by the energy stored on the capacitor at the VDD pin, CVDD, up to the self-powered circuit (usually the auxiliary winding of the transformer and the steering diode). generate enough voltage to sustain operation.
The size of the CVDD capacitor must be sufficient to avoid rapid discharge and maintain the desired voltage value above the VDDOFF threshold: too low a value of the capacitor may terminate switching operation before the controller receives any energy from the auxiliary winding.
The following formula can be used for the calculation of the VDD capacitor:
Equation 1

TSSAUX is the time required for the auxiliary voltage to stabilize. This time it's the application that estimates the capacitance based on the output stage configuration (transformer, output, etc.).
During converter startup, the drain current limit is gradually increased to a maximum value. In this way, the stress on the secondary diode is greatly reduced. It also helps prevent transformer saturation. The soft-start time lasts 8.5 ms This function is implemented for every attempt to start the converter or after a fault.

Power-off operation When the drive is powered off, once the input voltage is too low, the system will lose regulation to the peak current limit. When the voltage drops to the VDDOFF threshold (8 V typical) the power mosfet turns off and the energy transfer to the IC is interrupted, so the VDD voltage continues to decrease, after that, if the VDR is below VDRAIN_START (80 V typical), the start-up sequence is interrupted Disabled and power down is complete. This feature helps prevent converter restart attempts and ensures that the output voltage decays monotonically downward during system power.
Auto-restart operation If the VIN is higher than VDRAIN_START after the drive is powered off, the start-up sequence is not inhibited, it is activated only when the VDD voltage drops below the threshold (4.5 V typical). This means that the high voltage start-up current generator restarts VDD and the capacitor is only charged when the VDD voltage is lower than VDDRESTART. The above scenario, for example, describes a power outage due to a fault. After a fault, the charge current is 0.6 mA (typ) instead of the 3 mA (typ) stage that normally starts the converter. This feature, together with the low VDDREStart threshold (4.5 V), ensures faults, restart attempts of the IC with a long repetition rate, safe converter operation, and extremely low power throughput.
short circuit event.
Timing Diagram: Behavior After Short Circuit

The oscillator switching frequency is fixed internally at 60 kHz or 115 kHz. In both cases, the switching frequency modulation is about ±4 kHz (60 kHz version) or ±8 kHz. (115khz version) at 250hz (typical) rate, the resulting spread spectrum effect distributes the energy of each harmonic of the switching frequency over multiple sideband harmonics with the same total energy but smaller amplitudes.

The current mode conversion with adjustable current limit points to the fact that the device is a current mode converter: the drain current is sensed and converted to a voltage which is applied to the non-inverting pin of the pwm comparator. Compare this voltage one on the feedback pin, cycle by cycle, through a voltage divider.
The viper28 has a default current limit value idlim, which the designer can control via the RLIM resistor connected to the controller to have the minimum current sag required to initiate the IDLIM adjustment according to the electrical specification: no rlim or high rlim (i.e. 100 kΩ) , the current limit is fixed at the default value Over voltage protection (ovp) The device can monitor the output voltage of the inverter. This is done by the cont pin that tracks the output voltage of the converter while the voltage developed by the auxiliary winding during the power MOSFET off period, via the turns ratio. and ROVP resistor divider winding (R3, R4 are ROVP and RLIM respectively)). The controller recognizes an overvoltage condition if the voltage applied exceeds the internal 3V reference voltage four times in a row. This special function uses an internal counter; this is to reduce sensitivity to noise and prevent false activation of the latch. whenever the ovp signal is not triggered within one oscillator cycle.
The resistance-to-divider ratio kovp will be given by:

About cont pin
Through the cont pin, the following functions can be achieved:
one. Current limit set value
2. The inverter output voltage over-voltage protection external resistor combination needs to activate one or more cont pin functions.

Feedback and Overload Protection (OLP) viper28 is a current mode converter: the feedback pin controls pwm operation, controls burst mode and activates the device's overload protection.
Internal current mode structure.
When the feedback pin voltage is between vfb-bm and vfblin (0.6v and 3.5v respectively, typ) drain current is sensed and converted to be applied to the inverting pin of the non-pwm comparator.
This voltage is compared to the voltage on the feedback pin through a voltage divider on the loop basis. When these two voltages are equal, the pwm logic commands the switch to turn off the power mosfet. The drain current is always limited to the IDLIM value.
In the event of an overload, the feedback response to the event increases above vfflin, the drain current is limited, either set to the default idlim value or the value applied through the control pin's resistor (using RLIM); PWM Comparator is disabled.

At the same time, the internal current generator starts to charge the feedback capacitor (cfb). When the feedback voltage reaches the vfbolp threshold, the converter turns off, the start-up phase is activated, and the Icharge value is reduced to 0.6 mA. During the first start-up phase of the converter, after the soft-start time (8.5 ms typical) the output voltage can force the feedback pin voltage up to the threshold at which VFBOLP shuts down the converter itself.
To avoid this event, it must be based on the output load. The network feedback further corrects the stability of the compensation loop. The time from overload detection (vfb=vfblin) to device shutdown (vfb=vfbolp) can be calculated from the cfb value using the formula:
Formula 5

The capacitor connected to the FB pin (CFB) is used as part of the circuit to compensate the feedback loop, but also as the element that delays the OLP from turning off due to the time it takes for the capacitor to charge (see Equation 5).
After the start-up time, 8.5 ms typical, during which the feedback voltage is fixed at vfflin, the output capacitor cannot reach its nominal value, the controller interprets this overload condition. In this case, the olp delay helps to avoid the wrong device being shut down during boot.
Based on the above considerations, the OLP delay time must be long enough to pass the initial output voltage transient only when the output voltage is in steady state. The output transient time depends on the value of the output capacitor from the load.
When the calculated loop stability of the CFB capacitor is too low to ensure sufficient olp delay, an alternative compensation network can be used, the poles (fpfb, fpfb1) and zero (fzfb) are determined by the capacitor cfb and cfb1 and resistor rfb1 are introduced. Capacitor cfb is higher in frequency than fzb and fpfb1. This rod is usually used to compensate for high frequency zeros due to ESR (resistance of the output capacitor of an equivalent series flyback converter).
Considering the scheme, the mathematical expressions for these poles and zero frequencies are formulated as follows:

rfb(dyn) is the dynamic resistance seen by the fb pin cfb1 capacitor fixed olp delay, usually the result for cfb1 is much higher than cfb. Equation 5 can still be used to calculate the OLP delay time, but cfb1 must be considered in place of the CFB. Using alternative compensation networks, the designer can satisfy loop stability and sufficient olp delay time in all cases.

Burst Mode Operation at No Load or Very Light Load The feedback loop reduces the FEEDBACK pin voltage as the load decreases. As the voltage reaches the burst mode threshold vfbbm the mosfet stops switching. After the mosfet is stopped, the feedback pin voltage rises and exceeds the VFBBM threshold of 100 mV due to the feedback reaction to the cessation of energy transfer, and the burst mode hysteresis typical mosfet power device starts switching again. This behavior is called burst mode. The system alternately switches from time periods when the power mosfet is used to time periods when the power mosfet does not switch. The output delivered to the switching period exceeds the load power demand; the excess power is balanced from the non-switching period when no power is being processed. The advantage of burst mode operation is a much lower average switching frequency operating frequency than normal operation, up to about 100 Hz, minimizing all frequency-dependent losses.
During burst mode operation, the drain current is limited to Id_bm, 160 mA (typ). Burst Mode Timing Diagram, Light Load Management

Additional Power Management (EPT) Some applications require additional power for a limited time window during which the converter must guarantee regulation. Additional power management features allow the design of converters that can meet this requirement and are provided by the EPT pin. This feature requires the use of a charged capacitor on the EPT pin (CEPT) or discharge through a 5µA current cycle. When the drain current rises to 85% of the value of IDLIM, see IDLIM (Table 8 on page 8), the current generator charges CEPT and the capacitor discharges when the drain current falls below idlim. If the voltage of the cept reaches the VEPT threshold (typ., 4 V), the converter is turned off.
After the inverter is turned off, the VDD voltage will drop below the VDD(turn-on) threshold (14.5 V typical), and according to the auto-restart operation, the VDD pin voltage must be below the VDD(restart) threshold (typical, 4.5V) to charge Again the VDD capacitor. Also, only when the voltage on the EPT pin falls below VEPT (restart) (typ, 0.6V). Low cept discharge combined with low restart threshold current ensures safe operation and avoids overheating during repeated overloads. The value of cept must be chosen in to prevent the device from overheating. If the function is not used.
Secondary overcurrent protection and hiccup mode viper28 prevent short circuit of secondary rectifier, shorted secondary winding or hard saturation of flyback transformer. Such as abnormally when the drain current exceeds 1s to call the condition.
In order to distinguish between actual faults and disturbances (such as those caused during ESD tests) a "warning state" is entered after the first signal trip. If the signal does not trip during the subsequent switching cycle, assuming a temporary disturbance, the protection logic will reset in the idle state; otherwise, if the second OCP threshold is exceeded two consecutive switching cycles, a true fault is assumed and the power mosfet closure.
The closed state is locked as long as the device is provided. When it is disabled, no energy is transferred from the auxiliary winding, so a voltage is developed on the VDD capacitor. decay until the VDD undervoltage threshold (VDDOFF) clears the latch.
The startup high voltage current generator remains off until the VDD voltage falls below its restart voltage, VDD (restart). Under this condition, the VDD capacitor is charged again with 600mA current and the converter switch will restart if vddon occurs. If the fault condition is not eliminated the device goes into auto restart mode. This behavior, resulting in low frequency intermittent operation (hiccup mode operation), places very low stress on the power circuit.
Hiccup Mode ocp: Timing Diagram

Packaging Machinery Data To meet environmental requirements, ST offers these equipment packaging in EcoPack®. These packages feature lead-free secondary interconnects. Category secondary interconnects are marked on the packaging and inner box labels, in compliance with jedec standard jesd97. The maximum rating conditions related to welding are also marked on the inner box label. EcoPack is a ST trademark.