Features: 256 kbit Ferroelectric Random Access Memory (F-RAM) logically organized as 32k x 8 high endurance 100 trillion (1014) read/write 151 year data retention period (see data retention and endurance table) nodelay 8482 ; write Into advanced high reliability ferroelectric process Very fast Serial Peripheral Interface (SPI) frequency up to 40 MHz Direct replacement for Serial Flash and EEPROM Hardware Support for SPI Mode 0 (0, 0) and Mode 3 (1, 1) Sophisticated write protection scheme Hardware protection using write protect (WP) pin Software protection using write disable instruction Software block protection of 1/4, 1/2 or entire array Device ID Manufacturer ID and Product ID Low power 1 MHz 220µA Active Current 90µA (typ) Standby Current 5µA Sleep Mode Current Low Voltage Operation: VDD=2.0V to 3.6V Industrial Temperature: –40°C to +85°C Package 8-pin Small Outline Integrated Circuit (SOIC) Package 8-pin Thin Dual Flat No-Lead (DFN) Package Compliant with Restriction of Hazardous Substances (RoHS)

Function description: fm25v02 is a 256kbit non-volatile memory, using advanced ferroelectric technology. Ferroelectric random access memory or f-ram is non-volatile and performs read and write operations. Similar to a ram. It provides 151 years of reliable data retention while eliminating the complexity, overhead and system-level reliability concerns of serial flash, eeprom and other non-volatile memory. Unlike serial flash and eeprom, the fm25v02 performs writes at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been successfully transferred to the device. Can be started without data polling.

Also, this product has a sizable write-persistent non-volatile memory compared to other products. The FM25V02 is capable of supporting 1014 read/write cycles, or 100 million times more write cycles than eeprom. These features make the FM25V02 ideal for non-volatile memory applications that require frequent or fast writes. Examples include data collection, where cycles may be critical where industrial control is required, serial flash or long write times for eeproms can result in data loss. FM25V02 is a replacement for serial EEPROM or flash memory as hardware. This FM25V02 uses a high-speed SPI bus, which enhances the high-speed write capability of f-ram technology. The unit contains a read-only device ID that allows the host to determine manufacturer, product density, and product revision. Device specifications are guaranteed over the industrial temperature range of -40°C to +85°C.

Functional overview: FM25V02 is a serial F-RAM memory. The memory array is logically organized as 32768 x 8 bits using the industry standard Serial Peripheral Interface (SPI) bus. The functional operation of this F-RAM is similar to that of serial flash and serial EEPROM. The main difference between the FM25V02 and serial flash or EEPROM with the same pins is that the f-ram has excellent write performance, high endurance and low power consumption. Memory structure When accessing the FM25V02, the user address is the position of 8 data bits each of 32K. These eight data shift bits go in and out continuously. Use the spi access address protocol, including chip select (allowing multiple devices on the bus), an opcode, and a two-byte address. The value for the upper drill address range is 'don't care'. The full 15-bit address uniquely specifies each byte address. Most of the functions of the FM25V02 are handled by the SPI control interface or by the on-board circuitry. Access time memory operations are essentially zero, and serial protocols are required over time. That is, the memory is read or written at the speed of the spi bus. Unlike serial flashes or EEPROMs, there is no need to poll the device for a ready condition because writes happen at bus speed. A write operation has completed when a new bus transaction can be transferred to the device. This is explained in more detail in the interface area Serial Peripheral Interface - SPI Bus The FM25V02 is an SPI slave device that runs up to 40MHz. The high-speed serial bus provides high-performance serial communication with the SPI host. Many common microcontrollers have hardware SPI ports that allow direct interfacing. Use the normal port pins of the microcontroller.

The FM25V02 operates in SPI modes 0 and 3. SPI Overview SPI is a four-pin interface with chip select (CS), serial input (SI), serial output (SO), and serial clock (SCK) pins. SPI is a synchronous serial interface that uses clock and data pins for memory access and supports multiple devices on the data bus. Devices on the SPI bus use the CS active pin. The relationship between chip select, clock and data is through spi mode. This device supports SPI modes 0 and 3. In both modes, data is recorded to the F-RAM on the rising edge of SCK starting from the first rising edge after CS is active. The spi protocol is controlled by opcodes. These opcodes specify commands from a bus master to a slave. After activating CS, the first byte transferred from the bus master is the opcode. Depending on the opcode, any address and then transfer data. CS must complete the operation before a new opcode can be issued. The terms commonly used in the spi protocol are as follows: The master spi master device controls operations on the spi bus. An SPI bus may have only one master node and one or more slave node devices. All slaves share the same SPI bus. The master can use the cs pin to select any slave. All operations must be activated by the slave device by pulling the CS pin of the slave device low. The master also generates all data transfers on sck and si so the line is synchronized with this clock.

The SPI slave master activates the spi slave select line through the chip. The slave device gets sck from the spi as input to the master and all communication is clocked with this. The spi slave never starts the communication bus on the spi and only operates on the instructions of the master. The fm25v02 runs as a spi slave and can share the bus of the spi and other spi slave devices. Chip Select (CS) To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued to the slave device only when the CS pin is low. When the device is not selected, data passing through the si pin is ignored and the serial output pin (SO) remains in a high impedance state. Note: New instructions must start from the falling edge of CS. Therefore, only one opcode selection "loop" can be issued per active chip. Serial Clock (SCK) After the serial clock is run by the SPI master and CS, the communication is synchronized low with this clock. The FM25V02 enables SPI mode 0 and 3 communication for data. In both modes, the input is latched by the slave output on the rising edge of SCK issued on the falling edge. Therefore, the first rising edge of SCK indicates that the first bit (msb) of the spi instruction arrives at Spin. Additionally, all data inputs and outputs are synchronized with SCK. Data transmission (si/so) The spi data bus consists of two serial data lines si and so to communicate. si is also called master out slave in (mosi) so it is called master slave out (miso). The master issues commands to the slave via the si pin, and the slave responds via the SO pin. Multiple slave devices can share the si and so lines described earlier.

The FM25V02 has two separate pins for silicon and sulfur, and it can be connected to the host as shown. For microcontrollers that do not have a dedicated SPI bus, a general-purpose port can be used. To reduce resources on the hardware controller, you can connect the two data tie pins (si, so) together, and tie the fixed and wp pins together. The diagram shows such a configuration, which uses only three pins. Most Significant Bit (msb) The spi protocol requires that the first bit transmitted is the most significant bit (msb). This pairs address and data transfers. 256kbit serial f-ram for any read or write operation. Because the address has only 15 bits, the upper bits of the input are ignored by the device. Although the bit is "don't care", Cypress recommends setting this bit to "0" for a seamless transition to higher memory densities. After the serial opcode selects the slave, CS goes low and the first byte received is considered the opcode for the intended operation. The FM25V02 uses standard opcodes for memory access. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin until the next falling edge of CS and the SO pin remains tri-stated. Status Register FM25V02 has an 8-bit status register. The bit register in Status is used to configure the device.

SPI Mode The FM25V02 can be driven by a microcontroller with SPI to operate peripherals in one of two modes: spi mode 0 (cpol=0, cpha=0) spi mode 3 (cpol=1, cpha=1) for both In this mode, input data is latched on rising SCK edge active from the first rising edge after CS runs. If the clock starts from a high state (mode 3), the first one considers the rising edge after the clock switch. Output data is available on the falling edge of SCK.

The two SPI modes are shown in Figure 5 on page 6 and Figure 6 on page 6. The clock state in the absence of the bus master The transfer data is: Mode 0 SCK remains at 0 Mode 3 SCK remains at 1 The state of the device slave SCK pin is detected in SPI mode when the device is selected by lowering the CS pin. If the SCK pin is low when the device is selected, SPI mode 0 is assumed to be high, and the SCK pin is assumed to be high, operating in SPI mode 3.

The FM25V02 cannot be accessed within the TPU time after the power is turned on. The user must adhere to the timing parameter tpu, which is the minimum time from VDD (minutes) to the first CS low. The command structure has nine commands, called opcodes, that can be issued through a bus master connected to the FM25V02. They are listed in Table 1. These opcodes control the functions performed by the memory

wren - Set write enable latch FM25V02 will power up with write disabled. Wren commands must be issued before any write operations. Sending the wren opcode allows the user to issue subsequent opcodes for write operations. These include writing to the status register (wrsr) and writing to memory (write). Sending the wren opcode causes an internal write enable to set the latch. A flag bit in the status register, called WEL, indicates the state of the latch. wel='1' means writing is allowed. Attempting to write to the WEL bit in the status register has no effect on the state of that bit - only the wren opcode can set this bit. The WEL bit will automatically clear the cs edge after a wrdi, wrsr or write operation when rising. This prevents further writes to the Status Register or F-RAM array without another wren command. Figure illustrates the wren command bus configuration.

wrdi - reset write-enable latch The wrdi command clears the write-enable latch by clearing it. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that Wel equals '0'. Figure illustrates the wrdi command bus configuration.

RDSR - Read Status Register The rdsr command allows the bus master to verify the contents of the status register. The read status register provides the function for write protection. After the RDSR opcode, the FM25V02 will return a byte register containing the status content. wrsr - Write Status Register The wrsr command allows the SPI bus master to write to the status register and change the write protection configuration by setting the wpen, bp0 and bp1 bits as desired. Before issuing a wrsr command, the wp pin must be high or inactive. Notes On the FM25V02, wp only prevents writing to the status register, not the memory array. Before sending the wrsr command, the user must send the wren command to enable writing. Executing the wrsr command is a write operation and, therefore, clears the write enable latch.

The memory operates on an SPI interface, which is capable of providing high clock frequencies, highlighting the fast write capability of F-RAM technology. Unlike serial flash and eeprom, the fm25v02 can perform sequential writes at bus speed. All writes to memory are asserted and de-evaluated starting with the wren opcode and cs. The next opcode is write. This write opcode is followed by a 15-bit address (a14-a0) memory containing the first data byte to be written. The upper bits of the two-byte address are ignored. Subsequent bytes are data bytes written in sequence. The address is incremented internally as long as the bus master continues to issue clocks and keep CS low.