Features Adjustable Switching Frequency Up to 200kHz Current Mode Control Soft-Start and Shutdown Control Automatic Burst Mode Operation Standby Conditions Capable of Meeting "Blue Angel" Standards (<1W Total Power Consumption) Internal Trim Nano Reference Low Voltage Lock-in Hysteresis Integrated Startup Power Avalanche Rugged Thermal Protection Low Standby Current Adjustable Current Limit Description
Viper100/ 100A , using Vipower M0 fabrication technology, combines state-of-the-art pwm circuits and optimized high voltage avalanche rugged vertical power mosfet (620v or 700v/3a) on the same silicon wafer.
Typical applications include off-line power secondary power wide 50W range conditions and single range 100W or double configuration. Both are compatible with either primary or secondary regulation loops when compared to discrete solutions. Burst mode operation is an additional feature of this device, offering the possibility of alternate modes of operation without additional components.

Pin Function Description Drain Pin:
Integrated power mosfet drain pin. It provides internal bias current during startup and shut down during normal operation through an integrated high voltage current source. The device is able to operate at its normal level, ensuring self-protection against voltage surges, PCB stray inductance and unbuffered operation allowing low output power.
Source terminal number: power mosfet source pin. Primary side circuit common ground connection.
VDD pin:
This pin provides two functions:
- It corresponds to the control part of the circuit. If VDD is lower than 8V, the startup current source is activated and the output power mosfet is turned off until the VDD voltage reaches 11V, at this stage, the internal current consumption is reduced, the current generated by the VDD pin is about 2A The compressor pin is shorted to ground . After the current source is turned off, the device tries to start by switching it again. - This pin is also connected to the error amplifier in order to allow primary and secondary regulation configurations. In case of primary regulation, the internal 13V regulation reference voltage is used to keep VDD at 13V. For secondary regulation, the voltage is between 8.5V and 12.5V and will be designed by a transformer on the VDD pin to jam the transconductance amplifier Output to advanced state. The comp pin behaves like a constant current source and can be easily connected to the output of an optocoupler.
Note that any overvoltage errors due to regulation still detect loop failures by VDD voltage amplification that cannot exceed 13V. The output voltage will be slightly higher than nominal, but still under control.
Compressor Pins:
This pin provides two functions:
- It is the output amplifier of the error transconductance and allows the connection to provide the required compensation network to regulate the transfer function of the loop. Its bandwidth can be easily adjusted to the desired value and common component values. As mentioned above, the secondary regulatory configuration is also through the compressor pins.
- When the compressor voltage is lower than 0.5V, the circuit is closed and the duty cycle of the zero power mosfet. This feature can be used to shut down the converter and is automatically activated by the regulation loop (regardless of configuration) to provide negligible burst mode operation output power or open load conditions.
OSC pin: The RT-CT network must be connected on this pin to define the switching frequency. Note that although RT and VDD are connected, there is no significant frequency change in VDD ranging from 8V to 15V. It also provides when connected to an external frequency source.

Avalanche test circuit

Offline Power Supply with Auxiliary Power Feedback

Offline power supply with optocoupler feedback

Instructions:
Current Mode Topology: The current mode control method, as integrated in the Viper100/100A uses two control loops - an inner current control loop and an outer voltage control loop. When the power mosfet output transistor turns on, the inductor current (transformer primary side) is converted into a voltage proportional to this vs current as monitored using sensefet technology. Output voltage error when vs reaches vcomp) The power switch is toggled off. Therefore, the outer voltage control loop defines the inner loop to regulate the peak level through the power switch and the current transformer windings of the mains.
Excellent open-loop DC and dynamic line mode control with voltage feed-forward characteristics of the regulated current is guaranteed due to the inherent input. This results in improved line regulation, instantaneous correction to line voltage changes and better stability of the regulation loop.
The current mode topology also ensures good short-circuit limitation. In the first phase the output current increases slowly following the dynamics of the regulation loop. Then the max current limit internal setting is reached and eventually stops because the power on VDD is no longer correct. Specifically, the application of the maximum peak current internally can limit the voltage excursion on the compressor pins externally. An integrated blanking filter suppresses the PWM comparator output shortly after the integrated power mosfet is turned on. This feature prevents abnormal or premature termination of switching pulses from primary side current spike capacitance or secondary side rectifier reverse recovery time.
Standby mode quasi-on-load standby operation automatically results in burst mode operation allowing secondary side voltage regulation to flank. Burst mode operation occurs from normal operation to power pstby
lp is the primary inductance of the transformer.
fsw is the normal switching frequency.
Istby is the minimum controllable current,
Corresponds to the device can work normally. This current can be calculated as: stby=(tb+td) vehicle identification number Lp Tb+Td is the sum of punching time and punching time. The propagation time of the internal current sense and the comparator, roughly representing the minimum turn-on time of the device. Note that pstby may be affected by converter efficiency at low loads, the primary auxiliary voltage must be included.
Once the power falls below this limit, the auxiliary secondary voltage begins to increase above the 13V regulation level, forcing the output transconductance amplifier voltage to a low state (vcomp The above cycle repeats indefinitely, providing an effective duty cycle well below the minimum value for normal operation. The equivalent switching frequency is also lower than the normal frequency, reducing the consumption of the mains input. This mode of operation allows the Viper100/100A to meet the new German "Blue" "Angel" standard with a total power of less than 1W when the system consumes standby. The output voltage remains stable around normal levels, with low frequencies corresponding to burst-mode ripple. The amplitude of this ripple is low because the output capacitor and low output current draw under such conditions. Normal operation automatically resumes above pstby when power is restored. High Voltage Startup Current Source An integrated high voltage current source provides bias current from the DRAIN pin during startup. A portion of this current is absorbed by the internal control circuit into standby mode consumption, and is also supplied to an external capacitor connected to the VDD pin. Once the voltage on this pin reaches the threshold Vddon of the high voltage UVLO logic, the device enters active mode and begins toggling. The startup current generator is turned off, and the converter should normally supply the required current at the VDD pin through the auxiliary transformer winding as shown in Figure 15.
Under abnormal conditions the auxiliary winding cannot supply low voltage to supply current to the VDD pin (i.e. short circuit the output of the converter), the external capacitor self-discharges to the threshold voltage vddoff of the low uvlo logic, and the device returns to an inactive state where the internal circuit is in Standby mode, and the startup current source is activated. The converter enters an endless start-up cycle, starting with a duty cycle defined by the charge current ratio when the Viper100/100A tries to start. This ratio is fixed at 2 to 15 by design, providing a 12% startup duty cycle with a power consumption of approximately 0.6 W at startup, for a 230 Vrms input voltage. Such a low start-up duty cycle value prevents short-circuiting of the output rectifier and transformer.
The external capacitor CVDD on the VDD pin must be sized for the time required for the converter to start, switching when the device starts up. This time tss depends on many parameters, among them transformer design, output capacitor, soft start function and
IDD is the current consumption on the VDD pin when switching. Refer to the specified IDD1 and IDD2 values.
tss is when the device starts switching. The worst case is usually at full load.
vddhyst is the voltage hysteresis logic for uvlo. Refer to the minimum specified value. The soft-start function can also be used as a compensation network through a simple capacitor. In this case, the regulation loop bandwidth is low because of the large value of this capacitor.

Characteristics of high voltage current sources at startup

Used it's a mix of high-performance nets and separate high-value software start-up capacitors. Soft-start time and regulation loop bandwidth can be adjusted independently. If the device is intentionally turned off with the comp pin grounded, the device also performs a boot cycle and the VDD voltage is oscillating between vddon and vddoff. This voltage can be used to provide external functions if their consumption does not exceed 0.5mA. Figure this feature, lock off. Once the "shutdown" signal has been activated, the device is far from the input voltage. Transconductance Error Amplifier viper100/100a includes a transconductance error amplifier. Transconductance gm is the change in output current (icomp) with the change in input voltage (VDD). Therefore: gm = icon video display output impedance zcomp amplifier (comp pin) can be defined as: zcomp = vcomp icomp = 1 mm x vcomp video display The last equation shows that the open loop gain avol can be related to gm and zcomp: avol = gm x zcomp where viper100/100a has a gm value of 1.5ma/v typically. gm is well defined, but zcomp is therefore subject to tolerance.
Simple resistors are connected to the comp pins. The unloaded transconductance error amplifier shows an internal zcomp of about 330 kΩ. More complex impedances can be connected at comp pin laws to achieve different compensations. The capacitor will provide an integrator function, thereby eliminating DC static errors, and the series resistor will ensure correct phase margin at higher frequencies. This additional noise filtering typically requires a 2.2nF capacitor to avoid any high frequency interference.
It would also be interesting to implement a ramp with a compensated duty cycle greater than 50% for continuous operation. such a configuration. Note that r1 and c2 construct the classical compensation network, and q1 is the polarity of the sawtooth with the correct oscillator.
External Clock Synchronization: The OSC pin provides synchronization capability when connected to an external frequency source.

Adjust the schematic diagram according to the specific situation. If using the suggested schematic, the pulse duration must be kept low (500ns is sufficient) to minimize consumption. This optocoupler must be able to provide 20mA through the phototransistor.
The primary peak current limits the primary Idpeak current, so as a result, a simple circuit that can be used. The circuit is based on q1, r1 and r2 clamping voltages used to limit the main peak comp pin device current value:
Idpeak=vComp 8722 ; 0.5vComp=0.6 x r1+r2 The recommended value for r2r1+r2 is 220 kΩ. Over-temperature protection: Over-temperature protection is based on chip temperature sensing. The minimum junction overtemperature cut-off temperature that occurs is 140oC and the typical value is 170oC. When the junction temperature decreases to the restart temperature threshold is usually 40oC below the turn-off value.

Recommended layout

Layout Considerations A few simple rules ensure switching power supplies. They can be classified into two categories: - Minimizing the power loop: The way the switch must be carefully analyzed the power current and the corresponding path must show the smallest possible inner loop area. This avoids radiated EMC noise, conducted EMC noise through magnetic coupling, and provides elimination of parasitic, efficiency-enhancing inducers, especially on the second side. - Use a different track strong for low level signals. Interfering signal and power instability caused by mixing and/or equipment under severe power surges (input overvoltage, output short circuit.... In case of Viper, these rules apply. Loops C1-T1-U1, C5-D2- T1, C7-D1-T1 must be minimized. C6 must be as close as possible from T1. Signal components C2, ISO1, C3 and C4 are connected directly to the source of the device using dedicated rails.