Features: Fully integrated single-cell high-efficiency charger Li-Ion and Li-Polymer battery pack power path circuitry ensures fast system startup When VBUS is connected, battery power is less than 1.55 Maximum charge current Float voltage accuracy: ± at -25°C 0.5% - 0 to 125 °C ±1% input and charge current regulation accuracy ±5% Temperature sensing input prevents auto-charging jeita compliance Thermal regulation and shutdown 4.2 V at 2.3 A production test mode 5 V, 500 mA USB OTG Boost Mode 28V Absolute Maximum Input Voltage 6V Maximum Input Operating Voltage Programmable via High Speed I2C Interface (3.4 MB/s) with Fast Mode and Compatibility - Input Current - Fast Charge/Termination Current - Float Charge Voltage-termination enable 3 MHz synchronous buck PWM controller Wide duty cycle range Small size 1 μh External inductor Safety timer with reset control Dynamic input voltage control Low battery current when charger is not operating

Applications: Cell Phones, Smartphones, PDAs, Tablets, Portable Media Players, Gaming Devices, Digital Cameras

Description: The Fan5404x family includes i2C controlled 1.55 A compliant switch mode chargers with power path operation and USB OTG enhanced operation. Integrated with the charger, the IC supports production test mode and provides a maximum current of 2.3 A for a 4.2 volt system. To facilitate quick system start-up, the IC includes a power path circuit that disconnects the battery from the system rail, ensuring that the system can quickly start the VBUS connection. Power path circuitry ensures that when the charger is plugged in, the system rails remain in place, even if the battery is dead or shorted. The charging parameters and working mode are programmable through the i2 C interface, and the operation can reach 3.4 Mbit/s. The charger and boost regulator circuit is 3 MHz to minimize the size of external passive components. The FAN5404X provides three-phase battery charging: regulated, constant current and constant voltage. This IC automatically restarts the charge cycle when the battery falls below the voltage threshold. If the input power is disconnected, the IC enters a high impedance mode preventing battery current from leaking to the input. The charging status is reported to the host C port via the i2. Dynamic input voltage control prevents W EAK adapter voltage collapse, ensuring the charging capability of such adapters. Fan 5404X has 25 bumps, 0.4mm spacing, WLCSP package.

Circuit Description/Overview When charging a battery with a limited current input source, such as USB, the high efficiency of a software itch charger exceeds the output voltage range with minimal charge time. The FAN5404x incorporates a highly integrated synchronous buck regulator charged with a synchronous boost regulator, which can supply 5V to mobile USB (OTG) peripherals. The FAN5404X uses a synchronous rectifier charger and boost regulator to maintain high efficiency over a range of battery voltage and state of charge. FAN5404X has four working modes: 1. Charging mode: charging single-cell Li-ion or Li-polymer battery. 2. Boost Mode: Provides 5V power to USB-OTG with integrated synchronous rectifier boost regulator, using battery as input. 3. High Impedance Mode: During this process, both the boost and charging circuits are disconnected. From VBU to battery or from battery in this mode, VBUS is blocked. This mode consumes very little current from VBU or battery. 4. Production Test Mode This mode provides 4.2 V output on VBAT and supplies up to 2.3A load current. Charging Mode In charging mode, FAN5404X adopts six regulation loops: 1. Input current: limit from vbus. This current is sensed internally and can be programmed via the i2C interface.

2. Charging current: limit the maximum charging current. This current is sensed by the mosfet with internal sensing. 3. VBUS voltage: This loop is designed to prevent the input source from being dragged below the vbuslim (usually 4.5 V) W when the input supply current is limited. A travel charger is one example. This loop reduces the current w as vbus approaches vbuslim, allowing the input source to operate at the current limit. 4. Charging voltage: The regulator is limited to exceeding this voltage. As the internal battery voltage rises, the battery's internal impedance works in conjunction with the charging voltage regulator to reduce the amount of current flowing into the battery. When the current passes through, the battery is charged to the 4th quarter below the ITERM threshold. 5. Power path: When vbat is lower than vbatmin, Q4 operates as a linear current source and regulates its current to ensure that the voltage on the system remains above 3.4 V. 6. Temperature: If the junction temperature of the IC reaches 120°C, reduce the charging current until the IC temperature is below 120°C. Battery Charge Profile If the battery voltage is below VShort, the linear current source precharges the battery until VBAT reaches Vshort. The pulse width modulation then activates the charging circuit and charges the battery using a constant current if there is enough input power. The current slew rate is limited to prevent overshoot. The FAN5404X is designed to work as an input source for vbus with limited current. During the current conditioning phase, the IBuslim or programmed charge current limits the amount of current available to charge the battery and start the system. The impact of Ibslim on iCharge is shown in the picture.

Assuming that VOREG is programmed to the cell's charging "float" voltage, the battery accepts a current band limiting its output pwm regulator (sense at vbat) until VOREG falls and the charger enters the voltage charge regulation phase. When the current drops to the programmed iterm value, the charge cycle is complete. This can be done by resetting the TE bit (reg1[3]). The charger output or "float" voltage can be programmed with the OREG bits from 3.5 V to 4.44 V in 20 mV increments, as n shown in Table 4. Subsequent charging parameters are programmable for the host via i2C:

When the charge current is below iterm; pwm charging stops, but the status pin remains low. Then the stat pin goes high and the status bit changes to charging complete (10), provided the battery and charger are still connected. A post-charge function, "top-up" charging, can be used to continue charging the battery to a lower ER charge current to maximize battery capacity. The PC bit must be set to 1 for the normal charging current Iterm before the battery charging current reaches the terminal. The post-charge termination current is set by the PC_it[2:0] bits, as shown in Table 6. If PC_en is set to 1, it ends as before after normal charging, and the post-charge starts at PC U on the monitor bits Set to 1. Once the current reaches the post-charge completion threshold, the PC on the PWM charge stop bit changes back to 0. After charging, the STAT pin is high, indicating that the charging current is below the iterm level. To charge after exit, one of the following must be followed: VBUS POR, pok-b cycle drill cycle when vbat < 3.0v or ce or hz mode. When the safety timer charging begins, the IC starts the 15-minute timer (15 minutes). When the timer times out, charging is terminated. Writing to any register C via i2 stops and resets the T15min timer, which in turn starts the 32-second timer (T32s). Setting the tmr_rst bit (reg0[7]) resets the t32s timer. If the T32 timer times out; charging is terminated, the registers are set to their default values, and then use the default values when the T15min timer was running.

Normal charging is run by the host with T32S timer control to ensure the host is active. Run with T15min timer. If the 15 minute timer expires, the IC will shut down the charger and indicate a timer fault (110) on the fault bit (reg0[2:0]). If the host cannot reset the T32S timer. 256 ms after the vbus-por/incompatible charger refuses to connect to the vbus, the ic pulses to the stat pin and sets the con bit of the vbus. Before starting supply, the IC applies a 110Ω load from VBUS to GND. The VBU must remain above VIN (minimum) 1 and below VIN (minimum) 1 before the IC starts charging or providing power to the system. The vbus verification sequence usually occurs before valid current is drawn from VBU (eg, initiated after VBUS ovp failure or VRCH recharging). tvbus effectively ensures that unfiltered 50/60 Hz chargers and other non-compliant chargers will be rejected. The USB friendly boot sequence is at vbus por, the battery threshold (VLOWV) when the battery voltage is above the peak value; the IC is set according to its i2C register. if vbat

When vbat reaches vbatmin, Q4 is turned off and used as a current sensing element that limits iCharge according to I2 C register is set by limiting the current of the pwm modulator (full pwm mode). In PWM mode, if the system drops more than 5mV below VBAT, Q4 and Q5 (VTHSYS) turn on (the gate is pulled low). Once the system voltage is above VBAT, Q5 turns off and Q4 again acts as the current sensing element limiting the iocharge. When the IC goes to sleep, both Q4 and Q5 are on mode (vbus 3.0v, at which point the IC goes into power path charging mode. Dead battery start at vbus por, apply a 2 kΩ load to vbat for 256 ms to discharge any remaining system capacitance when the battery is absent or its discharge protection switch is open. if vbat

If the battery voltage exceeds 3.7 volts within 32 milliseconds when PWM charging begins, the battery is absent. Absence detected by IF battery: 1. Status pulse, fault bit set to 111, and no bit set. 2. For FAN54040 only; T15min timer is disabled until VBU is removed, idle state is entered, and pok is still high. 3. The IC bypasses the protection switch below the itching test because there is no battery. Fan 54042 and fan 54047 continue to charge. If VBAT remains below 3.7 volts for the first 32ms, power path mode charging continues Make sure the battery discharge protection switch exits POWER path mode before closing: 1. If vbat is less than 3.4v, vsys is set to 4v and power path charging continues , until VBAT exceeds 3.4 V to charge for at least 128 ms, until: 2. VBAT has dropped below 3.2 V for at least 32 ms. Once this happens, vsys falls back to the oreg register setting (default is 3.54 V). 3.vbat is again higher than vbatmin by at least 4ms. After these three events, pwm mode is entered, and the ic sets the dbat_b bit. If the host sets the dbat bit (reg2[1]), events 1 and 2 above are skipped and PWM is entered once vbat rises above vbatmin. In a typical application, as soon as the host processor clears its uvlo threshold (usually 3.3v), the host's low soft-switch will set the IbuSlim and IoCharge registers above vbatmin to charge the battery faster once the host determines Over 100 mA is provided through the VBU (see diagram). Once the host processor starts writing to the IC and the charging parameters are set by the host, the host must continuously reset the T32S timer to use the programmed continue charging charging parameters. If t32s times out; register defaults are loaded, fault bits are set to 110, stat pulses, and charging continues with default charging parameters in T15min mode for fan 54040, fan 54042, and fan 54047. The pok_b pins and bits are used to allow the device to work fully to the baseband processor with a strong enough battery. POK UB is high whenever the IC is running in POW ER PATH mode. Regarding exiting POW ER PATH mode, POK UB remains high until VBAT>VLOWV. reg1[5:4] sets the vlowv threshold. The stat pin pulses when the pok_b pin changes.

High Speed (HS) Modes High Speed (hs), Low Speed (ls) and Fast (fs) modes are the same except the bus speed is 3.4mhz for hs mode. The bus enters high speed mode after the host starts to send the hs host code 00001xxx condition. Master codes are sent in fast or fast plus mode (clocks less than 1 MHz); slaves do not return transmissions. The master then generates a repeated START condition (Figure) causing all slaves on the bus to switch to HS mode. The host then sends the i2C packet, as described above, using the hs-mode clock frequency and timing. The bus remains in high speed mode until the stop bit (figure) In hs mode, packets are separated by repeated START conditions (figure).

The sequential write (figure) slave address, register address and first data byte are transferred to the fan5404x byte write (figure) in the same way as in. How, instead of generating a STOP condition, the master sends an extra byte to be written after the falling edge of the eighth bit of the sequential register. After the last byte written and its ack received bit, the master issues a stop bit. The IC contains an 8-bit counter, which is written at every byte. Sequential Read (Graph) Sequential Read starts in the same way as Single Byte Read (Graph), but once the slave transmits the first data byte, the master issues an acknow ledge instead of a stop state. This will instruct the slave's i2C class to send the logic for the next sequentially addressed 8-bit WORD. The FAN5404X contains an 8-bit counter that increments the address pointer after each byte is read, which allows the contents of memory to be read during an i2C transaction.