feature

-3 dB bandwidth, 2.2 GHz, AV=12 dB; single-resistor programmable gain: 0dB≤AV≤26dB differential interface; low noise input stage 2.7 nV/√Hz, AV=10 dB; low harmonic distortion; -79 dBc seconds, frequency 70 MHz; -81 dBc, third at 70 MHz; oip3 of 31 dBm at 70 MHz; single supply operation: 3 V to 5.5 V Low power consumption: 28 mA at 5 V; adjustable output total Mode voltage; fast settling and overspeed recovery; conversion rate 13000v/μs; power-off capability.

application

Differential ADC driver; single-ended to differential conversion; IF sampling receiver; RF/IF gain block; SAW filter interface.

General Instructions

The AD8351 is a low-cost differential amplifier that can be used in RF and IF applications up to 2.2GHz. Using an external gain resistor, the voltage gain can be set from unity to 26dB. The AD8351 provides a nominal 150Ω differential output impedance. The device has excellent distortion performance and low noise characteristics, and has wide application prospects.

The AD8351 is designed to meet the high performance requirements of communications transceiver applications. The device can function as a general-purpose gain block, adc driver, and high-speed data interface driver. The AD8351 can also be used as a single-ended differential amplifier with its distortion products in a differential configuration. The exceptionally good distortion performance makes the AD8351 an ideal solution for 12-bit and 14-bit IF sampling receiver designs.

Manufactured on Analog Devices' high-speed XFCB process, the AD8351 provides high bandwidth with high frequency performance and low distortion. The quiescent current of the AD8351 is typically 28 mA. The AD8351 amplifier is available in a compact 10-lead MSOP or 16-lead LFCSP package and operates over the -40°C to +85°C temperature range.

Typical performance characteristics

V=5 V, T=25°C unless otherwise noted.

theory of operation

basic concept

Differential signaling is used in high-performance signal chains where distortion performance, signal-to-noise ratio, and low power consumption are key. Differential circuits inherently provide improved common-mode rejection and harmonic distortion performance, as well as better immunity to interference and ground noise.

Figure 33 illustrates the expected input and output waveforms for a typical application. Typically, the applied input waveform is a balanced differential drive, where the signals applied to the inhi and inlo pins are equal in amplitude and 180° out of phase. In some applications, baluns can be used to convert single-ended drive signals to differential signals. The AD8351 can also be used to convert single-ended signals to differential signals.

Gain adjustment

The differential gain of the AD8351 is set using an external resistor, R, connected between the RGP1 and RGP2 pins. Using the resistor values specified in Figure 5, the gain can be set to any value between 0 dB and 26 dB. Common gain values are shown in Table 4. The board used to connect the external gain resistors must be balanced and as short as possible to help prevent noise pickup and ensure balanced gain and stability.

The low frequency voltage gain of the AD8351 can be modeled as:

Among them, the right F type is 350Ω (internal); the right one is a single-ended load resistance. R is the gain setting resistor.

Common mode regulation

The output common-mode voltage level is the DC offset voltage present at each differential output. AC signals have the same amplitude and 180° phase difference, but are concentrated at the same common-mode voltage level. As shown in Figure 34, the common mode output voltage level can be adjusted from 1.2v to 3.8v by driving the desired voltage level into the vocm pin.

Input and output matching

The AD8351 provides a moderately high differential input impedance of 5 kΩ. In practice, the input of the ad8351 is terminated to a lower impedance to provide impedance matching the drive source, as shown in Figure 35. Place the termination resistor R as close as possible to the input pins to minimize reflections due to impedance mismatches. The 150Ω output impedance may need to be converted to provide the desired output matched to a given load. Matching components can be calculated using Smith charts, or resonance methods can be used to determine matching networks that lead to complex conjugate matching. Input and output impedances and reflection coefficients are shown in Figure 22, Figure 23, Figure 24, and Figure 25.

Figure 35 shows the Surface Acoustic Wave (SAW) filter interface. Many SAW filters are differential in nature, allowing low loss output matching. In this example, the saw filter requires a source impedance of 50Ω to provide the desired center frequency and q. The series l parallel c output network provides an impedance transformation of 150Ω to 50Ω at the desired operating frequency. The impedance transformation is shown in the Smith chart in Figure 36.

Single-ended saw filters can be driven by connecting the unused outputs to ground with appropriate termination resistors. The overall gain of the system is reduced by 6db because only half of the signal is available for the input of the saw filter.

Single-ended differential operation

The AD8351 can be easily configured as a single-ended to differential gain block, as shown in Figure 37. The input signal is AC coupled and applied to the inhi input. Unused inputs are AC coupled to ground. The values of C1 to C4 are chosen so that their reactances are negligible at the desired operating frequency. To balance the output, an external feedback resistor, r, is required. To select gain and feedback resistors, see Figure 38 and Figure 39. From Figure 38, choose an R for the desired gain in decibels at a given load. Next, select an R resistor from Figure 39 as the selected R and load.

Although the differential balance is not perfect in this case, the distortion performance is still impressive. Figure 13 and Figure 14 show the second and third harmonic distortion performance when driving the input of the AD8351 with a single-ended 50Ω supply.

ADC driver

The circuit in Figure 40 shows the AD8351 driving the AD6645, which is a 14-bit, 105 msps ADC. For optimum performance, the AD6645 and AD8351 are differentially driven. Resistors r1 and r2 provide 50Ω differential input impedance to the power supply, and r3 and r4 provide isolation from the analog to digital inputs. The gain setting resistor for the AD8351 is R. The AD6645 provides a 1 kΩ differential load to the AD8351, requiring 2.2 V PP for the differential signal between AIN and AIN for the full-scale output. This AD8351 circuit then provides gain, isolation and source matching for the AD6645. The AD8351 also provides a balanced input to the AD6645 instead of BARUN, which is critical for second-order cancellation. The signal generator is bipolar, centered on ground. Connecting the VOCM pin of the AD8351 (pin 10 on MSOP and pin 13 on the LFCSP) to the VREF pin of the AD6645 sets the common-mode output voltage of the AD8351 to 2.4V. This voltage is bypassed with a 0.1µF capacitor. Increasing the gain of the AD8351 increases system noise, thereby reducing the signal-to-noise ratio, but does not significantly affect distortion. The circuit in Figure 40 can provide SFDR performance better than -90 dBc at 10 MHz input and better than -80 dBc at 70 MHz input at 10 dB gain.

The circuit in Figure 41 represents the single-ended input to differential output configuration of the AD8351 driving the AD6645. In this case, r1 provides the input impedance. R is the gain setting resistor. Resistor R is required to balance the output voltage required for AD6645 second-order cancellation and can be selected using the diagram (see the Single-Ended to Differential Operation section). The circuit shown in Figure 41 can provide SFDR performance better than -90 dBc at 10 MHz input and better than -77 dBc at 70 MHz input.

analog multiplexing

In applications where multiple high-speed signals need to be selected, the ad8351 can be used as an analog multiplexer. When disabled (PWUP pin pulled low), each device provides approximately 60 dBc of isolation with a maximum input level of 0.5 VPP to 100 MHz. The low output noise spectral density allows for a simple implementation as shown in Figure 42. The pwup interface can be easily driven using most standard logic interfaces. By using an n-bit digital interface, up to n devices can be controlled. When using a large number of input signal paths, output loading effects and noise need to be considered. Each disabled AD8351 presents approximately a 700Ω load in parallel with the 150Ω output source impedance of the enabled device. With the addition of n devices, the load increases and the distortion performance decreases. The four devices are mixed in a 1kΩ load and can achieve better than -70dbc distortion at signal frequencies up to 70mhz.

I/O capacitive load

Input or output direct capacitive loads greater than a few picofarads can cause excessive peaking and/or out-of-band ringing. This is due to the parallel resonance of the package and bond wire inductances with the input/output capacitance of the device and the associated coupling created internally through the ground inductance. For low-resistance loads or source resistances, the effective q is lower, allowing higher relative capacitance to be terminated or terminated before ringing or excessive peaking occurs. These effects can be eliminated by adding series input resistance (R) for high source capacitance or series output resistance (ROP) for high load capacitance. In general, when the I/O capacitive load is greater than ~2pF, it only needs to be less than 25Ω. The higher the c, the smaller the r parasitic suppression resistance required. Additionally, R helps reduce low-gain in-band peaking, especially with lightly resistive loads.

Due to package parasitic capacitance on the R port, a high R value (low gain) results in excessive AC peaking in the passband, resulting in instability in the time domain. For example, when driving a 1kΩ load, if R is 25Ω, then R is equal to 200Ω (A = 10dB), and the peak is reduced by about 7dB (see Figure 44).

It is important to keep all I/O, ground, and R port traces as short as possible. Additionally, the ground plane must be removed from the package. Since the device gain is inversely proportional to the value of the r resistor, any parasitic capacitance on the r port will cause high frequency gain peaking. Following the precautions outlined in Figure 45 can help reduce parasitic board capacitance, thereby extending the bandwidth of the device and reducing potential peaking or ringing.

transmission line effect

As mentioned earlier, stray transmission line capacitance, combined with package parasitics, can form resonant circuits at high frequencies, resulting in excessive gain peaking. rThe design of the transmission lines connecting the input and output networks must minimize stray capacitance. The output single-ended source impedance of the AD8351 is dynamically set to a nominal value of 75Ω. Therefore, for the matched load termination, the characteristic impedance of the output transmission line is designed to be 75Ω. In many cases, the final load impedance can be relatively high, greater than 1kΩ. It is recommended that the board be designed as shown in Figure 45 under high impedance load conditions. In most practical board designs, this requires that the size of the printed circuit board traces be small (about 5 mils) and that the bottom layer and the adjacent ground plane be far enough apart to minimize capacitance.

Typically, the drive source impedance into the device is lower and terminating resistors are used to prevent input reflections. Transmission lines must be designed with appropriate characteristic impedance in the low z region. The high-impedance environment between the termination resistor and the device input pins must not have a ground plane under or near the signal traces. Small parasitic suppression resistors may be necessary at the device input pins to help desensitize (de-q) the effects of resonance, device bond wires and surrounding parasitic plate capacitances. Typically, 25Ω series resistors (size 0402) provide sufficient decoupling of the input system without significantly degrading AC performance.

Figure 46 illustrates the value of adding input and output series resistors to help eliminate resonant effects of board parasitics. Simply increasing r and r can significantly reduce overshoot and overshoot.

role settings

The test circuit used for 150Ω and 1kΩ load testing is shown in Figure 47. Evaluation boards use balun transformers to simplify interfacing with single-ended test equipment. The balun effect must be eliminated from measurements to accurately characterize device performance at frequencies above 1 GHz. The output L-PAD matching network provides broadband impedance matching with minimal insertion loss. The input line is terminated with a 50Ω resistor for input impedance matching. When attempting to measure device gain, the power losses associated with these networks must be considered.

Evaluation Committee

An evaluation committee is available for the experiment. Various parameters, such as gain, common mode level, input and output network configuration, can be modified with small resistance changes. A schematic and evaluation board diagram are shown in Figure 48, Figure 49, and Figure 50.