feature

Two fast 14-bit ADCs ; four input channels; simultaneous sampling and conversion; 5.2 second conversion time; single-supply operation; selection of input ranges; V to 2.5 V; high-speed parallel interface; low power, 70 mW (typ); power-save mode, 105 watts maximum; analog input overvoltage protection; 14-bit lead compatible upgrade to AD7862.

application

AC motor control; uninterruptible power supplies; data acquisition systems; communications.

General Instructions

The AD7863 is a high speed, low power, dual 14-bit A/D converter that operates from a +5 V supply. This section contains two 5.2 successive approximation ADCs, two track/hold amplifiers, an internal +2.5 V reference, and a high-speed parallel interface. The four analog inputs are divided into two channels (A and B), selected by the a0 input. Each channel has two inputs (va1 and va2 or vb1 and vb2) that can be sampled and converted at the same time, thereby preserving the relative phase information of the signals at the two analog inputs. The part accepts analog input ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V–2.5 V (AD7863-2). Overvoltage protection on the part's analog inputs allows input voltages to reach ±17 V, ±7 V, or +7 V, respectively, without damage.

A single conversion start signal (convst) puts both tracks/holds on hold simultaneously and initiates conversions on both channels. The busy signal indicates the end of the conversion, and the conversion results of the two channels can be read at this time. The first read after the conversion accesses the result from either va1 or vb1, while the second read accesses the result from either va2 or vb2, depending on whether the muxer selects a0 to be low or high, respectively. Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals.

In addition to traditional DC accuracy metrics such as linearity, gain, and offset error, this section specifies dynamic performance parameters including harmonic distortion and signal-to-noise ratio.

The AD7863 is fabricated using the Analog Devices Linear Compatible CMOS (LCmos) process, a hybrid process that combines precision bipolar circuitry with low-power CMOS logic. It is available in 28 lead SOIC and SSOP.

Product Highlights

1. The AD7863 has two complete ADC functions, allowing simultaneous sampling and conversion of two channels. Each adc has a dual channel input mux. After the conversion is initiated, the conversion result for both channels is 5.2 microseconds.

2. The AD7863 is powered by a +5 V power supply with a typical power consumption of 70 mW. An automatic power-down mode, where the part goes into a power-down state after a conversion is complete and "wakes up" before the next conversion cycle, makes the AD7863 ideal for battery-powered or portable applications.

3. This part provides a high-speed parallel interface for easy connection with microprocessors, microcontrollers and digital signal processors.

4. There are three versions of this part with different analog input ranges. The AD7863-10 provides a standard industrial input range of ±10 V; the AD7863-3 provides a common signal processing input range of ±2.5 V, and the AD7863-2 can be used in unipolar 0 V–2.5 V applications.

5. This section features a very tight aperture delay match between the two input sample-and-hold amplifiers.

term signal-to-noise ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals up to half the sampling frequency (fs/2), except DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio of an ideal n-bit converter with a sine wave input is:

So for a 14 bit converter this is 86.04db.

total harmonic distortion

Total Harmonic Distortion (thd) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7863, the definitions are as follows:

where are the rms amplitude of the fundamental and the rms amplitudes of the second to fifth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. An intermodulation term is a term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7863 is tested with two input frequencies. In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dbs.

Isolation between channels

Inter-channel isolation is a measure of the level of cross-talk between channels. It is measured by applying a full-scale 50 kHz sine wave signal to all non-selected channels and determining how much the signal is attenuated in the selected channel. The numbers given are the worst of all channels.

Relative accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line through the endpoints of the ADC transfer function.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

Positive Gain Error (AD7863-10, 10 V, AD7863-3, 2.5 V)

This is the deviation of the last code transition (01). ...110-01. ...111) After adjusting for bipolar offset error from ideal 4 × VREF–1 LSB (AD7863-10 ±10 V range) or VREF–1 LSB (AD7863-3, ±2.5 V range).

Positive Gain Error (AD7863-2, 0 V to 2.5 V)

This is the deviation of the last code transition (11). ...110 to 11. ...111) from ideal VREF – 1 LSB, after adjustment for unipolar offset error.

Bipolar Zero Error (AD7863-10, 10 V, AD7863-3, 2.5 V) This is the deviation of the mesoscale transition (from 0 to 1) from the ideal 0v (agnd).

Unipolar Offset Error (AD7863-2, 0 V to 2.5 V) This is the deviation of the first code transition (00). ... 000 to 00. ...001) from ideal agnd + 1 lsb.

Negative Gain Error (AD7863-10, 10 V, AD7863-3, 2.5 V)

This is the deviation of the first code transition (10). ... 000 to 10. ...001) After adjusting for bipolar zero error, from ideal –4 × VREF + 1 LSB (AD7863-10 ±10 V range) or –VREF + 1 LSB (AD7863-3, ±2.5 V range).

Track/Hold Acquisition Time

Track/Hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1/2 lsb) after the conversion ends (the point at which the track/hold returns to track mode). It is also suitable for cases where there is a change in the selected input channel, or where there is a step input change in the input voltage applied to the selected vax/bx input of the AD7863. This means that the user must wait for the duration of the track/hold acquisition time after a conversion ends or after a channel change/step input change to vax/bx before starting another conversion to ensure the part is operating to specification.

Converter Details

The AD7863 is a high speed, low power, dual 14-bit A/D converter that operates from a +5 V supply. This section contains two 5.2-step successive approximation ADCs, two track/hold amplifiers, an internal +2.5 V reference and a high-speed parallel interface. The four analog inputs are divided into two channels (A and B), selected by the a0 input. Each channel has two inputs (va1 and va2 or vb1 and vb2) that can be sampled and converted at the same time, thereby preserving the relative phase information of the signals at the two analog inputs. The part accepts analog input ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V–2.5 V (AD7863-2). Overvoltage protection on the part's analog inputs allows input voltages to reach ±17 V, ±7 V, or +7 V, respectively, without damage. AD7863 has two working modes, high sampling mode and automatic sleep mode. After the conversion is completed, the part automatically enters the sleep state. These modes are discussed in detail in the Timing and Control section. Conversions are initiated on the AD7863 by pulsing the convst input. On the falling edge of convst, both on-chip tracks/holds are placed in hold simultaneously and a conversion sequence is initiated on both channels. The conversion clock for this part is generated internally using a laser trimmed clock oscillator circuit. The busy signal indicates the end of the conversion, and the conversion results of the two channels can be read at this time. The first read after conversion accesses the result from va1 or vb1, while the second read accesses the result from va2 or vb2, depending on whether the multiplexer selects a0 low or high, respectively, before starting the conversion. Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals.

In high sampling mode, the AD7863 has a conversion time of 5.2 microseconds (10 microseconds in auto-sleep mode) and a track/hold acquisition time of 0.5 microseconds. For best performance from the part, read operations should not occur during a conversion or during the 400 ns before the next conversion. This allows the part to operate at throughputs up to 175 kHz and meet data sheet specifications.

track/hold segment

The track/hold amplifier on the AD7863 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. The input bandwidth of track/hold is greater than the Nyquist rate of the ADC, even when the ADC operates at its maximum throughput rate of 175 kHz (ie, track/hold can handle input frequencies in excess of 87.5 kHz).

The track/hold amplifier acquires the input signal to 14-bit accuracy in less than 500 ns. The operation of tracking/holding is basically transparent to the user. The two track/hold amplifiers simultaneously sample their respective input channels on the falling edge of convst. The aperture time of the track/hold (ie the delay time between the external convst signal and the track/hold actually entering the hold) is well matched between the two track/holds on one device, and also between devices ground match. This allows relative phase information between different input channels to be accurately preserved. It also allows multiple ad7863s to sample more than two channels simultaneously. At the end of the conversion, the part returns to its tracking mode. The acquisition time for the track/hold amplifier begins at this point.

Reference chapter

The AD7863 includes a single reference pin, labeled VREF, that provides access to the part's own +2.5V reference, or connects to an external +2.5V reference to provide the part's reference voltage source. This part is specified as a +2.5 V reference. Errors in the reference source will cause gain errors in the AD7863 transfer function and will add to the full-scale errors specified on the part. On the AD7863-10 and AD7863-3, it will also cause offset errors to be injected in the attenuator stage.

The AD7863 includes an on-chip +2.5V reference. To use this reference as a reference source for the AD7863, simply connect two 0.1µf disc ceramic capacitors from the VREF pin to AGND. The voltage appearing on this pin is buffered internally before being applied to the ADC. If the reference needs to be used external to the AD7863, it should be buffered because the part has a FET switch in series with the reference output, resulting in a nominal 5.5 kΩ source impedance for this output. At 25°C, the internal reference tolerance is ±10 mV, the typical temperature coefficient is 25 ppm/°C, and the maximum error is ±25 mV.

If the application requires a reference with tighter tolerances or the AD7863 needs to be used with a system reference, the user can choose to connect an external reference to this VREF pin. The external reference will effectively drive the internal reference, thus providing the reference source for the ADC. The reference input is buffered before being applied to the ADC, with a maximum input current of ±100µA. A suitable reference source for the AD7863 is the AD780 precision +2.5 V reference.

Circuit Description Analog Input Section

The AD7863 is divided into three types: AD7863-10 (handling a ±10 V input voltage range), AD7863-3 (handling a ±2.5 V input voltage range), and AD7863-2 (handling a 0 V to +2.5 V input voltage range).

Figure 3 shows the analog input section of the AD7863-10 and AD7863-3. The analog input range of the AD7863-10 is ±10 V, and the input resistance is typically 9 kΩ. The analog input range of the AD7863-3 is ±2.5 V, and the input resistance is typically 3 kΩ. This input is benign, with no dynamic charging current because the resistive stage is followed by the high input impedance stage of the track/hold amplifier. For the AD7863-10, r1=8 kΩ, r2=2 kΩ, and r3=2 kΩ. For AD7863-3, r1=r2=2 kΩ, r3 is open.

For the AD7863-10 and AD7863-3, the designed transcoding occurs on consecutive integer lsb values (ie, 1 lsb, 2 lsb, 3 lsb). …). The output encoding is two complementary binary, lsb=fs/16384. Ideal input/output transfer function for the AD7863-10 and AD7863-3.

Offset and full scale adjustment

In most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. With AC coupling, offset errors in the analog domain can be eliminated. The full-scale error effect is linear and should not cause a problem as long as the input signal is within the full dynamic range of the ADC. Some applications always require the input signal to span the entire analog input dynamic range. In this application, the offset and full-scale errors must be adjusted to zero.

Figure 4 shows a typical circuit that can be used to adjust the offset and full-scale error on the AD7863 (VA1 on the AD786310 version is for example purposes only). When adjustment is required, the offset error must be adjusted before the full-scale error. This is accomplished by trimming the offset of the op amp driving the AD7863's analog input when the input voltage is 1/2 lsb below analog ground. The trimming procedure is as follows: Apply a voltage of -0.61 mV (–1/2 lsb) at v1 in Figure 4 and adjust the op amp offset voltage until the ADC output code is between 11 1111 1111 1111 and 00 0000 0000 0000 0000 flashing.

Gain error can be adjusted at the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trimming procedure in both cases is as follows:

Positive full scale adjustment (-10 version)

A voltage of +9.9927 V (fs/2–1 lsbs) was applied at v1. Adjust r2 until the adc output code flashes between 01 1111 1111 1110 and 01 1111 1111 1111.

Negative full scale adjustment (-10 version)

Apply a voltage of -9.9976 V (–fs + 1 lsb) at v1 and adjust r2 until the ADC output code flashes between 10 0000 0000 0000 and 10 0000 0000 0001.

An alternative to adjusting the full-scale error in systems using an external reference is to adjust the voltage at the vref pin until the full-scale error of any channel is adjusted. Good full-scale matching of the channels will ensure small full-scale errors for the other channels.

time and control

Figure 5a shows the timing and control sequence required to obtain optimum performance (mode 1) from the AD7863. In the sequence shown, conversions are initiated on the falling edge of convs. This puts both tracks/holds on hold simultaneously, and new data from this conversion is available in the output registers of the AD7863 for 5.2 microseconds following. The busy signal indicates the end of the conversion, and the conversion results of the two channels can be read at this time. Then start the second conversion. If the multiplexer selects a0 low, the first converted first and second read pulses access the results from channel a (va1 and va2, respectively). The third and fourth read pulses access the results from channel b (vb1 and vb2 respectively) after the second transition and a0 high. The state of a0 can be changed anytime after convst goes high, i.e. before the next falling edge of convst, track/hold goes into hold and 500 ns. Note that during a conversion, if a negative voltage is applied on a non-selected channel that exceeds the input range of the AD7863, a0 should not be changed as this will affect the conversion in progress. Data is read from the part via a 14-bit parallel data bus with standard cs and rd signals, i.e. a read operation consists of a negative going pulse on the cs pin and two negative going pulses on the rd pin (when cs is low ), accessing two 14-bit results. Once a read operation has taken place, a further 400 ns should be allowed before the next falling edge of convst to optimize the track/hold amplifier settings before the next conversion begins. The achievable throughput of the part is 5.2 microseconds (conversion time) plus 100 nanoseconds (read time) plus 0.4 microseconds (quiet time). This results in a minimum throughput time of 5.7 microseconds (equivalent to a throughput rate of 175 kHz).

read options

In addition to the read operations described above and the read operations shown in Figure 5a, other combinations of cs and rd may result in different channels/inputs being read in different combinations. Appropriate combinations are shown in Figures 5b to 5d.

Working Mode Mode 1 working (normal power, high sampling performance)

The timing diagram in Figure 5a is used for optimum performance in operating mode 1, where the falling edge of convst initiates the transition and places the track/hold amplifier into its hold mode. This falling edge of convst also causes the busy signal to go high to indicate that a conversion is in progress. When a conversion is complete, the busy signal goes low for a maximum of 5.2 microseconds after the falling edge of convst, and new data from the conversion is available in the AD7863's output latch. Read operations access this data. If the multiplexer selects a0 low, the first converted first and second read pulses access the results from channel a (va1 and va2, respectively). After the second transition and a0 high, the third and fourth read pulses access the results from channel b (vb1 and vb2, respectively). Data is read from the part via a 14-bit parallel data bus with standard CS and RD signals. This data read operation consists of a negative-going pulse on the CS pin and two negative-going pulses on the RD pin (when CS is low), accessing two 14-bit results. For the fastest throughput, a read operation will take 100 ns. The read operation must complete at least 400 ns before the falling edge of the next convst, which gives a total time of 5.7 microseconds (equivalent to 175 kHz) for the entire throughput time. This mode of operation should be used for high sampling applications.

Mode 2 operation (power off, automatic sleep after transition)

The timing diagram in Figure 6 is for optimal performance in operating mode 2, after a transition, once busy goes low, the part automatically goes into sleep mode and "wakes up" before the next transition. This is achieved by holding convst low at the end of the second conversion and high at the end of the second conversion for Mode 1 operation.

The operation shown in Figure 6 shows how to access data from channels A and B, followed by automatic sleep mode. It is also possible to set the timing so that data is only accessed from either channel A or channel B (see the "Read Options" section) and then enter auto-sleep mode. The rising edge of Const "wakes up" this part. The wake-up time is 4.8 microseconds when using the external reference and 5 milliseconds when using the internal reference, at which point the track/hold amplifier enters its hold mode if convst goes low. After this, the conversion takes 5.2 microseconds, a total of 10 microseconds from the rising edge of convst to the completion of the conversion (external reference, 5.005ms for internal reference), which is indicated by busy going low. Note that since the wake-up time from the rising edge of convst is 4.8 microseconds, if the convst pulse width is greater than 5.2 microseconds, the conversion time from the rising edge of convst will exceed the 10 microseconds shown in Figure 6 (4.8 microseconds wake-up time + 5.2 microsecond conversion time). This is because the track/hold amplifier enters its hold mode on the falling edge of convst and the conversion does not complete within 5.2 microseconds. In this case, being busy will be the best indicator that the conversion is complete. Data can be read from the component even when the component is in sleep mode.

The read operation is the same as in Mode 1 operation and must also complete at least 400 ns before the next falling edge of convst to allow sufficient time for the track/hold amplifier to settle. This mode is useful when the part is transitioning at a slow rate, as the power consumption will be significantly reduced from that of Mode 1 operation.

AD7863 Dynamic Specifications

The AD7863 specifies and tests dynamic performance specifications as well as traditional dc specifications such as integral and differential nonlinearity. These AC specifications are required for signal processing applications such as phased array sonar, adaptive filters, and spectrum analysis. These applications require information about the effect of the ADC on the spectral content of the input signal. Therefore, the parameters specifying the ad7863 include signal-to-noise ratio, harmonic distortion, intermodulation distortion and peak harmonics. These terms are discussed in detail in the following sections.

signal to noise ratio

snr is the signal-to-noise ratio measured at the ADC output. The signal is the rms magnitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals, excluding DC, and has a maximum value of half the sampling frequency (fs/2). The signal-to-noise ratio depends on the number of quantization levels used in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio for a sine wave input is given by:

SNR = (6.02N + 1.76) dB (1), where is the number of bits.

So, for an ideal 14-bit converter, the signal-to-noise ratio is 86.04db.

Figure 7 shows a histogram of 8192 dc input conversions with the AD7863 using a 5 V supply. The analog input is set at the center of the transcoding. It can be seen that the codes appear mostly in one output bin, which shows that the ADC has very good noise performance.

The output spectrum of the ADC is evaluated by applying a very low distortion sine wave signal to the vax/bx input, which is sampled at 175khz. Generates a Fast Fourier Transform (fft) plot from which SNR data can be obtained. Figure 8 shows a typical 8192-point FFT plot of the AD7863 with an input signal of 10 kHz and a sampling frequency of 175 kHz. The signal-to-noise ratio obtained from the figure is -80.72db. Harmonics should be considered when calculating the signal-to-noise ratio.

significant digits

The formula given in Equation 1 relates the signal-to-noise ratio to the number of bits. Rewriting the formula, as in Equation 2, can obtain a performance metric expressed in effective number of bits (n).

A device's effective number of bits can be calculated directly from its measured signal-to-noise ratio.

Figure 9 shows a typical plot of effective bits versus frequency for the AD7863-2 sampled at 175 kHz. The number of significant bits is usually between 13.11 and 11.05, corresponding to snr numbers of +80.68db and +68.28db.

Total Harmonic Distortion (THD)

Total Harmonic Distortion (thd) is the ratio of the rms value of the harmonics to the rms value of the fundamental. For the AD7863, THD is defined as:

where are the rms amplitude of the fundamental and the rms amplitudes of the second to sixth harmonics. The thd is also derived from the fft plot of the adc output spectrum.

Intermodulation Distortion

When the input consists of sine waves of two frequencies (fa and fb), any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2 , 3. ……Wait. The intermodulation term refers to the intermodulation term for which both m and n are not equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dbs. In this case, the input consists of two equal-amplitude, low-distortion sine waves. Figure 10 shows a typical IMD diagram for the AD7863.

Peak harmonics or spurious noise

Harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts of the harmonic buried in the noise floor, the peak will be the noise peak.

DC Linear Graph

Figures 11 and 12 show typical DNL and INL plots for the AD7863.

Power Factor

In auto power-down mode, the part can operate at sample rates much less than 175 kHz. In this case the power consumption will be reduced and depends on the sampling rate. Figure 13 shows a graph of power consumption versus sampling rate from 1 Hz to 100 kHz in auto power-down mode. Conditions are 5 V supply at 25°C.

model

Microprocessor interface

The AD7863 high-speed bus timing allows direct connection to DSP processors as well as modern 16-bit microprocessors. A suitable microprocessor interface is shown in Figures 14 to 18.

AD7863–ADSP-2100 interface

Figure 14 shows the AD7863 and ADSP-2100. The convst signal can be provided by the adsp-2100 or an external power supply. The AD7863 is busy providing an interrupt to the adsp-2100 when the conversion is done on both channels. These two conversion results can then be read from the ad7863 using two consecutive reads to the same memory address. The following instruction reads one of two results:

where 0 is the ADSP-2100 0 register, which is the AD7863 address.

AD7863–ADSP-2101/ADSP-2102 Interface

The interface shown in Figure 14 also forms the basis for the interface between the AD7863 and the ADSP-2101/ADSP-2102. The read line for the ADSP-2101/ADSP-2102 is labeled RD. In this interface, the processor's RD pulse width can be programmed using the data memory wait state control register. The instructions for reading one of the two results are as described in the adsp-2100.

AD7863–tms32010 interface

The interface between the AD7863 and the tms32010 is shown in Figure 15. Again, the convst signal can be provided from the tms32010 or an external source, and the tms32010 is interrupted when both conversions are complete. The following instructions are used to read the conversion result from the AD7863: IN D, ADC

where is the data memory address and is the AD7863 address.

AD7863–tms320c25 interface

Figure 16 shows the interface between the AD7863 and the tms320c25. As with the previous two interfaces, conversions can be initiated from the tms320c25 or an external source, and the processor is interrupted when the conversion sequence is complete. The tms320c25 doesn't have a separate rd output to directly drive the ad7863 rd input. This has to be generated by the processor strb and r/w output, with some logic gates added. The rd signal is combined with the msc signal to provide one wait state during the read cycle required for correct interface timing. Read the conversion result from the AD7863 using the following command: IN D, ADC

where is the data memory address and is the AD7863 address.

Some applications may require that the conversion be initiated by the microprocessor rather than an external timer. One option is to decode the AD7863 convst from the address bus so that the write operation starts the conversion. Data is read at the end of the transformation sequence as before. Figure 18 shows an example of initiating a conversion using this method. Note that for all interfaces it is best not to attempt read operations during conversion.

AD7863–MC68000 interface

The interface between the AD7863 and the MC68000 is shown in Figure 17. As before, conversions can be provided from the MC68000 or from an external source. The AD7863 busy can be used to interrupt the processor, or a software delay can ensure that the conversion has completed before attempting to read the AD7863. Due to the nature of its interrupts, the MC68000 requires additional logic (not shown in Figure 18) to allow it to interrupt properly.

The MC68000 AS and R/W outputs are used to generate separate RD input signals for the AD7863. cs is used to drive the 68000 dtack input to allow the processor to perform normal read operations on the AD7863. Use the following 68000 instruction to read the conversion result: MOVE.W ADC, D0

Where 0 is the 68000 0 register, which is the AD7863 address.

AD7863–80C196 interface

Figure 18 shows the interface between the AD7863 and the 80C196 microprocessor. Here, the microprocessor initiates the conversion. This is achieved by gating the 80c196wr signal with the decoded address output (different from the ad7863 cs address). The AD7863 busy is used to interrupt the microprocessor when the conversion sequence is complete.

Vector Motor Control

The electric current of the motor can be divided into two parts: one part produces the torque, and the other part produces the magnetic flux. For optimum motor performance, these two components should be controlled independently. In traditional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the fundamental control variables. However, both torque and magnetic flux are functions of current (or voltage) and frequency. This coupling effect can degrade the performance of the motor because, for example, if the torque is increased by increasing the frequency, the magnetic flux tends to decrease.

Vector control of an AC motor involves controlling the phase in addition to the drive and current frequency. Controlling the phase of the motor requires feedback from the position of the rotor relative to the rotating magnetic field within the motor. Using this information, the vector controller mathematically converts the three-phase drive currents into individual torque and flux components. The AD7863 is ideal for vector motor control applications.

A block diagram of a vector motor control application using the AD7863 is shown in Figure 19. The position of the magnetic field is determined by determining the current in each phase of the motor. Only two phase currents need to be measured, because if two phases are known, a third current can be calculated. VA1 and VA2 of the AD7863 are used to digitize this information.

Simultaneous sampling is essential to maintain relative phase information between the two channels. A current-sensing isolation amplifier, transformer, or Hall-effect sensor is used between the motor and the AD7863. The rotor information is obtained by measuring the voltages at the two inputs of the motor. VB1 and VB2 of the AD7863 are used to obtain this information. The relative phase of the two channels is equally important. Use dsp microprocessor to carry out mathematical transformation and control loop calculation to the information fed back by ad7863.

Multiple AD7863S

Figure 20 shows a system in which multiple AD7863s can be configured to handle multiple input channels. This configuration is common in applications such as sonar, radar, etc. The AD7863 specifies typical aperture delay limits. This means that the user knows the difference in sampling instants between all channels. This allows the user to maintain relative phase information between different channels.

A common read signal from the microprocessor drives the RD input of all AD7863S. Each AD7863 is assigned a unique address selected by the address decoder. The reference output of AD7863 #1 is used to drive the reference inputs of all other AD7863s in the circuit shown in Figure 20. A VREF can be used to provide a reference to several other AD7863S. Alternatively, an external or system reference can be used to drive all VREF inputs. A common reference ensures good full-scale tracking between all channels.

Application Tips PC Board Layout Considerations

The AD7863 is optimized to achieve the lowest noise performance in terms of both radiated and conducted noise. To complement the AD7863's excellent noise performance, great care must be taken with the PC board layout. Figure 21 shows the recommended connection diagram for the AD7863.

horizon

The AD7863 and associated analog circuitry should have a separate ground plane, called the analog ground plane (AGND). This analog ground plane should include all AD7863 ground pins (including the DGND pin), voltage reference circuits, power supply bypass circuits, analog input traces, and any associated input/buffer amplifiers.

The regular PCB ground plane (called dgnd in this discussion) area should contain all digital signal traces (excluding ground pins) up to the AD7863.

powered aircraft

The PC board layout should have two different power planes, one for the analog circuits and one for the digital circuits. The analog power plane should include the AD7863 (VDD) and all associated analog circuitry. As shown in Figure 21, if necessary, this power plane should be connected to a regular PCB power plane (VCC) at a single point through a ferrite bead. This bead (reference part number: Fair Rite 274300111 or Murata BL01/02/03) should be within three inches of the AD7863.

The PCB power board (VCC) should provide power for all digital logic on the PC board, while the analog power board (VDD) should provide power for all AD7863 power pins, voltage reference circuits, and any input amplifiers (if required). A suitable LNA for the AD7863 is the AD797, one for each input. Make sure the +vs and –vs power supplies of each amplifier are disconnected from the agnd respectively.

PCB power (VCC) and ground (DGND) should not cover parts of the analog power plane (VDD). Keeping the vcc power and dgnd planes not covering the vdd will help reduce plane-to-plane noise coupling.

Power decoupling

Noise on the analog power plane (VDD) can be further reduced by using multiple decoupling capacitors (Figure 21).

Use disc ceramic capacitors for best performance. The VDD and reference pins (whether using an external or internal reference) should be separated from the analog ground plane (AGND) separately. This should be accomplished by placing the capacitors as close as possible to the pins of the AD7863, keeping the capacitor leads as short as possible to minimize lead inductance.