illustrate
The WM9707 is a high-quality stereo audio codec that is compliant with the AC'97 version 2.1 specification. The full-duplex 18-bit codec features and supports variable sampling rates from 8 to 48k samples/sec, providing excellent quality with a high signal-to-noise ratio. Other features include 3D sound enhancement, line level output, hardware sample rate conversion, master/slave mode operation and SPDIF output.
The WM9707 is interchangeable with the AC'97 codec from Wolfson and other suppliers. The WM9707 is fully operable on 3.3V or 5V or mixed 3.3/5V power supplies and is packaged in an industry standard 48-pin TQFP package in a 7mm body size.
AC'97 Features
8226 ; 3.3V or 5V operation • 18-bit stereo codec • Signal-to-noise ratio >95dB
• Multi-stereo input mixer • Mono and stereo volume controls • 48-pin TQFP package • Power management capabilities • Very low standby power • Supports Variable Rate Audio (VRA)
• Analog 3D Stereo Enhancement • Line Level Output • Support for Version 2.1 Specified Modem Sample Rate and Filtering • Master/Slave ID Selection

Introduction to Device Description
The WM9707 is fully compliant with version 2.1 of the AC'97 specification.
The WM9707 contains a stereo 18-bit codec (ie 2 ADCs and 2 DACs), integrated analog mixer with 4 sets of stereo inputs, telephone, 2 microphones and PC buzzer input. Additionally, an on-chip reference generation circuit generates the necessary bias voltages for the device, and a bidirectional serial interface allows the AC'97 controller. The WM9707 supports 18-bit resolution in the DAC and ADC functions, but the AC'97 serial interface specification allows writing or reading any word up to 20 bits long with the AC'97 codec. The words are msb justified, any unused lsb will default to 0. Typically, 16-bit words are expected to be used in most pc-type systems. So, for the DAC, the 16-bit word will be downloaded from the controller into the codec, padded with 0s to make the 16-bit word 20 bits long. In this case the wm9707 will handle a 16-bit word with 0 padding bits in the 2 LSB positions (making it 18 bits). At the ADC output, the WM9707 will provide a word of 18 bits, again with 0s in both lsb positions (bit 20). The AC'97 controller will ignore the 4 LSBs of a 20-bit word. When the wm9707 is interrogated at register 00h, it responds that it is an 18-bit device.
wm9707 has adc and dac functions implemented using oversampling or sigma delta.
converter, and use an on-chip digital filter to convert these 1-bit signals to the bit pcm words required by the 48ks/s 16/18-AC'97 controller. The digital portion of the device is powered separately from the analog power supply to optimize performance, and 3.3V digital and 5V analog power supplies can be used for the same device to further optimize performance. When the analog supply is 5V, so the WM9707 can be connected to a controller running on 5V to supply it, but the digital part of the WM9707 uses 3.3V. The WM9707 can also use only 3.3V supplies (digital and analog).
The WM9707 is not limited to PC applications. The ability to selectively power down various parts of the device, as well as the option to select an alternate master clock, and the resulting sample rate, means that many alternative applications in areas such as telecommunications may be expected. Additional features added by the Intel AC'97 specification, such as the EAPD (External Amplifier Power Down) bit, the internal connection of the PC beep to the output in the event of a device reset, support, and optional features such as variable sample rate Support and SPDIF output.
3D Stereo Enhancement This device contains stereo enhancement circuitry designed to optimize the listening experience when the device is used in a typical PC operating environment. That said, there's a pair of speakers placed on either side of the display, with little space between them. This circuit produces a differential signal by differencing the left and right channel playback data, then filtering this differential signal using a low pass filter and a high pass filter with a time constant set using an external capacitor connected to the cx3d pins 33 and 34. Typically, values of 100nF and 47nF set the high-pass and low-pass poles to approximately 100Hz and 1KHz, respectively. This frequency band corresponds to the range in which the ear is most sensitive to directional effects.
The filtered differential signal is gain adjusted by the amount set using the 4-bit value written to Register 22h, bits 3 to 0. A value of 0h is disabled, and a value of Fh is the maximum effect. Usually a value of 8h is optimal. User interfaces typically use a sliding control that allows the user to adjust the level of enhancement to suit the program material. Bits d13 3d in register 20h are the overall 3D enable bits. Capability register 00h reads the value 11000 from bit d14 back to d10. This corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement.
Note that the external capacitors that set the filter poles applied to the differential signal can be adjusted in value or even replaced with direct connections between pins. If this is adjusted then, the amount of differential signal fed back to the main signal path can be significant and can result in large signals that limit, distort or overdraw. There is no provision for pseudo-stereoscopic effects. Mono signals will have no boost applied (if the signals are in phase and the same amplitude). Stereo enhancement can be applied to the signal from the pcm dac channel. Can also be bypassed if desired. This control is enabled by setting the pop bit in register 20h.
Variable Sample Rate Support The DACs and ADCs on this device support all recommended sample rates specified in the Intel Revision 2.1 Audio Rate Specification. The default rate is 48ks/s. If an alternate rate is selected and variable rate audio is enabled (register 2ah, bit 0), the AC'97 interface continues to run at 48K words per second, but data is transmitted across the link in bursts such that the net sample rate is selected . It is an AC'97 version 2.1 compliant controller to ensure that data is supplied to, and received from, the ac link at the proper rate.
The device supports on-demand sampling. That is, when the DAC signal processing circuit needs another instance, it sends an instance request to the controller, and the controller must send it on the next frame it sends. For example, if you choose a rate of 24ks/s, the device will request the controller to provide one sample for each stereo DAC every other frame. Note that if an unsupported rate is written to one of the rate registers, the rate will default to the closest supported rate. When queried at a rate supported by the device, the register will respond by default.
The sampling rate of the left and right channels of the ADC and DAC is always the same.

SPDIF digital audio data output pin 48 can be used to output pcm dac playback data in spdif (iec958) digital data format. To enable this output, bit spdf in register 5ch should be set or pin 44 should be pulled high.
In addition, bit scm in register 5ch can also be set, which will delete the iec958 data, allowing a serial copy protection mechanism to be implemented. Note that this data output will only run at synchronous rate, so only 48ks/s operations are supported. The Powertrain Control Module DAQ continues to function normally when the SPDIF output is enabled.
Gain Control Register Location PGA Control Register Mute Default Value DAC 18H Mute (Bit-15) Mixer 72h Unmuted (Bit-15) Volume 02h Mute (15) Gain Control Register Location Master/Slave ID Support WM9707 Support as Master or Slave Codec operation. The device is configured to select master or slave by tying CID pin 45 to the package.
Basically, the device identified as master (id=0) has bitclk as output, while slave (any other id) must provide bitclk as input. This obviously means that if the master on the AC link is disabled, the slave will not work.
The AC'97 version 2.1 specification defines the CID pin to have reverse sensing and to provide internal powerless pull-ups. So if not connected to the CID pin, the pin pulls high select id=0, which is master. External ground will select other IDs.

The Control Interface provides a digital interface for controlling the WM9707 and transferring data between them. This serial interface is compatible with Intel AC'97.
The main control interface functions are:
• Control analog gain and signal path via mixer • Bidirectional transfer of ADC and DAC words between AC'97 controllers • Select power-down mode.
The AC-Link Digital Serial Interface Protocol WM9707 integrates a 5-pin digital serial interface to connect it to the AC'97 controller. The AC link is a bidirectional, fixed rate, serial pcm digital stream. It handles multiple input and output audio streams and control register accesses using a time division multiplexing (tdm) scheme.
The AC link architecture divides each audio frame into 12 output and 12 input data streams, each with 20-bit sampling resolution. The minimum required DAC and ADC resolution is 16-bit, AC'97 can also be implemented with 18- or 20-bit DAC/ADC resolution, provided the AC link architecture provides it. WM9707 supports 18-bit operation.

Synchronization of all AC link data transactions is signaled by the WM9707 controller. The WM9707 drives the serial bit clock onto the AC link, and the AC'97 controller then uses the synchronization signal to construct the audio frame.
Synchronization, fixed at 48kHz, is obtained by dividing by the serial clock (bit clock). The bit clock, fixed at 12.288MHz, provides the necessary clock granularity to support 12-bit, 20-bit outgoing and incoming time slots. AC link serial data is transferred on every rising edge of the bit clock. AC link receiver data (WM9707 for output data, AC'97 controller for input data), sampling the falling edge of the bit for each serial bit.
The AC link protocol provides a special 16-bit time slot (slot 0), where each bit conveys a valid flag for the corresponding time slot in the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been allocated to the data stream and contains valid data. If the slot is marked as invalid, the data (wm9707 for the input stream, ac'97 controller for the output stream), fills all bits in the positions represented by 0 during the active time of the slot.
At the beginning of each audio frame, synchronization is maintained for the total duration of the 16-bit clock. The part of the audio frame with high synchronization is defined as the marking phase. The remaining sync-low audio frames are defined as the data phase. Additionally, to conserve power, clock, sync, and data signals can be suspended. This requires the wm9707 to be statically designed, allowing its register contents to remain intact when entering power-saving modes.

AC-Link audio output frame The audio output frame data stream corresponds to a multiplexed beam of all digital output data aimed at the DAC input and control registers of the WM9707. As mentioned earlier, each audio output frame supports up to 12-bit output data time slots. Slot 0 is a special reserved time slot containing 16 bits for the AC link protocol infrastructure.
Output take closure (16 bits)
bit (15) frame valid bit (14) slot 1 valid command address bit (main codec only)
bit (13) slot 2 valid command data bit (main codec only)
Bits (12:3) Slots 3-12 AC'97 Defined Significant Bits Bit 2 Reserved (set to 0)
bits (1:0) 2-bit message ID field (00 reserved for primary; 01 for secondary) in slot 0, the first bit is the global bit (sdata out slot 0, bit 15), which marks the entire audio frame. If the valid frame bit is 1, it indicates that the current audio frame contains at least one slot of valid data. The 12-bit positions next sampled by wm9707 indicate that the corresponding 12 time slots contain valid data.
In this way, data streams of different sample rates can be streamed at their fixed 48kHz audio frame rate. Figure 11 illustrates a slot-based AC link protocol. Bits 14 and 13 are not used to verify data in slots 1 and 2 when the codec is a slave.
Conversely, if the message ID bits (1:0) match the codec ID, the address is valid, and bit 19 from slot 1 then indicates whether slot 2 is valid.

A new audio output frame begins with a sync low-to-high transition, which is synchronized with the rising edge of the bit clock. On the following falling edge of Bit_clk, the wm9707 samples the sync assertion. This falling edge marks the beginning of AC Link's knowledge of a new audio frame. On the next rising edge of Bit_clk, AC'97 transitions sdata_out to the first position of slot 0 (valid frame bit). Each new bit position is presented to the AC link on the rising edge of the bit clock and is subsequently followed by the WM9707 on the falling edge of the bit. This sequence ensures that the data transitions and the sampling points of the subsequent incoming and outgoing data streams are time-aligned.
The audio functions specified by the baseline AC'97 must always convert the sample rate to a fixed speed of 48ks/s on the AC'97 controller. This requirement is necessary to ensure that the AC'97 controller and WM9707, among other things, can guarantee the AC'97 functionality specified by the baseline by the following definitions.
The composite stream of sdata_out is msb justified (msb first), with all invalid slot positions filled with 0s by the AC'97 controller.
The AC'97 controller always fills all subsequent invalid bit positions of a 20-bit slot with 0s if there are fewer than 20 valid bits within the allocated valid time slot.

As an example, consider an 8-bit stream of samples that is being played to a wm9707 dax! The first 8 bit positions are shown to the dac (msb justified), then the next 12 bit positions, filled with 0s by the AC'97 controller. This ensures that no matter the resolution of the DAC implemented (16, 18 or 20 bits), at least no DC offset significant bits are introduced.
When a mono audio sample stream is output from an AC'97 controller, the left and right sample stream time slots must be filled with the same data.
Command Address Port The command port is used to control functions and monitor the status of wm9707 functions including but not limited to mixer settings and power management (see Serial Interface Registration Map). The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries. Only even-numbered registers (00h, 02h, etc.) are valid. Weird. Register read/write has no effect on wm9707. The information provided to the WM9707 by the audio output frame slot 1 communication control register address and read/write commands.
Read/write command by assigned command address bits (19) (1=read, 0=write)
Bits (18:12) Control Register Index (64-16 bit positions, even addressing change boundary) Bits (11:0) Reserved (padded with 0) The first bit (msb) of the wm9707 sample indicates whether the current control transaction is a read or write operation. The following 7-bit locations communicate with the destination control register address. The tail 12-bit position in the socket is reserved and must be controlled by the AC'97 controller.
Command Data Port The command data port is used to operate on the current command port is a write cycle. (as shown in slot 1 bit 19). Bits (19:4) control register write data (if the current operation is a read) Bits (3:0) are reserved (filled with 0s) If the current command port operation is a read operation, the entire time period must be filled with 0s AC'97 Control device.
End 3: pcm playback life channel audio output frame slot 3 is the composite digital audio left playback stream. Compatible with PCs in typical games this slot consists of a digital mixer (on an AC'97 controller or host processor), with a sample output for musical synthesis. If the resolution of the transmission is less than 20 bits, the AC'97 controller must fill all trailing invalid bits with zeros within this time period.
End 4: pcm playback right channel audio output frame slot 4 is the composite digital audio right playback stream. Compatible with PCs in typical games this slot consists of a digital mixer (on an AC'97 controller or host processor), with a sample output for musical synthesis.
If a stream of samples with a resolution less than 20 bits is transmitted, the AC'97 controller must fill all trailing invalid bit positions in this time slot with zeros.
Line codec's selectable mode audio output frame slot 5 contains msb adjusted modem dac input data. Optional AC'97
WM9707 does not support this function and will ignore this function if data is written to this location. This May is determined by the AC'97 controller querying the WM9707 Vendor ID register.

Conclusion 6 to 9: Surround and Data Audio Out Frame slots 6 to 9 are used to send surround sound data. Findings 10 and 11: Line2 and Handheld DACs do not support these data slots.
These data slots are not supported for GPIO control. AC-Link Audio Input Box (Data Input)
AC Connection Audio Input Box Audio Input Frame Data Stream Corresponding to multiplexed beams of all digital input data aimed at the AC'97 controller. Like audio output frames, each AC link audio input frame consists of 12-bit time slots.
Slot 0 is a special reserved slot containing 16 bits for the AC link protocol infrastructure. In slot 0, the first bit is the global bit (sdata in slot 0, bit 15) which marks whether the wm9707 is in a codec ready state. If the codec ready bit is 0, it means the wm9707 is not ready for normal operation. This condition is normal after a power-off reset, for example, when the voltage reference of the wm9707 is stable. When the AC link codec ready indicator bit is 1, it indicates that the AC link and WM9707 control and status registers are full of combat status. The AC'97 controller must further probe the power-down control/status register to determine which subsections (if any) are ready.
Before attempting to bring the WM9707 into operation, the AC'97 controller should first poll the bit in the audio input frame (SData in slot 0, bit 15) that indicates that the WM9707 has lost codec readiness.
Once the WM9707 is ready by the sampling codec, the next 12-bit positions are indicated by the AC'97 sampling controller which of the corresponding 12 time slots to assign to the incoming data stream and that they contain valid data.
There are several subsections in wm9707 that can go into busy/ready state independently. It is the responsibility of the WM9707 controller to probe deeper into the WM9707 register file to determine which wm9707 subsections are actually ready.

Synchronized with the rising edge of BIT-U CLK. On the following falling edge of BIT-U CLK, AC'97 samples the synchronization assertion. This falling edge marks the beginning of a new audio frame on both sides of the AC link. The next time bit clk goes up, ac'97 converts SData into the first bit position of slot 0 (codec ready bit). Each new bit position is presented to the AC link on the rising edge of BIT-U CLK and subsequently by the AC'97 controller following the falling edge of the bit CLK. This sequence ensures that the data transitions and the sampling points of the subsequent incoming and outgoing data streams are time-aligned. The composite stream of sdata is filled with 0s by wm9707 using all invalid bit positions (for allocated and/or unallocated slots). Should be sampled on the falling edge of BIT-U CLK. Conclusion 1: Status Address Port The status port is used to monitor the status of WM9707 functions, including but not limited to mixer settings and power management.
Audio input frame slot 1 echo control register index for historical reference to return data in slot 2. (Assuming slots 1 and 2 were marked as valid 0 by wm9707 during the slot).

End 4: pcm record right channel audio input frame slot 4 is the input MUX of WM9707 and the right channel output of ADC.
The ADC of the WM9707 can be implemented to support 16, 18 or 20 bit resolution.
The wm9707 outputs its ADC output data (msb) first and fills in any subsequent invalid bit positions.
Fill its 20-bit slot with 0s.
Optional mode for line codecs
WM9707 does not support.
The optional dedicated microphone to record data is not supported by the WM9707.
Audio input frame slots 7 to 12 are reserved for future use and are always used by the WM9707.
AC-Link Low Power Mode The AC link signal can be put into low power mode. When the WM9707's power down register 26h, is programmed to the appropriate value, both bits clk and sdata in will be brought in, and good luck with the logic low voltage levels. Bits clk and sdata in are in register 26H for power down with PR4. To program the AC link to a low power mode when the AC'97 controller driver is in the ready state, it is assumed that slots 1 and 2 are the only valid streams in the audio output frame. At this point, it is assumed that all audio input sources have been neutralized.
After programming the WM9707, the AC'97 controller should also drive the sync and SData outputs low to this low power, suspend mode.
Once the wm9707 is instructed to keep the bit-u clk, a special wake-up protocol must be used to put the AC link into active mode, since normal audio output and incoming frames cannot communicate without the bit-u clk. There are two ways to wake up the AC-Link to get the AC-Link out of a low power, suspend mode. Regardless of the method, it is the AC'97 controller that performs the wake-up task.
The AC link protocol provides a cold WM9707 reset and a warm WM9707 reset. The current power down state will ultimately determine which form of wm9707 reset is appropriate. Unless a cold reset or a register reset (write to reset register 00h) is performed, in which the wm9707 registers are initialized to their default values, the registers are in all power-down modes.
After a power outage, the AC link must not be reactivated by re-asserting the sync signal at least 4 audio frame times after the frame that triggered the shutdown.
When the AC link is powered up, it indicates ready via the codec ready bit (input slot 0, bit 15).
Cold WM9707 Reset A cold reset is achieved by asserting resetb within the specified minimum time (1ms). By driving resetb low, bit clk and sdata out will be activated, or reactivated as appropriate, and all WM9707 control registers will be initialized to their default power-on reset values.

Warm WM9707 Reset A warm WM9707 reset will reactivate AC link values without changing the current WM9707 registers. In the absence of a sync signal, a warm reset is signaled by driving sync high for at least 1 ms.
bit CLK.
Sync in normal audio frames is a sync input. Without the bit clk, sync is handled as an asynchronous input to generate a warm reset of the WM9707. This WM9707 will not respond to BIT-U CLK activation until through the WM9707. This will preclude false detection of new audio frames. Serial Interface Register Map Description The serial interface bits perform the control functions described below: The register map is fully specified by the AC'97 specification, and this description is simply repeated below, optionally omitting unsupported functions.
Other registers (index 00H) Writing any value to this register will perform a register reset, which will cause all registers to revert to their default values. Reading this register returns the part's ID code that the modem supports (not supported by the WM9707) and a type of 3D stereo enhancement code.
id decodes the wm9707's capabilities based on:
Bit value function on
ID0 dedicated microphone PCM in channel 0 of model WM9707
ID1 modem line codec support 0
ID2 Bass and Treble Control 0
ID3 Analog Stereo (Mono to Stereo) 0
ID4 headphone output support 1
ID5 loudness (bass boost) support 0
ID6 18-bit DAC resolution 1
ID7 20-bit DAC resolution 0
ID8 18-bit ADC resolution 1
ID9 20-bit ADC resolution 0
SE4…SE0 Wolfson Microelectronics 3D Enhanced 11000
Reset Register Function Note that wm9707 indicates 18-bit compatibility by default.
Play Master Volume Registers (Indexes 02h, 04h and 06h) These registers manage the output semaphore. Register 02H controls the stereo master volume (left and right channels), register 04H controls the optional stereo headphone output, and register 06H controls the mono volume output. Each step corresponds to 1.5 dB. The msb of the register is the mute bit. When this bit is set to 1, the level of this channel is set to -db.
ml5 to ml0 represent the left channel level, mr5 to mr0 represent the right channel, and mm5 to mm0 represent the mono output.
wm9707 does not provide support for volume level msb. If the msb is written then the wm9707 detects when the bit is set and sets all 4 lsbs to 1s.
A 1xxx wm9707 interpreter, i.e. x11111. When read with x11111, it also responds, not the value greater than 1xxxxxx, written. Drivers can use this feature to detect whether bit 6 is supported or not.
The default value for both the mono and stereo registers is 8000h (1000 0000 0000), which corresponds to 0dB gain when mute is on.

Verification Control/Status Register (Index 26H) This read/write register is used to program power down states and monitor subsystem readiness. The lower half of this register is read-only, 1 means the subsection is ready. Ready is defined as a subsection capable of executing in its nominal state. The value on the AC link when this register is written has no effect on read-only bits 0 through 7.
When the AC Link Codec Ready Indication bit (SData in slot 0, bit 15) is 1, it indicates that the ACLink and WM9707 control and status registers are fully operational. The AC'97 controller must further probe the power-down control/status register to determine the exact subsection of the analog mixer, etc. The power-down status register functions as follows: The first three bits will be used individually, not in combination with each other . The last bit, pr3, can be used in combination with pr2 or alone. PR0 and PR1 control only pcm adc and dac. WM9707 does not support PR6.
Write as a function
pr0 pcm and adc and input mux power down PR1 PCM OUT DACS power down PR2 analog mixer power down PR3 analog mixer power down (VREF off) normal link code WM9707 power down/power up flow example demonstrates a complete WM9707 power down example process. Writes to the power-down registers from the normal operating sequence shut down the WM9707 one block at a time. After shutting down all devices (setting PR0 to PR3), the last write (setting PR4) performs a shutdown of the WM9707 digital interface (AC link).

WM9707 Power-Down/Power-Up Procedure Example An example procedure to complete the WM9707 power down. Writes to the power-down registers from the normal operating sequence shut down the WM9707 one block at a time. After shutting down all devices (setting PR0 to PR3), the last write (setting PR4) performs a shutdown of the WM9707 digital interface (AC link).

The party will remain in sleep mode with all its registers maintaining their static values. Wake up the WM9707 and the AC'97 controller will send a pulse on the sync line to issue a warm reset. This will restart the WM9707 digital interface (reset PR4 to 0). The WM9707 can also be woken up from a cold reset. A cold reset will cause register values to be lost because a cold reset will set them to their default state. When a segment is powered back on, the power down control/status register (index 26h) is attempting any operation that requires it.
WM9707 power down/analog stream still active The state that all mixers should use static volume settings is contained in the relevant registers. When the user can play CDs (or externally) connect to speakers through the WM9707, but most of the system is in low power mode. This process follows the previous steps, except that the analog mixer is never turned off.
Verify control/status register (index 26H) Note that in order to enter extreme low power mode, pr4 and pr5 need to be set to turn off the oscillator circuit. Synchronization ensures that the PR4 and PR5 bits are reset and the oscillator is restarted. Under the same conditions, the AC link is restarted. Note that PR4 is redundant in slave mode.
Audit 2.1 registers (index 28h to 58h) These registers are specified for use in version 2.1 of the AC'97 specification and have
The following features on the WM9707:
Register 28h extended audio id
The Extended Audio ID register is a read-only register that identifies which extended audio features are supported (except by reading index 00h). A non-zero value indicates that the feature is supported.
Function Date Arbitrary Mode Variable Rate Audio Support 1
DRA Dual Rate Audio Support 0
VRM variable rate small ADC supports 0
CDAC Center DAC Support 0
SDAC Surround DAC support 0
LDAC LFE DAC support 0
AMAP slot to front-end DAC mapping support 0 ID1 codec configuration fixed in 9707 0 ID0 codec configuration pin 45 value 1 (opposite level at pin 45) extended audio ID register register 2a extended audio state and Control Register The extended audio status and control register is a read/write register that provides status and control of extended audio functions.

Registers 2ch to 32h Audio Sampling Council Register Control These registers are read/write registers for writing and are used to select the audio pcm converter. Default is 48ks/s rate. Note that only the recommended rates for version 2.1 are supported by the WM9707, selecting any other unsupported rate will cause the rate to default to the closest supported rate, and the supported rate value to be locked and read back.
Note that SPDIF mode only supports 48ks/s rate.
Registers 36H and 38H - 6 Channel Volume Control These read/write registers control the output volume of the optional four pcm channels. (Not supported by WM978) Sales reserved registers (index 5AH-7AH) These registers are vendor specific. Unless the Vendor ID register is checked first to make sure the driver knows the source of the AC'97 part.
SPDIF digital audio data output (index 5ch) WM9707 provides SPDIF output. To enable this output, bit spdf in register 5ch should be set. In addition, bit scm in register 5ch can also be set, which sets a flag in the copyright IEC958 data, allowing removal of the serial copy protection mechanism.
The WM9707 can be programmed to automate the DAC. By setting the mute bit, the WM9707 will mute the DAC when a continuous sequence of 1024 zeros is detected.

Specific Gain Control Register (Index 72h) This register controls the gain and mute functions applied to the mixer path. This PGA is not included in the Intel specification, but in order to allow the recording of the mixer output and playback of the dac signal at the same time. The function is the same as another mixer however, the default value of the register is not muted. If you don't use it, it will be transparent to the user.
Sales ID Register (index 7ch to 7eh) This register is used for specific vendor identification if required. The id method is Microsoft's plug and play vendor ID code. The first character of the id is f7 to f0, the second character is s7 to s0, and the third t7 to t0. These three characters are ascii encoded. The rev7 to rev0 fields are for the salesperson revision number. In wm9707 the vendor id is set to wml3.
Wolfson is a registered Microsoft Plug and Play vendor.
Sales ID Register (Index 74H) This register describes how data is mapped to the AC'97 DAC. Register 74h can be used to change the incoming DAC data slot used by the onboard DAC. This allows software to control multiple codecs.

Recommended External Components

Suggested SPDIF output circuit for external component values 3.3V operation is recommended in the case of avdd=3.3v, the performance of the device is expressed in the electrical characteristics.
In 3.3V analog operation, the mid-rail reference voltage is 1.5V. All ADC and DAC reference voltages are 3/5 their nominal 5V value. 1Vrms input and output signals in 5V applications, scaled to 660MVrms and 3.3V applications. If a 1VRMS output is required, the mixer gain adjustment PGA needs to be increased by a factor of 3 in 1.5db steps.