General Instructions
The W25P80 (8M-bit) and W25P16 (16M-bit) serial flash memory provides a storage solution for systems with limited space, pins, and power. They are ideal for code-downloading applications and for storing voice, text, and data. These devices operate on a 2.7V to 3.6V supply, with current consumption as low as 4mA active and 1 microA off. The device is housed in a space-saving SOIC package. As part of the series of flash products, winbond also offers compatible devices with 1m/2m/4m bit density.
The w25p80 /16 array is organized into 4096/8192 programmable pages of 256 bytes each. Use the PAGE PROGRAM instruction to program up to 256 bytes at a time. Pages are divided into 16/32 erasable sectors of 256 pages (64K bytes) each, as shown in Figure 2. Both sector erase and chip (full chip) erase commands are supported. In addition, a 256-byte parameter page is provided for user data normally stored in eeprom, such as id or revision numbers and configuration parameters. The parameter page is separated from the main array, allowing faster erase times.
The Serial Peripheral Interface (SPI) consists of four pins (Serial Clock, Chip Select, Serial Data In and Serial Data Out) and supports high-speed serial data transfer up to 50MHz. A hold pin, a write-protect pin and a programmable write-protect function provide further control flexibility. In addition, you can query the manufacturer and device type of the device. 8M-bit and 16M-bit serial flash

package type
The W25P80/16 is mainly available in SOIC package. W25P80 and W25p16 use 8-pin plastic 208mil wide SOIC (Winbond package code SS) (NexFlash package code S), W25p16 also uses 16-pin plastic 300mil wide SOIC (Winbond package code SF) (NexFlash package code F), as shown in Figure 1A and 1B. Packaging drawings and dimensions are at the end of this data sheet. An optional 8-contact MLP package is available. Please contact Winbond for more MLP package information.
Chip Select (/cs)
The spi chip select (/cs) pin enables and disables device operation. When /cs is high, the device is deselected and the serial data output (do) pin is at high impedance. When deselected, device power consumption is in standby unless an internal erase, program, or status register cycle is in progress. When /cs is lowered, the device will be selected, power consumption will increase to the active level, and commands can be written to and data read from the device. After power up, /cs must transition from high to low in order to accept new commands. The /cs input must track the VCC supply level at power up. This can be done using a pull-up resistor on /cs if desired.
Serial data output (do)
The SPI Serial Data Out (DO) pin provides a way to serially read (shift out) data and status from the device. Data is shifted out on the falling edge of the serial clock (CLK) input pin.
Write Protect (/wp)
The write protect (/wp) pin can be used to prevent writing to the status register. Used in conjunction with the Block Protection (bp2, bp1, and bp0) bits of the Status Register and the Status Register Protection (srp) bit, part or the entire memory array can be hardware-protected. The /WP pin is active low.
keep (/hold)
The /hold pin allows to hold the device while it is active. When /hold goes low, when /cs goes low, the do pin will be in high impedance and the signals on the di and clk pins will be ignored (don't care). When /HOLD is high, device operation can resume. The /hold function is useful when multiple devices share the same spi signal. ("See Hold function")
Serial Clock (CLK)
The SPI serial clock input (CLK) pin provides the timing of serial input and output operations. ("See SPI" operation)
Serial Data Input (DI)
The SPI serial data input (DI) pins provide a method for serially writing (shifting) commands, addresses, and data into the device. Data is latched on the rising edge of the serial clock (CLK) input pin.
block diagram

The W25P80/16 is accessed via an SPI-compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data In (DI), and Serial Data Out (DO). SPI bus operating modes 0 (0,0) and 3 (1,1) are supported. The main difference between Mode 0 and Mode 3 is the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the serial flash. For Mode 0, the CLK signal is usually low. For Mode 3, the CLK signal is normally high. In both cases, the data input on the DI pin is sampled on the rising edge of CLK. The data output on the do pin is clocked on the falling edge of clk.
hold function
The /HOLD signal allows W25P80/16 operation to be suspended when activated (when /CS is low). The /hold function may be useful in situations where spi data and clock signals are shared with other devices. For example, when priority interrupts need to use the SPI bus, consider whether the page buffer is only partially written. In this case, the /hold function can save the state of the instruction and data in a buffer so that programming can resume where it left off once the bus is available again.
To initiate the A/HOLD condition, a device with /CS low must be selected. If the CLK signal is already low, the A/HOLD state will activate on the falling edge of the /HOLD signal. If CLK is not already low, the /hold condition will activate after the next falling edge of CLK. If the CLK signal is already low, the /HOLD condition will terminate on the rising edge of the /HOLD signal. If CLK is not low, the /hold condition will terminate after the next falling edge of CLK.
In the A/HOLD state, the serial data output (do) is high impedance and the serial data input (di) and serial clock (clk) are ignored. The chip select (/cs) signal should remain active (low) for the entire duration of the /hold operation to avoid resetting the device's internal logic state.
Write-protecting applications using non-volatile memory must consider the possibility of noise and other adverse system conditions that could compromise data integrity. To solve this problem, w25p80/16 provides several ways to protect data from accidental writing.
Write Protection Function • When VCC falls below the threshold, the device resets.
• Time delay write disabled after power up.
• Write enable/disable instructions.
• Automatic write disable after program and erase.
• Use software write protection of the status register.
• Hardware write protection using status register and /wp pin.
• Write protection using power down command.
On power-up or power-down, the W25P80/16 will remain in reset when VCC is below the threshold of VWI (see power-up timing and voltage levels and Figure 17). When reset, all operations are disabled and no commands are recognized. All program and erase related instructions are further disabled due to the time delay of TPUW during power up and after VCC voltage exceeds VWI. This includes Write Enable, Page Program, Sector Erase, Chip Erase and Write Status Register instructions. Note that the chip select pin (/cs) must track the VCC supply level at power-up until the VCC minimum level and TVSL delay are reached. This can be done using a pull-up resistor on /cs if desired.
After power-up, the device will automatically be placed into the write-disable state of the status register with the write-enable latch (WEL) set to 0. Before accepting a Page Program, Sector Erase, Chip Erase, or Write Status Register command, the Write Allow command must be issued. The Write Enable Latch (WEL) is automatically cleared to a write disable state of 0 upon completion of a program, erase or write instruction.
Software-controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protection (srp) and Block Protection (bp2, bp1, and bp0) bits. These status register bits allow some or all of the memory to be configured as read-only. Used in conjunction with the write-protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. See Status Register for more information.
In addition, the power-down command provides an additional level of write protection because all commands except the release power-down command are ignored.
Control and Status Registers The Read Status Register instruction can be used to provide the status of the Flash array availability (if the device has writes enabled or disabled) and write protection status. The Write Status Register instruction can be used to configure the device write protection feature.
status register busy
busy is a read-only bit in the status register (s0) that is set to a 1 state when the device executes a page program, sector erase, chip erase, or write status register instruction. During this time, the device will ignore commands other than the read status register command (see tw, tpp, tse, and tce in AC Characteristics). When a program, erase or write status register instruction completes, the busy bit will be cleared to the 0 state, indicating that the device is ready to accept further instructions.
Write Enable Latch (WEL)
The Write Enable Latch (WEL) is a read-only bit in the Status Register (S1) that is set to 1 after a Write Enable instruction is executed. When the device write is disabled, the WEL status bit is cleared to 0. The write disable state occurs at power-up or after any of the following commands: write disable, page program, sector erase, chip erase, and write status register.
The block protection bits (bp2, bp1, bp0) are non-volatile read/write bits in the status registers (s4, s3, s2) that provide write protection control and status. The block protection bits can be set using the Write Status Register instruction (see tw in AC Characteristics). All, none or part of the memory array can be protected from program and erase instructions (see Status Register Memory Protection Table). The factory default setting of the block protection bit is 0, there is no protected array. If the Status Register Protection (SRP) bit is set to 1 and the Write Protect (/WP) pin is low, the Block Protection bit cannot be written.
Reserved Bits Status register bits 5 and 6 are reserved for future use. The current device will read 0 in these bit positions. It is recommended to mask reserved bits when testing the status register. Doing so will ensure compatibility with future devices.
The Status Register Protect (SRP) bit is a nonvolatile read/write bit in the Status Register (s7) that can be used with the Write Protect (/wp) pin to disable writes to the Status Register. When the srp bit is set to the 0 state (factory default), the /wp pin has no control over the status register. When the srp pin is set to 1, the write status register instruction is locked when the /wp pin is low. When the /wp pin is high, write status register instructions are allowed.

illustrate
The instruction set of the W25P80/16 consists of 13 basic instructions, which are fully controlled via the SPI bus (see instruction set table). Use the falling edge of chip select (/cs) to start the instruction. The first byte of data coming into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of the clock, most significant bit (msb) first.
Instructions vary in length from one byte to several bytes, possibly followed by address bytes, data bytes, dummy bytes (don't care), and in some cases a combination. The description is done using the rising edge of EDGE/CS. Clock-dependent timing diagram for each instruction. All read instructions can be completed after any timing bit. However, all write, program, or erase instructions must complete on a byte boundary (/cs driven high after a full 8-bit clock) or the instruction will terminate. This feature further protects the device from accidental writes. In addition, when memory is being programmed or erased, or when the status register is written, all instructions except read status register are ignored until the program or erase cycle is complete.

Write Enable (06h)
The write enable instruction sets the write enable latch (WEL) bit in the status register to 1. The WEL bit must be set before every Page Program, Sector Erase, Chip Erase and Write Status Register instructions. Move the instruction code "06h" into the data input (di) pin on the rising edge of clk by driving /cs low, then drive /cs high to enter the write enable instruction.
Write Disable (04h)
The Write Disable instruction resets the Write Enable Latch (WEL) bit in the Status Register to 0. The write disable command is entered by driving /cs low, moving the command code "04h" to the di pin, then driving /cs high. Note that the WEL bit is automatically reset after power-up and after the Write Status Register, Page Program, Sector Erase and Chip Erase commands are completed.
Read Status Register (05h)
The Read Status Register instruction allows the 8-bit status register to be read. Commands are entered by driving /CS LOW and shifting the command code "05H" into the DI pin on the rising edge of CLK. Then, the status register bits are shifted out on the do pin on the falling edge of CLK, the most significant bit (msb) first as shown in Figure 6. The status register bits are shown in Figure 3 and include the busy, wel, bp2-bp0, and srp bits (see the description of the status register earlier in this data sheet).
Status register instructions can be used at any time, even if a program, erase or write status register cycle is in progress. This allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The status register can be read continuously. This command is done by driving /cs high.
Write Status Register (01h)
The Write Status Register instruction allows writing to the Status Register. A write enable command must be executed before the device can accept a write status register command (status register bit WEL must be equal to 1). Once the write operation is enabled, enter the command by driving /cs low, send the command code "01h", then write the status register data byte. Only the non-volatile status register bits srp, bp2, bp1 and bp0 (bits 7, 4, 3 and 2). All other status register bit positions are read-only and will not be affected by the write status register instruction.
The /cs pin must be driven high after the eighth bit of the last byte is latched. If this is not done, the write status register instruction will not be executed. After /cs is driven high, an auto-timed write status register cycle will begin for a duration of tw (see AC Characteristics). While a write status register cycle is in progress, the read status register instruction can still be accessed to check the status of the busy bit. During the write status register cycle, the busy bit is 1; at the end of the cycle and ready to accept other instructions again, the busy bit is 0. After the write register cycle is complete, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the block protection bits (bp2, bp1 and bp0) to be set to protect all, some or none of the memory from erase and program instructions. The protected area becomes read-only (see Status Register Memory Protection Table). The Write Status Register instruction also allows the Status Register Protection bit (srp) to be set. This bit is used in conjunction with the write protect (/wp) pin to disable writes to the status register. When the srp bit is set to the 0 state (factory default), the /wp pin has no control over the status register. When the srp pin is set to 1, the write status register instruction is locked when the /wp pin is low. When the /wp pin is high, write status register instructions are allowed.
Write status register instruction sequence diagram to read data (03h)
The Read Data instruction allows more than one byte of data to be read sequentially from memory. The instruction is initiated by driving the /cs pin low, then shifting the instruction code "03h" followed by the 24-bit address (A23-A0) into the DI pin. Code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte at the address memory location will be shifted on the DO pin on the falling edge of CLK, MSB first. After each byte of data has been shifted out allowing a continuous stream of data, the address is automatically incremented to the next higher address. This means that the entire memory can be accessed with a single instruction as long as the clock continues. This command is done by driving /cs high. The read data command sequence is shown in Figure 8. If a read data command is issued during an erase, program or write cycle (busy=1), the command will be ignored and will not have any effect on the current cycle. The Read Data command allows clock rates from DC to reach the maximum FR (see AC Electrical Characteristics).
fast read (0bh)
The fast read command is similar to the read data command, except that it operates at the highest frequency of fr (see AC electrical characteristics). This is accomplished by adding a "dummy" byte after the 24-bit address, which allows extra time for the device's internal circuitry to set the initial address. The dummy byte data value on the DI pin is "don't care".
Page program (02h)
The Page Program instruction allows programming of up to 256 bytes of data in all previously erased 1S (FFH) memory locations. A write enable instruction must be executed before the device accepts a page program instruction (status register bit WEL must be equal to 1). The instruction is initiated by driving the /cs pin low, then shifting the instruction code "02h" followed by a 24-bit address (a23-a0) and at least two data bytes into the di pin. Because w25p80/16 programs are incremented by one word (two bytes) at a time, the 24-bit address (a23-a0) must be an even address (a0 must be equal to 0). When data is sent to the device, the /cs pin must be held low for the entire length of the command.
If an entire 256-byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the last address byte is non-zero and the number of clocks exceeds the remaining page length, then addressing will wrap to the beginning of the page. Less than 256 bytes can be programmed without any effect on other bytes in the same page. If more than 256 bytes are sent to the device, addressing wraps to the beginning of the page and overwrites previously sent data.
As with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte is locked. If this is not done, the page program instructions will not be executed. After /cs is driven high, self-timed page program instructions will start within a period of tpp (see ac characteristics). While a page program cycle is in progress, the Read Status Register instruction can still be accessed to check the status of the busy bit. During a page program cycle, the busy bit is 1 and becomes 0 when the cycle ends and the device is ready to accept other instructions again. After the page program cycle is complete, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. If the addressed page is protected by the block protection (bp2, bp1, bp0) bits (see Status Register Memory Protection Table), the page program instruction is not executed.
Page Program Instruction Sequence Diagram Sector Erase (D8H)
The Sector Erase instruction sets all memory within the specified sector to the erased state for all 1s (ffh). A Write Enable command must be executed (status register bit WEL must be equal to 1) before the device accepts the Erase Sector command. This instruction moves the instruction code "d8h" by driving the /cs pin low and after the 24-bit sector address (a23-a0)
The /cs pin must be driven high after the eighth bit of the last byte is latched. If this is not done, the sector erase command will not execute. After /cs is driven at high speed, the self-timed sector erase command will start within a period of tse (see AC characteristics). While a sector erase cycle is in progress, the Read Status Register instruction can still be accessed to check the status of the busy bit. During a sector erase cycle, the busy bit is 1 and becomes 0 when the cycle ends and the device is ready to accept other instructions again. After the sector erase cycle is complete, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. If the addressed page is protected by the block protection (bp2, bp1, bp0) bits (see Status Register Memory Protection Table), the sector erase instruction will not be executed.
Chip Erase (C7H)
The chip erase instruction sets all memory within the device to an erased state for all 1s (ffh). Before the device can accept a chip erase command, a write enable command must be executed (status register bit WEL must be equal to 1). This instruction is initiated by depressing the /cs pin and moving the instruction code "c7h".
After locking the eighth bit, the /cs pin must be driven high. If this is not done, the chip erase instruction will not execute. After /cs is driven high, the self-timed chip erase command will begin within a period of tce (see AC characteristics). While a chip erase cycle is in progress, the Read Status Register instruction can still be accessed to check the status of the busy bit. During a chip erase cycle, the busy bit is 1 and becomes 0 when done, and the device is ready to accept other instructions again. After the chip erase cycle is complete, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. If any page is protected by the block protection (bp2, bp1, bp0) bits (see Status Register Memory Protection Table), the chip erase instruction is not executed.
Power outage (B9H)
Although the standby current during normal operation is relatively low, the standby current can be further reduced as the power-down command is executed. The lower power consumption makes the power-down command particularly useful for battery-powered applications (see ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /cs pin low and moving the instruction code "b9h".
After locking the eighth bit, the /cs pin must be driven high. If this is not done, the power down command will not be executed. After /cs is driven high, the power-down state is entered for the duration of tdp (see AC Characteristics). When in the off state, only the release from the shutdown/device ID command, which restores the device to normal operation, will be recognized. All other directives are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the power-down state a valid condition for guaranteed maximum write protection. During normal operation, the device is always energized with the standby current of ICC1.
Release Power Off/Device ID (ABH)
The Power Off Release/Device Identification command is a multipurpose command. It can be used to de-energize a device, obtain the device's electronic identification (ID) number, or both.
When used only to release the device from a power-down state, the device will resume normal operation after the duration of TRES1 (see AC characteristics) by issuing commands via drive /cs pin low, move command code "abh" and drive /cs high , and accept other commands. The /CS pin must be held high for the duration of TRES1.
When used only to get the device id in a non-power-down state, the instruction is initiated by driving the /cs pin low and shifting the instruction code "abh" followed by 3 dummy bytes. The device ID bits are then shifted outward on the falling edge of clk, most significant bit (msb) first, and the device ID values for W25P80 and W25P16 are listed in the Manufacturer and Device Identification tables. The device ID can be read continuously. This command is done by driving /cs high.
When used to release the device from the powered down state and get the device ID, the instruction is the same as described earlier and shown in Figure 13, except that after /cs is driven high, it must remain high for the period of tres2 flat (see AC characteristics). After this time, the device will resume normal operation and accept other commands.
If a power down/device id command is issued while an erase, program or write cycle (when busy is equal to 1) is being executed, the command will be ignored and will have no effect on the current cycle.
Release Power Off/Device ID Command Sequence Diagram Read Manufacturer/Device ID (90h)
The read-manufacturer/device-id command is an alternative to the power-off release/device-id command, which provides a jedec-assigned manufacturer-id and a specific device-id.
The Read Manufacturer/Device ID command is very similar to the Power Release/Device ID command. This instruction is initiated by driving the /cs pin low and moving the instruction code "90h", then moving the 24-bit address (a23-a0) 000000h. After that, the manufacturer ID and device ID of winbond (efh) are shifted outward on the falling edge of CLK, most significant bit (msb) first, and the device ID values of W25P80 and W25P16 are listed in the manufacturer and device identification table. If the 24-bit address is initially set to 000001H, the device ID is read first, then the manufacturer ID. Manufacturer and device IDs can be read continuously, from one to the other. This command is done by driving /cs high.

Read manufacturer/device ID (90h)
The read-manufacturer/device-id command is an alternative to the power-off release/device-id command, which provides a jedec-assigned manufacturer-id and a specific device-id.
The Read Manufacturer/Device ID command is very similar to the Power Release/Device ID command. This instruction is initiated by driving the /cs pin low and moving the instruction code "90h", then moving the 24-bit address (a23-a0) 000000h. After that, the manufacturer ID and device ID of winbond (efh) are shifted outward on the falling edge of CLK, most significant bit (msb) first, and the device ID values of W25P80 and W25P16 are listed in the manufacturer and device identification table. If the 24-bit address is initially set to 000001H, the device ID is read first, then the manufacturer ID. Manufacturer and device IDs can be read continuously, from one to the other. This command is done by driving /cs high.
For compatibility reasons, w25p80/16 provides some instructions for electronically determining device identification. The read jedec id instruction is compatible with the spi-compatible serial memory jedec standard adopted in 2003.
This instruction is initiated by driving the /cs pin low and moving the instruction code "9FH". Then the manufacturer id byte and the two device id bytes, memory type (id15-id8) and capacity (id7-id0) allocated by jedec for winbond (efh) will be shifted on the falling edge of clk, highest first Effective bit (msb), the memory type of W25P80 is 20h and the capacity is 14h; the memory type of W25P16 is 20h and the capacity is 15h.
The read parameter page command allows one or more bytes of a parameter page to be read. The instruction is initiated by driving the /cs pin low, then shifting the instruction code "53h" and the 24-bit address (a23-a0) into the di pin. Only the lower 8 address bits (a7-a0) are used and the upper 16 address bits (a23-a8) are ignored. Code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte at the address memory location will be shifted on the DO pin on the falling edge of CLK, MSB first. After each byte of data has been shifted out allowing a continuous stream of data, the address is automatically incremented to the next higher address. When the end of the parameter page is reached, the address wraps to the beginning. The read parameter page command is shown in Figure 18. If a read parameter page command is issued during an erase, program or write cycle (busy=1), the command will be ignored and will not have any effect on the current cycle. The read parameter page command allows clock rates from DC to reach the maximum FR (see AC Electrical Characteristics).
Quick read parameter page (5bh)
The fast read parameter page command is basically the same as the read parameter page command, except that it allows a faster clock rate to be used. A quick read of the Parameter Page instruction allows clock rates from DC to maximum FR (see AC Electrical Characteristics). This is accomplished by appending a "dummy" byte to the 24-bit address, as shown in Figure 19. Dummy bytes allow extra time for device internal circuits to set the initial address. The dummy byte data value on the DI pin is "don't care".
Program Parameters Page (52h)
The Program Parameter Page instruction allows programming of up to 256 bytes (128 words) in memory word locations that have previously been erased to all 1s "ffffh" (see Erase Parameter Page Instructions). The Write Enable command must be executed before the device accepts the Program Parameters Page command (status register bit WEL must be equal to 1). The instruction is initiated by driving the /cs pin low, then shifting the instruction code "52h" followed by the 24-bit address (a23-a0) and all 256 data bytes into the di pin. Only the lower 8 address bits (a7-a0) are used and the 16 most significant address bits (a23-a8) are ignored. Because the w25p80/16 program is incremented by one word (two bytes) at a time, the address must be an even address (a0 must be equal to 0). When data is sent to the device, the /cs pin must be held low for the entire length of the command. The program parameter page instruction sequence is shown in Figure 20.
The starting address needs to be set to 00h on the parameter page. If more than 256 bytes are sent to the device, addressing wraps to the beginning of the page. If a previously written data byte is overwritten, the data will be invalid.
In most applications, it is best to read the full 256-byte contents of a page into temporary RAM. The data can then be modified as needed, and the entire 256 bytes can be reprogrammed into the parameter page at once.
As with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte is locked. If this is not done, the parameter page program instructions will not be executed. After /cs is driven high, self-timed page program instructions will start within a period of tpp (see ac characteristics). While a page program cycle is in progress, the Read Status Register instruction can still be accessed to check the status of the busy bit. During a program cycle, the busy bit is 1 and becomes 0 when the cycle ends and the device is ready to accept other instructions again. After the program cycle is complete, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. If the address page is protected by the block protection (bp2, bp1, bp0) bits (see status register memory protection table), the program parameter page instruction will not execute.
Parameter page Program instruction sequence diagram Clear parameter page (D5H)
The Write Enable command must be executed before the device accepts the Erase Parameter Page command (status register bit WEL must be equal to 1). This instruction is initiated by depressing the /cs pin and moving the instruction code "d5h".
After locking the eighth bit, the /cs pin must be driven high. If this is not done, the Erase Parameter Page command will not be executed. After /cs is driven high, the self-timed erase parameter page command will begin within a period of tpe (see AC characteristics). While the Erase Parameter Page cycle is in progress, the Read Status Register instruction can still be accessed to check the status of the busy bit. During the erasing parameter page cycle, the busy bit is 1 and becomes 0 when complete, and the device is ready to accept other commands again. After the Erase Parameter Page cycle is complete, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. If any page is protected by the block protection (bp2, bp1, bp0) bits (see Status Register Memory Protection Table), the Erase Parameter Page instruction is not executed.