feature

Precision 2.5V to 5V supply monitor; 7 reset threshold options: 2.19 V to 4.63 V; 140 ms (min) reset timeout; 1.6 second timeout watchdog timer ( ADM823 , ADM824); manual reset input (ADM823) , ADM825); push-pull output stage; reset (ADM823); reset, reset (ADM824/ADM825); low power consumption: 5 µA; reset output guaranteed to be valid for VCC=1 V; power-fail immunity; over automotive temperature Range; 5-lead SC70 and SOT-23 packages.

application

Microprocessor systems; computers; smart meter controllers; portable equipment.

General Instructions

The ADM823/ADM824/ADM825 are supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor systems. In addition to providing a power-on reset signal, the on-chip watchdog timer can also reset the microprocessor if the microprocessor does not flicker within a preset timeout period. The reset signal can also be asserted by an external push button via the manual reset input. The three sections have different combinations of watchdog input, manual reset input and output stage configuration.

These parts have seven reset threshold options to choose from, ranging from 2.19 V to 4.63 V. The reset and watchdog timeout times are fixed at 140 ms (minimum) and 1.6 seconds (typical), respectively.

The ADM823/ADM824/ADM825 are available in 5-wire SC70 and SOT-23 packages and typically consume only 5 microamps, making them suitable for low-power portable applications.

Typical performance characteristics:

Circuit Description

The ADM823/ADM824/ADM825 provide the microprocessor with power supply voltage monitoring by controlling the microprocessor's reset input. By asserting the reset signal when the supply voltage is below a preset threshold, code execution errors during power-up, power-down, and power-down are avoided. Errors can also be avoided by fixing the time-out reset pulse to stabilize the supply voltage when the supply voltage rises above the threshold. Additionally, problems with microprocessor code execution can be monitored and corrected with a watchdog timer (ADM823/ADM824). By including a watchdog gating instruction in the microprocessor code, the watchdog timer can detect if the microprocessor code crashes or gets stuck in an infinite loop. If this happens, the watchdog timer asserts a reset pulse that restarts the microprocessor in a known state. If the user detects a problem with system operation, the manual reset input (ADM823/ADM825) can be used to reset the microprocessor using an external button (for example).

reset output

The ADM823 has an active low push-pull reset output, and the ADM824/ADM825 have dual active low push-pull and active high push-pull reset outputs. For active low and active high outputs, when VCC≥1V, the reset signal is guaranteed to be logic low and logic high, respectively.

The reset output threshold (VTH) will be asserted when VCC is below the reset value, when MR is driven low, or when WDI is not serviced within the watchdog timeout period (TWD). Reset remains asserted for the reset activity timeout period (TRP) after VCC rises above the reset threshold, after a low-to-high transition of MR, or after the watchdog timer expires. Figure 15 illustrates the behavior of the reset output.

Manual reset input

The ADM823/ADM825 have a manual reset input (MR) that asserts the reset output when driven low. When mr transitions from low to high, reset remains asserted for the reset active timeout period before releasing the asset. The mr input has an internal pull-up of 52 kΩ, so the input is always high when not connected. An external pushbutton switch can be connected between MR and ground for user-generated resets. A denoising circuit for this purpose is integrated on-chip. Provides noise immunity at the magnetic resonance input, ignoring fast negative-going transients up to 100 ns (typical). A 0.1µf capacitor between mr and ground provides additional noise immunity.

watchdog input

The ADM823/ADM824 have a watchdog timer that monitors microprocessor activity. With every low-to-high or high-to-low logic transition on the watchdog input pin (WDI), the timer circuit is cleared and WDI detects pulses as short as 50ns. The assertion resets if the timer counts by the preset watchdog timeout time (twd). The microprocessor needs to toggle the WDI pin to avoid reset. Therefore, the failure of the microprocessor to toggle the WDI within the timeout period indicates a code execution error, and the generated reset pulse will restart the microprocessor in a known state.

In addition to logic transitions on WDI, the watchdog timer can also be cleared by a reset assertion due to a brownout condition on V or MR being pulled low. When reset is asserted, the watchdog timer is cleared and does not restart counting until reset is released. The watchdog timer can be disabled by leaving WDI floating or by declaring three WDI drivers.

application information

Watchdog input current

To minimize watchdog input current (and minimize overall power dissipation), keep WDI low during most watchdog timeouts. When driven high, the WDI can sink up to 160 microamps. Pulsed WDI low-high-low at low duty cycles reduces the effects of large input currents. When WDI is not connected, the window comparator disconnects the watchdog timer from the reset output circuit so that a reset is not asserted when the watchdog timer times out.

Negative going V transient

To avoid unnecessary resets caused by fast power supply transients, the ADM823/ADM824/ADM825 are equipped with fault suppression circuitry. The typical performance characteristics in Figure 12 depict VCC transient duration versus transient amplitude. The curves show the combination of magnitude and duration of transients that do not produce a reset for the 4.63v and 2.93v reset threshold portions. For example, with a 2.93 V threshold, a transient 100 mV below the threshold and lasting 8 microseconds will not normally cause a reset, but if the transient is greater in magnitude or duration, a reset will be generated. An optional 0.1µF bypass capacitor installed near V provides additional fault suppression.

Make sure reset is valid to V=0 V

Active low and active high reset outputs are guaranteed to be valid for VCC as low as 1V. However, by using an external resistor with a reset output in a push-pull configuration, a valid output from VCC may be as low as 0V. For an active low reset output, a resistor connected between reset and ground pulls the output low when no current can be drawn. For an active high reset output, it will pull the output high when the resistor connected between reset and VCC cannot supply current. A large resistor, such as 100 kΩ, should be used so that the reset output is not overloaded when VCC is higher than 1 V.

Watchdog Software Considerations

When implementing a microprocessor watchdog strobe code, wdi needs to be toggled from low to high and then high to low quickly (minimizing wdi high time) for current consumption reasons. However, a more efficient approach using the watchdog function can be considered.

A low-high-low WDI pulse in a given subroutine prevents the watchdog from timing out. However, if the subroutine gets stuck in an infinite loop, the watchdog cannot detect this because the subroutine continues to toggle the WDI. A more efficient coding scheme to detect this error is to use a slightly longer watchdog timeout. In the program that calls the subroutine, WDI is set high (see Figure 18). The subroutine sets WDI low when called. If the program executes without error, WDI will toggle high and low on each cycle of the program. If the subroutine enters an infinite loop, WDI is held low, the watchdog times out, and the microprocessor is reset.