feature

Dual 10-bit, 40 msps, 65 msps, 80 msps, and 105 msps analog-to-digital converters; low power: 275 mW, 105 msec per channel; on-chip reference and track-and-hold; 300 MHz analog bandwidth per channel; signal-to-noise Ratio = 57dB @ 41MHz, Code = 80ms/sec; 1 V PP or 2 V PP analog input range per channel; 3.0 V single-supply operation (2.7 V to 3.6 V); power-down mode for single-channel operation; Binary or offset binary output mode Output data alignment mode; 8-bit AD9288 compatible pinout; –75 dbc channel-to-channel crosstalk.

application

Battery powered instruments; handheld oscilloscopes; low cost digital oscilloscopes; I and Q communications; ultrasonic equipment.

General Instructions

The AD9218 is a dual 10-bit monolithic sampling analog-to-digital converter with on-chip track and hold circuitry. The product has low cost, low power consumption, small size and convenient use. The AD9218 operates at a slew rate of 105 msps and has excellent dynamic performance over its entire operating range. Each channel can operate independently.

The ADC only needs a 3.0V (2.7V to 3.6V) power supply and a clock for full operation. Many applications do not require external references or driver components. The digital outputs are TTL/CMOS compatible, and separate output power pins support interfacing with 3.3V or 2.5V logic.

The clock input is ttl/cmos compatible, and the 10-bit digital output operates from a 3.0v (2.5v to 3.6v) power supply. User-selectable options provide combinations of power-down modes, digital data formats, and digital data timing schemes. In power-down mode, the digital outputs are driven to a high impedance state.

Product Highlights

1. Low power. At 105 msps, each channel consumes only 275 megawatts of power. Other speed grades are scaled down while maintaining high AC performance.

2. PIN compatibility upgrade. Allows easy migration from 8-bit devices to 10-bit devices. Pin compatible with the 8-bit AD9288 dual ADC.

3, easy to use. On-chip reference and user control provide flexibility in system design.

4. High performance. Use the Nyquist input to maintain a 54dB SNR at 105ms per second.

5. Channel crosstalk. Very low at -75 degrees Celsius.

6. Manufactured by advanced CMOS process. Available in a 48-lead low-profile quad flat pack (7 mm x 7 mm LQFP) specified over the industrial temperature range (-40°C to +85°C).

the term

analog bandwidth

Analog input frequency at which the fundamental frequency (determined by fft analysis) is reduced by 3 dB.

The instant between the 50% point of the rising edge of the aperture delay encoded command and the analog input is sampled.

Aperture uncertainty (jitter)

Sample-to-sample variation of aperture delay.

crosstalk

Coupling to a channel driven by a low-level signal when the adjacent interfering channel is driven by a full-scale signal.

Differential Analog Input Resistance, Differential Analog Input Capacitance, Differential Analog Input Impedance.

The actual impedance and complex impedance measured at each simulated point are input to the port. Resistance is measured statically, capacitance and differential input impedance are measured using a network analyzer.

Differential analog input voltage range

must be applied to the converter to produce a full-scale response. Peak differential is calculated by looking at the voltage on a single pin and subtracting the voltage from the other pin, i.e. 180 degrees out of sync. The peak-to-peak difference calculation formula is as follows. Rotate the input phase by 180 degrees and take the peak measurement again. Then calculate the difference peak measure between the two. Differential nonlinearity The deviation of any code width from the ideal 1lsb step size.

Effective Number of Bits (ENOB)

The number of significant digits is the formula-based signal-to-noise ratio measured according to:

Code Pulse Width/Duty Cycle

Pulse width high is the minimum time that the encoded pulse should remain in a logic 1 state to achieve rated performance; pulse width low is the minimum time the encoded pulse should remain in the low state. See time meaning change tench in text. These specifications define acceptable code duty cycles for a given clock frequency.

Full-scale input power

Expressed in dBm. Calculate using the following formula:

gain error

Gain error is the difference between the measured value and the ideal value of the ADC's full-scale input voltage range. Harmonic distortion, second rms signal amplitude and second harmonic component, expressed in dbc.

Harmonic Distortion, 3rd

RMS signal amplitude and third harmonic component, expressed by dbc.

Integral nonlinearity

The deviation of the transfer function from the reference line was determined by least squares curve fitting using a "best straight line" measured in fractions of 1 lsb.

Minimum conversion rate

Minimum analog signal-to-noise ratio encoding rate frequency drops not more than 3 dB below the guaranteed limit.

maximum conversion rate

The encoding rate when performing the parametric test.

output propagation delay

Output data bits for encoder A or encoder B and respective 50% level crossing channels.

Noise (applies to any range within the ADC):

where z is the input impedance, fs is the full scale of the device for the frequency in question, snr is the input level, and signal is the signal level within the ADC expressed in decibels below full scale. This value includes thermal noise and quantization noise.

power supply rejection ratio

The input offset voltage varies with the supply voltage.

Signal to Noise and Distortion (SINAD)

rms The ratio of the signal amplitudes (set to 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding DC.

Signal-to-noise ratio (no harmonics)

The ratio of the rms signal amplitude (set to a scale of 1 dB below full) to the rms value of the sum of all other spectral components, excluding the first five harmonics and DC.

Spurious Free Dynamic Range (SFDR)

RMS signal amplitude and peak spurious spectral components. Peak spurious components may or may not be harmonics. Reported in DBC (i.e. decreasing as signal level decreases) or dbfs (always related to back transition full scale).

Two-tone intermodulation distortion suppression

Worst third-order intermodulation product with the ratio of the rms value to the rms value of any input tone; reported in DBC.

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be IMD products. Reported in DBC (i.e. degraded when signal level decreases) or in dbfs (always correlated back to converter full scale).

worst other stimulus

The rms signal amplitude and worst spurious components (excluding second and third component harmonics) are expressed in dbc.

Transient response time

Transient response is defined as the time required for the ADC to regain the analog input negative full scale to 10% below positive full scale after a transient above 10%.

Out of range recovery time

The out-of-range recovery time is the time the ADC takes to regain the analog input positive full scale to 10% above negative full scale or 10% below negative full scale to 10% below positive full scale after a transient above 10%.

Equivalent Circuit:

Typical performance characteristics:

theory of operation

The AD9218 ADC architecture is a one-bit-per-stage pipelined type conversion using a switched capacitor technique. These internships determine 7 msbs and drive 3-bit flash. Each stage provides sufficient overlap and error correction to allow optimization or precision comparators. The input buffer is differential, and both sets of inputs have an internal offset. This allows the most flexibility to use either AC-coupled or DC-coupled differential or single-ended input modes. The output scratch block aligns the data, performs error correction, and feeds the output buffer's data. The output buffer banks are powered from separate power supplies, allowing the output voltage swing to be adjusted. There is no noticeable difference in performance between the two channels.

Use AD9218 to encode input

Any high speed ADC is very sensitive to the quality of the sample clock provided by the user. The track-hold circuit is essentially a mixer. Any noise, distortion or timing jitter on the clock is combined with the desired signal at the analog to digital output. Therefore, considerable care has been taken in designing the encoded input of the ad9218, and the user is advised to give corresponding consideration to the clock source. Encoded input is fully compatible with ttl/cmos.

digital output

The digital output is ttl/cmos compatible and consumes less power. During power down, the output buffer transitions to a high impedance state. The data format selection option supports two's complement (set high) or offset binary output (set low) formats.

analog input

The analog input of the AD9218 is a differential buffer. For best dynamic performance, the impedances at A and A should be matched. Special care was taken when designing the analog input section of the AD9218 to prevent corruption and data corruption if the input is too large. The nominal input range is 1.024v pp. The best performance is achieved with differential drive with minimal common-mode noise and reduced even-order harmonics. Figure 42 shows an example of the AD9218 differentially driven through a wideband rf transformer for an AC coupled application. As shown in Figure 43, applications requiring a dc-coupled differential driver can be regulated using the AD8138 differential output op amp.

voltage reference

A stable and accurate 1.25 V voltage reference is built into the AD9218 (VREF OUT). Typically, pin 5 (refa) and pin 7 (refb) are tied to pin 6 (ref) using an internal reference. The input range of each channel can be adjusted independently by changing the reference voltage input applied to the AD9218. When the reference value is adjusted to ±5%, there is no significant degradation in performance. The full-scale range of the ADC tracks the reference voltage, which varies linearly (a 5% change in VREF results in a 5% change in full scale).

opportunity

The AD9218 provides latched data outputs with five pipeline delays. Data output is available with a propagation delay (TPD) after the rising edge of the encode command (see Figure 2 through Figure 4). The length of the output data line and load placed on it should minimize transients within the AD9218. These transients can degrade the dynamic performance of the converter. The minimum guaranteed conversion rate is 20 msps. On-time rates are lower than 20 msps, and dynamic performance is degraded.

User select option

The two pins can be used in a combination of various modes of operation, allowing the user to power down both channels, excluding the reference, or just the B channel. Both modes place a buffer with the output in a high impedance state. The recovery state after power down is completed within 10 clock cycles after power up. Another option allows the user to ramp the b-channel output data for half a clock cycle. In other words, if two clocks are fed to the AD9218, 180 degrees out of phase, aligning the data allows channel B to output data on the rising edge of clock A. If supplying the same encoding clock is enabled for both the channel and the data alignment pins, the output data is from channel B to channel A. If both channels provide the same encoded clock channel and the data alignment pins are disabled, both outputs are transmitted on the same rising edge of the clock.

application information

The wide analog bandwidth of the AD9218 makes it ideal for a variety of high performance receiver and encoder applications. Figure 44 shows a typical low-cost I and Q demodulator implementation for cable, satellite or wireless LAN modem receivers. The dynamic performance of the ADC under the excellent high analog input frequency and code rate allows the user to use sampling techniques directly. If sampling eliminates or simplifies analog mixers and filter stages to reduce overall system cost and power.

Evaluation Committee

The AD9218/AD9288 customer evaluation boards provide an easy way to test the AD9218 or AD9288. Compatible pins for both parts facilitate testing either part using one PCB. PCBs require power, clock sources and filtered analog sources in order to do most of the ADC testing required.

power connector

Power is supplied to the board via a removable 12-wire power strip. The minimum 3V supplies required to run the board are V, V, and V. To allow the optional amplifier path to be used, a ±5V supply is required.

analog input

Each channel has an independent analog path that uses a wideband transformer to differentially drive the ADC from a single-ended sinusoidal source at the input SMA. The transformer path can be bypassed to allow the use of a dc-coupled path for two AD8138 op amps with simple board modifications. The analog input should be bandpass filtered to remove any harmonics from the input signal and to minimize aliasing.

voltage reference

The AD9218 has an internal 1.25 V voltage reference; an external reference per channel can be used instead by connecting two external voltage references at the power connector and setting jumpers at E18 and E19. The evaluation board is shipped configured in internal reference mode.

timing

Each channel can be coded A and coded B by a common clock input at the SMA input. Channels can also be independently clocked by a simple board modification. The clock input should be a low jitter sinusoidal source for maximum performance.

data output

The data output is latched onto the board via two 10-bit latches and drives an 8-wire connector that is compatible with dual-channel FIFO boards from Analog Devices, Inc. Together with the ADC analyzer software, this board can greatly simplify ADC testing.

Data Format/Gain

At the dfs jumper located on the s1, s2 jumpers, the dfs/gain pin can be biased for the desired operation.

opportunity

Timing on each channel can be controlled on the pcb if desired. If desired, the clock signal on the latch or the data ready signal into the output 80-wire connector can be inverted. Jumpers also allow biasing of pins S1 and S2 for power down and timing alignment control.

Troubleshooting

If the board is not working properly, try the following:

(1) Verify the power supply of the IC pins.

(2) Check that all jumpers are in the correct positions for the desired operating mode.

(3) Confirm that V is 1.23 V.

(4) Try running the encoding clock and analog input at low speed (20 msps/1 mhz) and monitor the LCX821 output, DAC output and ADC output for switching.

The AD9218 evaluation board is provided as a design example for analog equipment customers. Analog Devices makes no warranties, express, statutory or implied, of merchantability or fitness for a particular purpose.