Use PC board. The ground needle (pin 4) should be tightened directly ground plane, and the minimum lead length (A low -key socket is possible). Figure 7 shows the ideal LTC1292/LTC1297 ground floor design of the double panel. Of course, so many ground planes are not always possible, but users should work hard to approach for this ideal.

Wing by

In order to achieve good performance, VCC must have no noise and ripples. Any change in the VCC voltage may cause noise in errors or output code within the conversion cycle. VCC noise and ripples can keep the VCC pins directly bypass to the ingredients with an analog ground capacitor and lead that is at least 22 μF. The clue from the device to the VCC power supply should also be maintained at the minimum value, and the VCC power supply should have low output impedance, such as the impedance obtained from the voltage regulator (such as LT323A). For high -frequency bypass, 0.1 μF and 22 μF parallel placed ceramic disk recommendation. Similarly, the wire should be kept at the minimum. Figures 8 and 9 show bad bypass by GOOD and VCC.

Simulation input

Because the technology used by the capacitor re -assigns A/D conversion, the analog input/LTC1297 of the LTC1292 has a capacitor switch input current peak. These current peaks are quickly stabilized and will not cause problems. If a large source resistance or slow and stable operation amplifier driver input, pay attention to ensure that the transients caused by the current peak completely disappear before the conversion starts.

Source resistance

The analog input of LTC1292/LTC1297 looks like 100pf capacitors (CIN) and 500 10A and 10B). CIN switch between (+) and between ( -) in each conversion cycle once. Large external source resistance and capacitors will reduce the input settings. It is important that the entire RC time constant is short enough to allow simulation input to be completely solved within the allowable time. ""+"" Input Set the input capacitor of LTC1292 to switch to ""+"" (TSMPL, see Figure 11A, 11B and 11C) in the sampling stage. The sampling cycle can be shortened to TWHCS+1/2 CLK cycle or before the start of the conversion as the TWHCS+1 1/2 CLK cycle. This variability depends on the decline in CS compared to CLK. The voltage of the ""+"" input end must be completely precipitated during the sample period. To minimize RSOURCE+and C1 will improve the settlement time. If the large ""+"" input source must use the resistance, the sampling time can be increased by using the slow CLK frequency. The shortest sampling time is 3.0 μs, rsource+ lt; 2.0kc1 lt; 20PF will provide sufficient settlement time.

The sampling cycle of the LTC1297 starts from the edge of the CS and the end of the first CLK's decline (Figure 12). The length of the sampling cycle is TSUCS+0.5CLK cycle. Similarly, the voltage of the ""+"" input end must be stable and completely within the sample period. If you enter the ""+"" large source resistance, the sampling time can be used by using a slower CLK frequency or increased

Tsucs. The shortest sampling time is 6 μs, rsource+ lt; 5K and C1 LT; 20pf will provide sufficient stable time. Under normal circumstances, LTC1292 and LTC1297 maintain total resistance and total resistance than TSMPL/9. If this situation cannot be met, then C1 GT; 0.47μF (see RC input filter section).

"" -"" Input settings

At the end of the sampling phase, the input capacitor is switched to "" -"" input, and the conversion starts (see Figure 11A, 11B, 11C, and 12). During the conversion process, the ""+"" input voltage is effectively ""maintained"" and does not affect the conversion result. The most important thing is

"" -"" input voltage no noise, completely stable during the first CLK cycle of the conversion. To minimize RSOURCE -and C2 will improve the settlement time. If the large "" -"" input source resistance must be used, it can be expanded by using a slower CLK frequency. At most, the CLK frequency is 1MHz, rsource - lt; 250 and C2 LT; 20PF will provide sufficient settlement.

Enter the operational amplifier

When the calculation amplifier is used to drive an analog input, it is important to stabilize the operation amplifier within the allowable time (see Figure 11A, 11B, 11C, and 12). Besides, ""+"" and ""-"" Input sampling time can be extended by instructions to adapt to slower calculation amplifiers. Most computing amplifiers include LT1797 and LT1677 single power supply amplifiers even if they use the minimum sedimentation volume, which can make the sedimentation good for LTC1292, the window is 3.0 μs, for the maximum clock frequency frequency of LTC1297 (""+"" input) and 1 μs ("" -"" input) 1MHz. Figure 13 and 14 show an example of appropriate and poorly setting amplifiers.

RC input filter

You can use RC network filtering input as shown in Figure 15. For larger CF values u200bu200b(for example, 1 μF), the capacitor input switch current is average to a DC current in one network. The filter should use small resistors and large capacitors to prevent DC voltage from falling over the resistor. The size of the DC current is aboutIDC u003d 100pf × Vin/TCYC is roughly proportional to Vin. when? Run LTC1292 (LTC1297) at a minimum period of 16.5 μs (20μs), and the input current is equal to 30 μA (25μA) at VIN u003d 5V. At this time, the filter resistance of the 4 (5 ) will cause the 0.1LSB full marking error. If a large filter resistance must be used, it can be used to increase the characteristic curve time of the maximum filter resistance and the cycle of the cycle time shown in the typical performance.

Input leakage current

Input leakage current will also be too much resistance. For example, the 1 μA leakage specification of the maximum input flow source 1K can cause 1MV or 8 pounds. This error will greatly reduce the rapid decline in leaks (see typical input channel leakage performance characteristic curve current and temperature).

Sample reservation

Single -end input

LTC1292/LTC1297 provides a built -in sampling and maintenance signal to the acquisition signal (s amp; h) function to collect signals (s amp; h) at the+in input terminal. In a single -end mode ( -needle ground ground). Sampling and keeping allowed LTC1292/LTC1297 to quickly convey the change signal (see typical performance characteristics s amp; AMP; H collection time and source resistance curve). This input voltage is sampled in TSMPL time, as shown in Figure 11 as shown in Figure 11. The sampling interval starts from the rise of the CS edge of the LTC1292 and the edge of the CS decline. For LTC1297, CLK continues until the beginning of the conversion. At this decreased edge S AMP; AMP; H enter the maintenance mode and the conversion begins.

Differential input

with differential inputs, A/D no longer converts a single but converts the difference between two voltages. Sample the voltage on the+IN pin and keep changing quickly, such as a single -end mode. The voltage must be kept in the entire conversion process of the voltage and no noise. Otherwise, the differential operation cannot be performed accurately. This conversion time is the 12 CLK cycle. Therefore, input voltage can cause conversion errors within this time. This error input this error for the input terminal:

where f (–IN) is the frequency of the input voltage, VPEAK is its peak amplitude, and FCLK is Clek. Usually, errors are not important. For the signal of the 60Hz input terminal to generate a 0.25LSB error (300 μV), the peak must be 66mv when the converter runs at CLK u003d 1MHz. Re -arrange the maximum sine signal digitalization of the above content of the above content to the formula of a given accuracy as follows:

For 0.25LSB error (3 3]00 μV), the switch current generated by the maximum input sine curve switching capacitor conversion technology (see Figure 16). The capacitor current A/D of the conversion (each CLK cycle) during each bit test will generate a peak on the reference pin. These current peaks are quickly stabilized and will not cause problems. If the slow settlement circuit is used to drive reference inputs, it is important to ensure that the transient peaks are tested 5V peak amplitude to 0.8Hz due to the conversion of these current peaks.

Reference input

LTC1292 Reference voltage/LTC1297 determines the voltage range of the A/D converter. Reference input has transient capacitance

Figure 17 and 18 show the proper and settlement difference. Using the slower CLK will allow more time to reference settlement. Even at the rate of 1MHz at the highest clock, most references and operational amplifiers can sink within a time of 1 μs. For example, the LT1790 will be fully resolved.

Simplified reference operation

The effective resolution of the LTC1292/LTC1297 can be increased by reducing the input range of the converter. LTC1292/LTC1297 has a good linear within a reference voltage range (see linearity and reference voltage). Due to the decrease in LSB, when operating at a low VREF value, you must be carefully stepped on the converter when operating at a low VREF value. Shooting and noise must consider this value when running under low VREF. VREF's internal reference has been bound to the GND pin. From GND pins to ground layers will cause gain errors. Reduce the offset of VREF's offset LTC1292/LTC1297 to reduce the reference voltage when the output code is reduced during A/D operation. The displacement (usually a fixed voltage) becomes the size of the size of LSB. The typical unsettled offset error is related to the performance characteristic curve of the reference voltage, which shows that the existing volume is related to the reference voltage. It is a typical value about VOS. For example, 0.1MV VOS, that is, 0.1LSB In the case of 5V, the reference voltage becomes 0.4LSB and the voltage is 1.25V reference. If this offset is unacceptable, you can use digital corrections by receiving systems or offset LTC1292/LTC1297 input.

Reduce the noise of VREF

The total input noise of the LTC1292/LTC1297 can be available on the plane, good bypass, good layout technology about input and minimizing noise. This noise is insignificant under the 5V reference input, but it has become a larger part of LSB as a decrease in LSB. Typical performance characteristic noise errors and reference voltage relationship curves show the LSB contribution of 200 μV noise. For the operation of 5V reference voltage, 200 μV noise is only 0.16LSB in the peak. here isLTC1292/LTC1297 noise will hardly pay for the output code. For reference, noise may become an important part of LSB's output code that is not needed in the output code. For example, under 1.25V reference voltage, the peak between 200 μV noise is 0.64LSB. This will reduce the range of input voltage through it to obtain a stable output code 0.64 pounds. The average reading may now be necessary. These noise data are collected in a very clean test fixture. Any settings caused by settings (noise or ripples or VIN on VREF) increase internal noise. The lower the reference voltage, the higher the noise setting. The gain error caused by the gain error caused by VREF LTC1292/LTC1297 is very good in the extensive reference voltage range. The change of component gain error error and the characteristic curve of the reference voltage in the typical properties are from the device to the horizon caused by the voltage drops on the GND pins. Try to minimize this situation error LTC1292/LTC1297 should be welded directly to the PC board. Internal reference points are connected to GND because VREF is connected to GND. Whether the GND pin has a voltage drop, the reference voltage is less than the value of the external application inside the device (Figure 19). Due to the product of the pin, the voltage drop is usually 420 μV resistor (RPIN) and the LTC1292/LTC1297 power supply.

For example, when VREF u003d 1.25V, this will cause vRF u003d 5V measurement when the gain error and the gain error-1.0LSB. LTC1292 AC characteristics Two commonly used advantages numbers, used to specify the dynamic performance processing application of A/DS in the digital signal is the signal -to -noise ratio (SNR) and ""ENOB)."" SNR is the average root root value of Kobo The average root value of all non -base wave signals has the frequency of Danaquist (half of the sampling frequency). The maximum signal -to -noise ratio of the sine wave is input. The signal -to -noise ratio u003d (6.02n+1.76db) of n is the number of bites. Therefore, the signal -to -noise ratio depends on the resolution of A/D. The ideal 12 -bit A/D signal -to -noise ratio is equal to 74DB. In the fast Fourier transform chart, the output spectrum chart of the LTC1292 is in Fig. 20A and 20B, the input (fin) frequency is 1kHz and 28kHz, and the sampling frequency (FS) is 58.8 kilo. The measured SNR is 73.0db61.5 decibels. By rewriting the SNR expression, the equivalent resolution based on the signal -to -noise ratio can be obtained.

This is the validity number (enob). For examples, as shown in Figure 20A and 20B, n u003d 11.8 bits and 9.9 bits. FIG. 21 shows the function of enob as the input frequency. The second harmonic disturbance explains the enob as fin is close to FS/2. Figure 22 shows two tones applied to A/D input. Non -linear in A/D,It will lead to different frequencies of the total and basic principles and basic principles of distortion products. This is a classic statement as an distortion (IMD).

Overvoltage protection

The simulation of the signal to LTC1292/LTC1297 exceeds the positive power supply or the input floor below the positive power supply will reduce a A. /D's accuracy and may damage the device. For example, if the signal is applied to analog input, it will occur before the LTC1292/LTC1297 is powered on. Another example is that the input source is more valuable from LTC1292 more valuable supply/

LTC1297. These situations should also be prevented by proper supply order or use of external clamps or current restricting input sources. There are two ways to protect input. Use diode clips from the input terminal of VCC and GND in FIG. 23. The second method is to input the resistor and current limit simulation. Limit the current to 15mA per channel. +In input can accept a resistor value of 1k, but the –in input cannot accept more than 250 when its maximum clock frequency is 1 meter. If the LTC1292/LTC1297 is not enough to limit the input source at the maximum clock frequency and 250 then the diode is recommended (Figure 24A and 24B). The reason for the resistance value is that the MSB bit test is affected by the resistance value of the resistance at the –in (see the maximum clock frequency VS source resistance of simulation input and typical performance characteristics).

If VCC and VREF are not connected, then VCC should be opened first, and then open VREF. If this sequence cannot be met, it is recommended to connect the diode from VREF to VCC (see Figure 25). Because the unique input protection structure is used for digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device.

The ""Quick View"" circuit user of LTC1292 can quickly understand the ""Quick View"" circuit in the LTC1292 in the figure of the ""Quick View"" circuit in the figure 26VREF and VCC binding. VIN is used to connect to the horizon with+in input input terminal. CS is driven by CD4520 and DOUT data at a clock rate of 1/32. The output data of DOUT tube foot can be viewed on the trigger oscilloscope (Figure 27). Note that LSB data is punch -in before the CS is higher.

The ""Quick View"" circuit of LTC1297 is similar to the LTC1292 circuit that can be used for LTC1297 (Figure 28). Only one chance to meet the setting time TSUCS with non -door, resistance and capacitors. If you use a slower clock. Triggered when the CS becomes lower. This will turn off the fixed time of the LTC1297 clock. See Tsucs. The clock is from the beginningDuterte began to move a little.CS drives the clock rate at a speed of 1/64 to 74HC393.The output data can be triggered on the setting of the double -footed foot CS on the settings.See Figure 29.

The light isolation temperature monitor

usually requires enlarging the output of the sensor to generate a sufficient large signal to correct digitalization.For example, the J -type thermocouple provides only 52 μV/° C.The error caused by the 5 μV offset AMP operation of the LTC1050 beep operation is less than 0.1 ° C (Figure 31).Cold knot compensation is provided by LT1025A.(For more details, please refer to the LTC design annotation 5).A two signals generate in the light isolation interface from the beginning.This allows a two -line interface to connect to the LTC1292 type.CLK in input The height signal ( gt; 1ms) allows 0.1 μF capacitors to discharge at high CS.This will reset the next conversion A/D.When CLK starts to switch, CS becomes lower and keeps there until the next extend the clock in the next high time.See Figure 30.