W681360 is a general purpose single channel 13 bit line pcm codec with 2 full and tssop pack options. The main function of the device is digitization and reconstruction. For speech signals, including band limiting and smoothing required by pcm systems. w681360 performance is specified over the industrial temperature range -40°C to +85°C.
The W681360 includes an on-chip precision voltage reference. The analog part is fully differential and the VAG reference pin allows the internal circuit that generates the reference voltage to be disconnected from the vehicle speed sensor power supply Minimal ground clock noise on the analog circuit when referencing an external analog signal Synchronous and asynchronous are used for communication of pcm applications. w681360 at 256kHz and 480mHz, the on-chip prescaler automatically determines Crook.
1. An additional on-chip power expander capable of driving 3000 different oya loads up to 354V peak-to-peak.
For quick evaluation, a development kit (W681360DK) is available. For rapid prototyping, a low-cost evaluation board (W681360ES) is also provided.
Features
8226 ; single +3V supply (2.7V to 5.25V)
•Typical power consumption: 9.8mW Standby power consumption: 3µm Power-down loss: 0.09µm •Fully differential analog circuit design for low noise •13-bit line A/D&D/A convention with 2s Supplementary data grid •Compliant with Codec A /D and D/A filtering with ITU G.712
• 8 256kHz master clock frequency 4800MHz • 256kHz to 4.8MHz serial pcm port • Chip accuracy reference is 0.886 V
• Operating range (-40°C to +85°C)
• 20-pin SOG (SOP), SSOP and TSSOP assemblies • Lead-free/RoHS packaging options available • VoIP, VoIP devices • Wireless voice devices • DECT/digital cordless phones • Broadband access devices • Bluetooth sites • Fiber to the curb Equipment • Business Phone • Digital Voice Recording
W681360 Block Diagram

Function description
The W681360 is a single-track single-channel PCM codec for soundtrack applications. The codec conforms to the specifications recommended by ITU-T G.712.
The codec block diagram in Section 3 illustrates the main components of the w681360. The chip includes a pcm interface that can handle long and short frame sync formats. The prescaler chip provides the internal clock signal and synchronizes the codec sample rate with the external frame frequency. The power conditioning block is the digital and analog section, while the voltage reference block provides the ground voltage for accurate analog analog signal processing.
The calibration level of the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC) refer to the μ-law and have the same bit voltage, called a zero-crossing, resulting in a 0dBm0 calibration level 3.2db below the peak sine level, at clipping Before the wave, based on a calibrated level of 0.436vrms or -5dbm at 600Ω at a reference voltage of 0.886v.

W681360 Signal Path

The first stage of the codec a to d path is the analog input operating an amplifier with externally configurable gain settings. Differential analog inputs can be applied to inputs ai+ and ai-. Alternatively, the input amplifier can also be powered down and a single-ended input signal can be applied to the AO pin or the AI pin. The input amplifier can be powered down or vss by connecting the ai+ pin to either vdd, which also depends on
W681360 AO pin becomes high input impedance when input op amp is powered down

Input op amp gain - differential input For microphone interface circuits, the gain of the op amp is usually set to 30db. However, gain can be used above 30dB, but this will require a compact layout, minimum trace length and good isolation from noise sources. It is also recommended that the layout be designed for unbalanced operation as symmetrical as possible to counteract the noise advantage of the differential.
receive path
The 13-bit digital input samples of the d-to-a path are shifted in serially by the pcm interface and converted to parallel data bits. In each cycle of the frame sync fsr, the parallel data bits are fed through a 13-bit linear DAC and converted to analog samples. The analog samples are passed through a low-pass smoothing filter according to the ITU-T G.712 specification with a cutoff frequency of 3.4 kHz.
sin(x)/x compensation is integrated with a low-pass smoothing filter. The output of this filter is buffered to provide the receive output signal ro-. When the device is in receive path adjustment mode. If the device uses the fst pin for half-channel operation clock and the fsr pin is held low, the receive filter input will be connected to the VAG voltage. This minimizes transients at the RO pin when full channel operation is resumed by timing the FSR pin.
The reverse osmosis output can be connected externally to the PAI pin to provide high drive capability on the PAO+ and PAO- pins. By using an external resistor, it is possible to set the output amplifier. If the transmit power amplifier is not in use, it can be shut down by connecting PAI to VDD. The bias voltage and signal reference for the pao+ and pao- outputs are the vagus pins. The VAG pins cannot source or sink current like these pins, so a low current impedance load must be placed between pao+ and pao-. The PAO+ and PAO- differential drivers are also capable of driving 100Ω resistive loads or with 20Ω resistors with a slight increase in distortion. These drivers can be used to drive 32Ω when the gain of pao- is set to 1/4 or less.

Receive gain adjustment mode
The W681360 can enter receive path adjustment mode by applying logic "1" to the BCLKR pin while all other clocks are clocked normally. The device is then in a position to read the 16-bit data, using three additional coefficient bits, to add the 13-bit digital speech data. These three coefficients are used to program the receive path attenuation so that the receive signal is attenuated according to the values in the table below. If this feature is not used, the default value is 0db.
Attenuation coefficient relationship in receive gain adjustment mode

Power Management Analog and Digital Power
The power supply for the analog and digital parts of the W681360 must be 2.7 volts to 5.25 volts. voltage is connected to the VDD pin. The VDD pin needs to be separated from ground by a 0.1µF ceramic capacitor.
Analog Ground Reference Bypass The system has an internal precision voltage reference that generates a VDD/2 mid-supply analog ground voltage. This voltage needs to be separated from the vss capacitor at the VREF pin through a 0.1µf ceramic.
Analog Ground Reference Output An analog ground reference can be used as an external reference to the VAG pin. This voltage needs to be separated from vss by a 0.01µf ceramic capacitor. The analog ground reference is generated from the voltage on the VREF pin and is also used for internal signal processing.

pcm interface
The pcm interface is controlled by pins bclkr, fsr, bclkt and fst. The input data is received through the pcmr pin, and the output data is transmitted through the pcmt pin. Long frame sync or short frame sync interface modes can be selected by connecting BCLKR or connecting the BCLKT pin to a 256kHz to 4.800MHz clock and connecting the FSR or FST pin to an 8kHz frame sync. The device synchronizes the data word of the pcm interface and the positive edge of the frame sync signal on the codec sample rate. Long frame sync is recognized when the fst pin is held high on two consecutive falling edges of the BCLKT pin bit clock. The short frame sync mode is when the frame sync signal at pin fst is bit clocked to the BCLKT pin.
Long Frame Sync The device recognizes the bit clock edge of the Long Frame Sync BCLKT pin when the fst pin is brought high for two consecutive falls. The length of the frame sync pulse can vary from frame to frame, as long as the frame sync edge occurs every 125µs. In the long frame sync mode, the transmit data pin pcmt is high when the frame sync signal fst is high or when a 13-bit data word is transmitted. Transmit data pin When data is frame sync signal fst goes low, pcmt will go high impedance or when half of lsb is sent. Internal decision logic will decide whether the next frame sync is a long or short frame sync based on the previous frame sync pulse. To avoid bus collisions, the pcmt pin will have a high impedance state for two frame sync cycles after each power down. The long frame sync mode is shown in the figure below. More detailed timing information can be found in the Interface Timing section.

Short Frame Sync When the frame sync signal at pin fst is one of the BCLKT pin bit clocks and only one falling edge is high. On the following rising edge in the bit clock, the w681360 starts clocking the data on the pcmt pin, which also changes from high impedance to low impedance. The data transfer pin pcmt will return a high impedance statement midway through the LSB. The short frame synchronization operation of the W681360 is based on a 13-bit data word. When data is received on the pcmr pin, the data is on the falling edge consistent with the frame sync signal. Internal decision logic will decide whether the next frame sync is a long frame sync or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the pcmt pins will be in every power down state. The short frame sync mode is shown below. More detailed timing information can be found in the Interface Timing section.

System Timing System operating frequency is 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz & 4800KHz master clock rate. The system clock is input to mclk via the master clock and can be derived from the bit clock if desired. An internal prescaler is used to generate a fixed 256kHz and 8kHz sample clock for the internal codec. The prescaler measures the master clock frequency versus the frame sync frequency and sets the division ratio accordingly. If both frame syncs are present when the MCLK and BCLK pins clock signals are still present, the W681360 will enter a low power standby mode with a low level for the entire frame sync cycle. Another way to power off is to set the pui pin low. When the system needs to be powered up again, the pui pin needs to be set high, then the transmit frame sync pulse needs to be present. becomes low impedance at pin pcmt.
On-Chip Power Amplifiers On-chip power amplifiers are typically used to drive external speakers. Inverting input power amplifiers are available on pin pai. The non-inverting input is internally connected to VAG. This inverted output PAO- is used to provide a feedback signal to the PAI pin to set the power gain amplifier outputs (PAO+ and PAO-). These push-pull outputs are capable of driving 300Ω load volts peak.
Connecting PAI to VDD will turn off the power driver amplifier and the PAO+ and PAO- outputs will be high impedance.

Timing diagram

Typical Application Circuit

Packing Drawings and Dimensions
20L Potassium Sulfate (SOP) - 300ml Small Outer Package (Same as SOIC) Size