feature

Fast 12-bit adc with 5.9ms conversion time; eight single-ended analog input channels; selection of input ranges: 610 V for AD7890-10 ; 0 V to 14.096 V for AD7890-4; 0 V to 12.5 V for AD7890-2 ; allows separate access to multiplexer and ADC; on-chip track/hold amplifier; on-chip reference; high-speed, flexible, serial interface; single-supply, low-power operation (50 mW max); power-down mode (75 mW typical) .

General Instructions

The AD7890 is an 8-channel 12-bit data acquisition system. This section includes an input multiplexer, on-chip track/hold amplifier, high-speed 12-bit ADC, a+2.5v reference, and a high-speed serial interface. The part operates from a single +5 V supply and accepts analog input ranges of ±10 V (AD7890-10), 0 V to +4.096 V (AD7890-4), and 0 V to +2.5 V (AD7890-2).

Multiplexers on parts can be accessed independently. This allows the user to insert anti-aliasing filters or signal conditioning (if required) between the multiplexer and the ADC. This means that one antialiasing filter can be used for all eight channels. The connection of an external capacitor allows the user to adjust the time set for the multiplexer to include any external delays in the filter or signal conditioning circuit.

The output data of the AD7890 is provided through a high-speed bidirectional serial interface port. This section contains an on-chip control register that allows channel selection, conversion start, and power-down to be controlled via the serial port. Versatile, high-speed logic ensures easy interface to serial ports of microcontrollers and digital signal processors.

In addition to traditional DC accuracy specifications such as linearity, full scale, and offset error, the AD7890 specifies dynamic performance parameters including harmonic distortion and signal-to-noise ratio.

Power consumption in normal mode is low at 30 mW (typ), and the part can be put into standby (power-down) mode if conversions do not need to be performed. The AD7890 is fabricated using the Analog Devices Linear Compatible CMOS (LC2MOS) process, a hybrid process that combines precision bipolar circuitry with low-power CMOS logic. The part is available in a 24-pin, 0.3" wide, plastic or hermetic dual in-line package or a 24-pin Small Outline Package (SOIC).

Product Highlights

1. A complete 12-bit data acquisition system on chip The AD7890 is a complete monolithic ADC that combines an 8-channel multiplexer, a 12-bit ADC, a +2.5V reference voltage, and a track/hold amplifier on a single chip.

2. Independent access to multiplexer and ADC

The AD7890 provides access to the output of the multiplexer, allowing the use of one antialiasing filter for eight channels—a considerable savings over the eight antialiasing filters required if the multiplexer is connected internally to the ADC more time.

3. High-speed serial interface

This part provides a high-speed serial interface for easy connection with serial ports of microcontrollers and dsp processors.

Timing Characteristics 1, 2 (VDD=+5 V 6 5%, AgNd=dGnd=0 V, Ref-In=+2.5 V, FCLK-In=2.5 MHz external, MUX-Out connected to SHA-In.)

The AD7890 is production tested with FCLK-In at 2.5 MHz. Its features are guaranteed to work at 100khz. 4 are specified using the 10% and 90% points on the waveform of interest. 5 of these numbers are measured with the load circuit in Figure 1 and are defined as the time it takes for the output to cross 0.8 volts or 2.4 volts.

These numbers are derived from the measurement time it takes for the data output to change by 0.5 V when the circuit of Figure 1 is loaded. The measurements were then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. This means that the time quoted in the timing characteristics is the true bus abandon time of the part and is therefore independent of the external bus load capacitance.

term signal-to-noise ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals up to half the sampling frequency (fs/2), except DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio of an ideal n-bit converter with a sine wave input is given by:

So for a 12-bit converter, that's 74 dB.

total harmonic distortion

Total Harmonic Distortion (thd) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7890, the definitions are as follows:

where v1 is the rms amplitude of the fundamental and v2, v3, v4, v5 and v6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fs/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. An intermodulation term is a term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7890 is tested using the CCIF standard, which uses two input frequencies near the top of the input bandwidth. In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the thd specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dbs.

Isolation between channels

Inter-channel isolation is a measure of the level of cross-talk between channels. Measured by applying a full-scale 1khz signal to any of the other seven inputs and determining how much that signal is attenuated in the channel of interest. The numbers given are the worst of the eight channels.

Relative accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line through the endpoints of the ADC transfer function.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7890-10)

This is the deviation of the last code transition (01). ...110 to 01....111) After adjusting the bipolar zero error, start with the ideal value (4 × ref in – 1 lsb).

Positive Full-Scale Error (AD7890-4)

This is the deviation of the last code transition (11). ... 110 to 11. ...111) After adjusting for the unipolar offset error, start with the ideal value (1.638 × ref in – 1 lsb).

Positive Full-Scale Error (AD7890-2)

This is the deviation of the last code transition (11). ...110 to 11. ...111) After adjusting for the unipolar offset error, start with the ideal value (ref in – 1 lsb).

Bipolar Zero Error (AD7890-10)

This is the deviation of the mesoscale transition (from 0 to 1) from the ideal 0v (agnd).

Unipolar Offset Error (AD7890-2, AD7890-4) This is the offset of the first code transition (00). ... 000 to 00. ...001) from an ideal 0V (AgNd).

Negative Full-Scale Error (AD7890-10)

This is the deviation of the first code transition (10). ... 000 to 10. ...001) After adjusting the bipolar zero error, start from the ideal value (–4 × ref in + 1 lsb).

Track/Hold Acquisition Time

Track/Hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1/2 lsb) after the conversion ends (the point at which the track/hold returns to track mode). It also applies when there is a change in the selected input channel, or when there is a step input change in the input voltage applied to the selected vin input of the AD7890. This means that the user must wait for the duration of the track/hold acquisition time after the conversion ends or after the channel change/step input changes to vin before starting another conversion to ensure the part is operating to specification.

control register

The control register of the AD7890 contains 5 bits of information as described below. Six serial clock pulses must be supplied to the part in order to write data to the control registers (seven if a write is required to put the part in standby mode).

If tfs returns high before six serial clock cycles, then no data is transferred to the control register and the write cycle must be restarted to write data to the control register. However, if the register's conv bit (see below) is set to logic 1, then no matter how many serial registers there are, as long as the control register is written, a conversion is initiated for the clock cycle that tfs remains low. The default (power-up) condition of all bits in the control register is 0.

Converter Details

The AD7890 is an 8-channel, 12-bit, single-supply, serial data acquisition system. It provides users with signal scaling, multiplexing, track/hold, reference, A/D converter, and versatile serial logic functions. Signal scaling allows parts that handle ±10 V input signals (AD7890-10) and 0 V to +4.096 V input signals (AD7890-4) while operating from a single +5 V supply. The AD7890-2 does not include signal scaling and accepts an analog input range of 0 V to +2.5 V. The part operates from a +2.5 V reference, which can be sourced from the part's own internal reference or an external reference.

Unlike other single-chip data acquisition solutions, the AD7890 provides the user with separate access to the multiplexer and A/D converter. This means that the flexibility of a separate multiplexer and ADC solution is not sacrificed by a single-chip solution. By accessing the multiplexer output, the user can implement external signal conditioning between the multiplexer and track/hold. This means that an antialiasing filter can be used at the output of the multiplexer to provide antialiasing for all eight channels.

Either by pulsing the convst input on the AD7890 or by writing a logic 1 to the control register. When using the hardware convst input, the rising edge of the convst signal is turned on, the on-chip track/hold goes from track to hold mode, and the conversion sequence is initiated with an internal pulse timeout. This internal pulse (appearing on the C EXT pin) is initiated whenever the multiplexer address is loaded into the AD7890 control register. This pulse goes from high to low when a serial write to the part is initiated. In a serial write operation to the part, it begins to discharge on the sixth falling clock edge of SCLK. Track/Hold cannot go into hold and a conversion cannot start until the C EXT pin crosses its 2.5 V trigger point. The discharge time of the voltage on C EXT depends on the value of the capacitor connected to the C EXT pin (see the C EXT function section). The pulse is triggered every time the control register is written, which means that the software conversion start and track/hold signals are always delayed by the internal pulse.

The component's transition clock is generated by a clock signal applied to the component's clk in pin. The conversion time of the AD7890 is 5.9 microseconds from the rising edge of the hardware convst signal and the track/hold acquisition time is 2 microseconds. For best performance from the part, data reads or control register writes should not occur during a conversion or during the 500 ns period before the next conversion. This allows the part to operate at throughputs up to 117 kHz in external clock mode and meet data sheet specifications. The part can operate at slightly higher throughput rates (up to 127 kHz), also in degraded external clock mode (see Timing and Control section). The throughput rate in self-clocked mode is limited by the serial clock rate to 78 kHz.

All unused inputs should be connected to voltages within the nominal analog input range to avoid noise pickup. On the AD7890-10, if any of the unconverted input channels have a negative voltage of more than -12v, it will interfere with the conversion on the selected channel.

Circuit Description Analog Input Section

The AD7890 consists of three parts, the AD7890-10 handles the ±10 V input voltage range, the AD7890-4 handles the 0 V to +4.096 V input range, and the AD7890-2 handles the 0 V to +2.5 V input voltage range.

AD7890-10

Figure 2 shows the analog input section of the AD7890-10. The analog input range of each analog input is ±10 V, and the input resistance is typically 33 kΩ. This input is benign, has no dynamic charging current, the resistive attenuator stage is followed by a multiplexer, and with the mux out connected to the SHA, this input is followed by the high input impedance stage of the rail/hold amplifier. The designed transcoding occurs on consecutive integer lsb values (ie, 1 lsb, 2 lsb, 3 lsb...). The output encoding is 2s complement binary, 1 LSB – fs/4096=20 V/4096=4.88 mV.

AD7890-4

Figure 3 shows the analog input section of the AD7890-4. The analog input range for each analog input is ±10 V, and the input resistance is typically 15 kΩ. This input is benign, has no dynamic charging current, the resistive attenuator stage is followed by a multiplexer, and with the mux out connected to the SHA, this input is followed by the high input impedance stage of the rail/hold amplifier. The designed transcoding occurs on consecutive integer lsb values (ie, 1 lsb, 2 lsb, 3 lsb). …). The output code is straight (natural) binary, 1 LSB=fs/4096=4.096 V/4096=1 mV.

track/hold segment

The SHA input on the AD7890 is connected directly to the input stage of the track/hold amplifier. This is a high impedance input with an input leakage current of less than 50nA. Connect the mux output pins directly to the SHA input pins and the multiplexer output directly to the track/hold amp. The input voltage range for this input is 0 V to +2.5 V. If an external circuit is connected between the MUX output and the SHA input, the user must ensure that the SHA input has an input voltage range of 0 V to +2.5 V to ensure that the full dynamic range of the converter is used.

The track/hold amplifier on the AD7890 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. When the ADC is at its maximum throughput of 117 kHz (ie, the track/hold can handle input frequencies in excess of 58 kHz), the input bandwidth of the track/hold is greater than the ADC's Nyquist rate.

The track/hold amplifier obtains a 12-bit precision input signal in less than 2 microseconds. The operation of tracking/holding is basically transparent to the user. At the beginning of a conversion, the track/hold amplifier goes from its track mode to its hold mode.

The start of a conversion is the start of the rising edge of convst for hardware conversions (assuming the internal pulse has timed out), and for software conversions, the start is the point at which the internal pulse times out. The aperture time for track/hold (ie, the delay time between the external convst signal and the actual track/hold entering the hold) is typically 15ns. For software conversion start, the time depends on the internal pulse width. Therefore, the definition of the sampling instant is not well defined for the start of a software conversion. For sampling systems that require well-defined equidistant sampling, starting with a software transformation may not get the best performance from the part. At the end of the conversion, the part returns to its tracking mode. The acquisition time of the track/hold amplifier starts at this point.

Reference chapter

The AD7890 includes a single reference pin, labeled REF OUT/REF IN, which provides access to the part's own +2.5 V reference voltage, and can also be connected to an external +2.5 V reference to provide a reference voltage source for the part. This part is specified as a +2.5 V reference. Errors in the reference source will cause gain errors in the AD7890 transfer function and will add to the full-scale errors specified on the part. On the AD7893-10, it will also cause offset errors to be injected in the attenuator stage.

The AD7890 includes an on-chip +2.5V reference. Use this reference as a reference source for the AD7890, simply - connect a 0.1µF disk ceramic capacitor from the REF OUT/REF IN pins to AGND. The voltage appearing on this pin is buffered internally before being applied to the ADC. If this reference needs to be used outside the AD7890, it should be buffered

Because the source impedance of this output is 2 kΩ nominal. At 25°C, the internal reference tolerance is ±10 mV, the typical temperature coefficient is 25 ppm/°C, and the maximum error is ±25 mV.

If the application requires a reference with tighter tolerances or if the AD7890 needs to be used with a system reference, the user has the option to connect an external reference to this REFOUT/REFIN pin. The external reference will effectively drive the internal reference, thus providing the reference source for the ADC. The reference input is buffered, but has a nominal 2 kΩ resistor connected to the AD7890's internal reference. Suitable reference sources for the AD7890 include the AD680, AD780, and the REF-43 precision +2.5V reference.

Timing and Control Section

The AD7890 has two interface modes, selected by the SMODE input. The first is self-clocked mode, where the part provides frame synchronization, serial clock, and serial data at the end of the conversion. In this mode, the serial clock rate is determined by the part's master clock rate (the rate of the clock in the input). The second mode is the external clock mode, where the user provides frame synchronization and serial clock signals to obtain serial data from the part. In this second mode, the user has control of the serial clock rate up to 10 MHz. Both modes are discussed in more detail in the Serial Interface section.

This section also provides hardware and software transition startup features. The former provides a well-defined sampling instant to track/hold on the converted signal. For software conversion initiation, a write to the conv bit of the control register will initiate the conversion sequence. However, for software conversion initiation, the internal pulse must time out before the input signal is sampled. This pulse, combined with the difficulty of maintaining an exact equal delay between each software conversion start command, means that the dynamic performance of the ad7890 may struggle to meet specifications when used in software conversion start mode.

The AD7890 provides individual channel selection and conversion start control. This allows the user to optimize the throughput of the system. Once the track/hold enters hold mode, the input channel can be updated while the current conversion is in progress and the input voltage can settle to the new value.

Assuming the internal pulse has timed out before the convst pulse is executed, the conversion will consist of 14.5 master clock cycles. In automatic timing mode, the conversion time is defined as the time from the rising edge of the const-rfs to the falling edge (i.e. when the device starts transmitting its conversion result). This time includes 14.5 master clock cycles plus the update of the output registers and the delay time I/O to place the RFS signal, resulting in a total conversion time of 5.9 μs maximum. Figure 4 shows the conversion timing hardware conversion when the AD890 is used in self-clocked (master) mode. The timing diagram assumes that the internal pulse is not active when the convst signal goes high. To ensure this, the channel address to be translated should be on the translation pulse. Sufficient setup time should be allowed between the control register write and convst to ensure that the internal pulse has timed out. The duration of the internal pulse (and therefore the duration of the setup time) depends on the value of cExt.

When using the device in external clock mode, the output registers can be read at any time and the latest conversion results are available. However, reading data from output registers or writing data to control registers - during a conversion or 500 ns before the next conversion will result in reduced part performance. The recited opera - the output registers have the greatest impact on performance, especially when using higher serial clock rates, the signal-to-noise ratio may decrease and the code flicker from the part may increase (see AD7890 Performance section).

Figure 5 shows the timing and control sequence required to obtain optimum performance from the part in external timing mode. In the sequence shown, the conversion begins on the rising edge of convst, and new data is available later in the AD7890's output register for 5.9 microseconds. Once a read operation has taken place, an additional 500 ns should be allowed before the next rising edge of convst to optimize the track/hold settings before starting the next conversion. The figure shows read and write operations in parallel. The internal pulse of the sixth falling edge of sclk in the write sequence will be initiated. Assuming mux out is connected to sha in, it takes 2 microseconds between the sixth fall - the edge of SCLK and the rising edge of CONVST to allow the full acquisition time of the track/hold amplifier. At serial clock rates up to 10 MHz, the achievable throughput rate for this part is 5.9 seconds (conversion time) plus 0.6 Mbytes (six serial clock pulses before the internal pulse starts) plus 2 seconds (capture time) time). This results in a minimum throughput time of 8.5 microseconds (equivalent to a throughput rate of 117 kHz). If the part operates with a slower serial clock, it will affect the achievable throughput for optimal performance.

In auto-clock mode, the AD7890 indicates when a transition-SION is complete by lowering the RFS line and initiating a serial data transfer. In external clock mode, there is no indication of when the conversion is complete. In many applications this will not be a problem as data can be read from the part during or after the conversion. However, applications that want to get the best performance from the ad7890 must make sure to do so during transitions or at Const. This can be achieved in two ways. The first is to ensure in software that the read operation does not start until 5.9 microseconds after the rising edge of convst. This can only be done if the software knows when to issue the convst command. The second scheme is to use the convst signal as the conversion start signal and interrupt signal. The easiest way is to generate a square wave signal for the convst with high and low powers of 5.9 microseconds. Conversions are initiated on the rising edge of convst. The falling edge of convst occurs after 5.9 microseconds and can be used as an active low or falling edge triggered interrupt to tell the processor to read data from the AD7890. If the read operation completes 500 ns before RIS - on the edge of the convst, the ad7890 will work according to spec.

This scheme limits throughput to a minimum of 11.8 microseconds. However, based on the microprocessor's response time to the interrupt signal and the time it takes the processor to read the data, this may be the fastest the system can achieve after surgery. Anyway, the convst signal doesn't have to have a 50:50 duty cycle. This can be tailored to optimize component throughput for a given system. Alternatively, the convst signal can be used as the normal nar-line pulse width. The rising edge of convst can be used as an active high or rising edge triggered interrupt. Then, a software delay of 5.9 microseconds can be achieved before reading data from the part.

CEXT function

The c ext input on the AD7890 provides a way to determine how long after the new channel address has been written to the part where the translation can take place. There are two reasons behind this. First, when the input channel to the AD7890 is changed, the input voltage on this new channel may be very different from the previous channel voltage. Therefore, the tracking/holding of the part must acquire the new voltage before an accurate conversion can be made. The internal pulse delays any conversion start commands (and signals track/hold to hold) until the pulse times out. The second reason is to allow the user to connect external antialiasing or signal conditioning circuits between mux out and sha in. This external circuit will bring additional settling time to the system. The CEXT pin provides the user with a way to extend the internal pulse to account for this extra settling time. Basically, changing the value of the capacitor on the cext pin changes the duration of the internal pulse. Figure 7 shows the relationship between the value of the CEXT capacitor and the internal delay.

The duration of the internal pulse can be seen on the CEXT pin. When a serial write to the part starts (on the falling edge of TFS). In a serial write operation, it begins to discharge on the sixth falling edge of SCLK. Once the CEXT pin discharges beyond its nominal trigger point of 2.5V, the internal pulse times out.

Each time a control register is written, an internal pulse is initiated. As a result, for all software conversion start commands, the pulse is initiated and the conversion process is delayed. For hardware conversion start, the conversion start command can be separated from the internal pulse.

If the multiplexer output (mux out) is directly connected to the track/hold input (sha in), the internal pulse width does not have to take into account the external settings. In applications where the multiplexer is switched and the conversion does not start until more than 2 microseconds after the channel change (which may be the case at the start of a hardware conversion), the user does not have to worry about connecting any capacitors to the cext pins. 2µs is equal to the track/hold capture time of the ad7890. In applications where the multiplexer is switched and conversions are initiated at the same time (such as when software conversions are initiated), a 120 pF capacitor should be connected to cext to allow for track/hold acquisition time before conversions are initiated.

If an external circuit is connected between mux out and sha in, the extra settling time introduced by this circuit must be considered. In the case where the multiplexer change command and the conversion start command are separated, if the user does not have to worry about cext capaci, they need to be separated with an acquisition time greater than the AD7890 plus the settling time of the external circuit -

and many more. During multiplexer switching and simultaneous initiation of conversions (eg, software conversion initiation), the capacitors on CEXT are required to allow for the acquisition time of the track/hold plus the settling time of the external circuit before initiation of the conversion.

serial interface

The serial communication port of the AD7890 provides a flexible means of easily interfacing with industry standard microprocessors, microcontrollers and digital signal processors. Serial reads to the AD7890 access data from the output registers via the data out lines. Serial writes to the AD7890 write data to the control register via data concatenation.

There are two different modes of operation, optimized for different types of interfaces, where the AD7890 can act as either a master in the system (it provides serial clock and data frame signals) or as a slave (it can provide external serial signals to the AD7890). line clock and frame signals). These two modes, labeled Self-Clocked and Externally Clocked, are discussed in detail below.

Automatic timekeeping mode

The AD7890 configures its self-clocked mode by connecting the smode pin of the device to a logic low level. In this mode, the ad7890 provides the serial clock signal and serial data frame signal used to transfer data from the ad7890. This self-clocked mode can be used with processors that allow external devices to clock their serial ports, including most digital signal processors.

read operation

Figure 8 shows the timing diagram for reading the AD7890 in automatic timing mode. At the end of the conversion, RFs goes low and the serial clock (sclk) and serial data (data out) outputs become active. Sixteen bits of data are transferred with a leading zero, followed by the three address bits of the control register, followed by a 12-bit conversion result starting at msb. Serial data is clocked from the device on the rising edge of SCLK and is valid on the falling edge of SCLK. The rfs output remains low cycled during 16 clocks. On the sixteenth rising edge of SCLK, the RFS output is driven high and the data output is disabled.

write operation

Figure 9 shows the year 7890 AD. Set the tfs input low to indicate an impending serial write. A low tfs enables the SCLK output, which is used to clock data out of the processor serial port and into the control registers of the AD7890. The AD7890 control register requires only 5 bits of data. They are loaded on the first five clock cycles of the serial clock, ignoring data on all subsequent clock cycles. However, this part requires six serial clock cycles to load the data into the control registers. Serial data to be written to the AD7890 must be valid on the falling edge of SCLK.

external clock mode

The AD7890 configures its external clock mode by connecting the device's smoke pin to a logic high. In this mode, the SCLK and RFS of the AD7890 are configured as inputs. This external clock mode is designed for direct connection to systems that provide a serial clock output that is synchronized with the serial data output including microcontrollers such as the 80C51, 87C51, 68HC11 and 68HC05 and most digital signal processor.

read operation

Figure 10 shows the slave AD7890 in external clock mode. RFS is low enough to access data from the AD7890. The serial clock input does not have to be continuous. Serial data can come through bytes. However, rfs must be kept low during data transfer operations. Again, the 16-bit data is sent with a leading zero, followed by the 3 address bits in the control register, followed by the 12-bit conversion result starting with msb. If RFS goes low for the SCLK time at the high point, the leading zero RFS edge is clocked from the fall (as shown in Figure 10). If RFS goes low during the low time of SCLK, a leading zero is clocked on the next rising edge of SCLK. This ensures that leading zeros are valid on the first falling edge of sclk after rfs goes low regardless of whether rfs goes low during sclk's high or low time, as long as t14 and t17 are respected. Serial data is clocked from the device on the rising edge of SCLK and is valid on the falling edge of SCLK. At the end of the read operation, the data output line is input by SCLK or RFS, whichever occurs first. If a serial read from the output register is in progress when the conversion is complete, the update of the output register is deferred until the serial data read is complete and RFS returns high.

write operation

Figure 11 shows the year 7890 AD. As in self-timed mode, the tfs input goes low to indicate that the part of the serial write is about to take place. As before, the AD7890 control register requires only 5 bits of data. They are loaded on the first five clock cycles of the serial clock, ignoring data on all subsequent clock cycles. However, this part requires six serial clocks to load the data into the control registers. Serial data to be written to the AD7890 must be valid on the falling edge of SCLK.

Simplified interface

To minimize the number of interconnect lines to the AD7890, the user can connect the RFS and TFS lines of the AD7890 together while reading and writing from the part. In this case, the new control register data should be provided on the data input line, the input channel should be selected and a conversion start command may be provided, while the part should provide the result of the just completed conversion on the data output line.

In self-clocked mode, this means that the part provides all signals for the serial interface. It does require when the part brings the TFS line low. In external clock mode, this means that the user only needs to provide a single-frame sync signal to control read and write operations.

If the user wants the best performance from the part, he must take care to complete the read operation before the next conversion begins. In the case of a software conversion start, the conversion command is written to the control register on the sixth serial clock edge. However, the read operation continues for 10 serial clock cycles. To avoid reading at sampling instants or during conversions, the user should ensure that the internal pulse width is long enough (by selecting cext) to complete the read operation before the next conversion sequence begins. Otherwise, the performance of the part will be significantly degraded, both in terms of signal-to-noise ratio and DC parameters. With the hardware conversion started, the user should ensure that the delay convst between the sixth falling edge and the next rising edge of the serial clock in a write operation is greater than the internal pulse width.

Microprocessor/Microcontroller Interface

The flexible serial interface of the AD7890 allows easy connection to the serial ports of DSP processors and microcontrollers. Figures 12 through 15 show the AD7890 interfacing with many different microcontrollers and digital signal processors. In some of the interfaces shown, the AD7890 is configured as the master in the system, providing the serial clock and frame synchronization for read operations, while in others it acts as a slave to the microprocessor providing these signals.

AD7890–8051 interface

Figure 12 shows the interface between the AD7890 and the 8XC51 microcontroller. The AD7890 is configured in its external clock mode, while the 8XC51 is configured in its Mode 0 serial interface mode. The graph shown in Figure 12 does not specify monitoring when a conversion is completed on the AD7890 (assuming a hardware conversion start is used). Monitoring conversion times on the ad7890 As mentioned earlier, convst can be used. This may be achieved in two ways. One is to connect the convst line to another parallel port bit that is configured as an input. This port bit can then be polled to determine when the conversion is complete. Another way is that in this case the convst line should be connected to the int1 input of the 8xc51.

Since the 8XC51 contains only one serial data line, the data output line and data input line of the AD7890 must be connected together. This means that the 8XC51 cannot communicate with the AD7890's output registers and control registers at the same time. The 8XC51 outputs the LSB first in a write operation, so care should be taken when arranging the data to be sent to the AD7890. Similarly, during a read operation, the AD7890 outputs msb first, while the 8xC51 requires lsb. Therefore, the data to be read into the serial port needs to be rearranged before the correct data word from the ad7890 is provided in the microcontroller.

The serial clock frequency from the 8XC51 is limited to significantly lower than the allowable input serial clock frequency at which the AD7890 can operate. Therefore, the time to read data from the component is actually longer than the transition time of the component. This means that the AD7890 cannot operate at its maximum throughput when used with the 8xC51.

AD7890–68HC11 interface

The interface circuit between the AD7890 and the 68HC11 microcontroller is shown in Figure 13. For the interface shown, the AD7890 is configured in its external clock mode, while the SPI port of the 68HC11 is used and the 68HC11 is configured in its microcontroller mode. The 68HC11 is configured in master mode with its cpol bit set to logic zero and its cpha bit set to logic one.

As with the previous interface, there is no provision for monitoring when the conversion is done on the AD7890. Monitoring the conversion time of the AD7890A scheme, as in the previous interface with convst, can be used. This can is implemented in two ways. One is to connect the convst line to another parallel port bit that is configured as an input. This port bit can then be polled to determine when the conversion is complete. Another way is to use an interrupt driven system in which case the convst line should be connected to the IRQ input of the 68HC11.

The serial clock frequency of the 68HC11 is limited to significantly lower than the allowable input serial clock frequency at which the AD7890 can operate. Therefore, the time to read data from the component is actually longer than the transition time of the component. This means that the AD7890 cannot run at its maximum throughput when used with the 68 HC11.

AD7890–ADSP-2101 interface

The interface circuit between AD7890 and ADSP-2101 digital signal processor is shown in Figure 14. The ad7890 is configured in its external clock mode, and the adsp-2101 provides the serial clock and frame synchronization signals. The rfs1 and tfs1 inputs are outputs configured to run low.

In the scheme shown, the maximum serial clock frequency that the ADSP-2101 can provide is 6.25 MHz. This allows the AD7890 to operate at a sampling rate of 111 kHz. If the AD7890 is desired to operate at a maximum throughput rate of 117 kHz, an external serial clock of 10 MHz can be provided to drive the serial clock input of the AD7890 and ADSP-2101.

In order to monitor the conversion time on the AD7890, the scheme as described in the previous interface of convst can be used. This can be achieved by connecting the convst line directly to the IRQ2 input of the ADSP-2101. Alternatives so that users don't have to worry about surveillance

The conversion state is to operate the AD7890 in its automatic clock mode. In this scheme, the actual interface connections will remain as shown in Figure 14, but now the AD7890 provides the serial clock and receives the frame sync signal - nars. Using the AD7890 in automatic timing mode limits the throughput of the system as the serial clock rate is limited to 2.5mhz.

AD7890–DSP56000 interface

Figure 15 shows the interface circuit between the AD7890 and the DSP56000 DSP processor. The AD7890 is configured in its external clock mode. The DSP56000 is configured in normal mode, running synchronously with a continuous clock. It is also set to a 16-bit word, with sck and sc2 as output. The FSL bit of the DSP56000 should be set to 0.

The RFS and TFS inputs of the AD7890 are connected together so that data is transferred to and from the AD7890 at the same time. When the DSP56000 is in sync mode, it provides a common frame sync pulse for read and write operations on its SC2 output. It is applied to the RFS and TFS inputs of the AD7890.

In order to monitor conversion times on the AD7890, a scheme (as described in the previous convst interface example) can be used. This can be achieved by connecting the convst directly to the IRQA input of the DSP56000.

AD7890–tms320c25/30 interface

Figure 16 shows the interface circuit between the AD7890 and the tms320c25/30dsp processor. The AD7890 is configured in its self-clocked mode, in which it provides the serial clock and frame synchronization signals. However, the tms320c25/30 requires a continuous serial clock. In the scheme outlined here, the AD7890's master clock signal clk in is used to provide the serial clock to the processor. The output SCLK (serial data reference) of the AD7890 is a delayed version of the CLK input signal. The typical delay between the CLK input and SCLK is 20 ns, with a delay of less than 50 ns over power and temperature. So there will still be enough setup time to clock the data output into the DSP on the edge of the clk-in signal. When writing data to the AD7890, the processor holds the data long enough for two clocks. The RFS signal of the AD7890 is connected to the FSX and FSR inputs of the processor. The processor can generate its own fsx signal, so the interface can be modified if needed - so that the rfs and tfs signals are separated, the processor generates the fsx signal, and the fsx signal is connected to the TFS input of the AD7890.

In the scenario outlined here, the user does not have to worry about monitoring the end of the transition. Once the conversion is complete, the AD7890 is responsible for passing its conversion result back to the processor. Once the processor receives the 16-bit data into the serial shift register, it generates an internal interrupt. Since the rfs and tfs are connected together, whenever the ad7890 sends its conversion result, the data is sent to the control register of the ad7890. The user only needs to ensure that the word to be written to the AD7890 control register is set before the end of the conversion. As part of an interrupt routine that recognizes that data has been read in, the processor can set the data to be written to the control register next.

antialiasing filter

The AD7890 provides separate access to the multiplexer and ADC through the MUX output and SHA input pins. One of the reasons for this is to allow the user to implement an antialiasing filter between the multiplexer and the ADC. The advantage of inserting an anti-aliasing filter at this point is that if one were to be placed before the multiplexer, one anti-aliasing filter would satisfy all eight channels, rather than setting it individually for each channel An antialiasing filter.

The antialiasing filter inserted between the mux out and sha in pins is usually a low pass filter to remove high frequency signals that may be aliased back into band during sampling. It is recommended that this filter be an active filter, ideally, the high impedance stage is driven by the mux output from the AD7890 and the sha-in of the section is driven by the low impedance stage. This will remove any effect of the component multiplexer on the voltage resistance variation of the input signal, and will also remove any effect of the high source impedance at the track/hold sample input. When an external antialiasing filter is in place, the additional settling time associated with the filter should be calculated by using a larger capacitor on CEXT.

AD7890 performance linearity

The linearity of the AD7890 is mainly determined by the on-chip 12-bit D/A converter. This is a segmented DAC laser trimmed for 12-bit integral linear and differential linear. Typical relative numbers for parts are ±1/4 LSB, while typical DNL errors are ±1/2 LSB.

noise

In an a/d converter, noise appears as code uncertainty in DC applications and as a noise floor in fft.

in communication applications. In a sampling A/D converter like the AD7890, from DC to 1/2 the sampling frequency, all information about the analog input appears in baseband. The input bandwidth of track/hold exceeds the Nyquist bandwidth, so in applications where such a signal is present, an antialiasing filter should be used to remove unwanted signals above FS/2 in the input signal.

Figure 17 shows a histogram of 8192 DC input conversions using the AD7890. The analog input is set at the center of the transcoding. The timing and control sequence used is shown in Figure 5, where the performance of the ADC is maximized. The same performance will be achieved in automatic clock mode, in which the part transfers its data after the conversion is complete. As can be seen, almost all the codes appear in one output bin, which shows that the ADC has very good noise performance. The rms noise performance of the AD7890-2 in the figure above is 81µV. Since the analog input range and LSB size on the AD7893-4 is 1.638 times that of the AD7893-2, the same output code distribution results in an output rms noise of 143 μV for the AD7893-4. For the AD7890-10 with 8 times the lsb size of the AD7890-2, the code distribution represents 648 µV of output rms noise.

In external clock mode, data can be written to the control register or read from the output register during a conversion. The data shown in Figure 18 is the same as the data shown in Figure 17, except in this case, the output data read for the device occurs during the conversion. These results were achieved with a serial clock frequency of 2.5MHz. If a higher serial clock rate is used, the transcoding noise will be reduced from that shown in the graph of Figure 18. This injects noise into the die when making bit decisions, increasing the noise produced by the AD7890. The histogram of 8192 conversions of the same DC input now shows a larger spread of the code as the rms noise of the AD7890-2 increases to 170 microvolts. This effect will vary depending on where the serial clock edge occurs in the bit trial of the conversion process. Depending on the relationship of the serial clock edge to the bit trial point (i.e. the serial clock edge to the clk in edge), the same level of performance can be achieved when reading during conversion as when reading after conversion. During the conversion process, the bit decision point on the AD7890 is on the falling edge of the master clock (CLK IN). From a noise perspective, recording new data bits at these points (ie the rising edge of sclk) is the most critical. The most critical bit decision is msbs, so to achieve the performance levels shown in Figure 18, reads within 1 microsecond of the rising edge of convst should be avoided.

Writing data to the control registers also introduces digital activity on the part during the conversion process. However, since there is no active output driver during a write operation, the amount of current flowing on the die is less than that of a read operation. Therefore, the amount of noise injected into the mold is smaller than that of the read operation. Figure 19 shows the effect of a write operation during a transition. The histogram of 8192 transitions of the same dc input now shows a larger spread than the code under ideal conditions, but less spread than a read operation. The rms noise generated by the AD7890-2 is 110µV. In this case, the serial clock frequency is 10 MHz.

Dynamic performance

The AD7890 includes an on-chip track/hold that allows the part to sample input signals up to 50 kHz on any of its input channels. Many applications of the AD7890 only require it to sequence low frequency input signals through eight channels. However, for some applications, the dynamic performance of the converter output to the 40kHz input frequency is of concern. For these broadband sampling applications, it is recommended to use the hardware conversion initiation method for the reasons outlined earlier.

These applications require information about the effect of the ADC on the spectral content of the input signal. Signal-to-noise ratio (noise + distortion), total harmonic distortion, peak harmonics or spurs, and intermodulation distortion are specified. Figure 20 shows an FFT plot of a typical 10 kHz, 0 V to +2.5 V input, after digitization by the AD7890-2 at a sample rate of 102.4 kHz. The signal pair (noise + distortion) is 71.5dB and the total harmonic distortion is -85dB. It should be noted that reading data from the part during 10 MHz serial clock transitions has a significant impact on dynamic performance. Therefore, for sampling applications, it is recommended not to read data during conversion.

significant digits

The formula for signal-to-noise ratio (noise + distortion) (see the Terminology section) is related to the resolution or number of bits of the converter. The following formula is rewritten to give a measure of performance in significant bits (n): n = (SNR-1.76)/6.02, where snr is the signal-to-noise ratio.

The effective number of bits of a device can be calculated from the ratio of its measured signal to (noise + distortion). Figure 21 shows a typical plot of effective bits versus frequency for the AD7890-2 from DC to 40kHz. The sampling frequency is 102.4khz. The graph shows that the ad7890 converts a 40 kHz input sine wave to an effective number of digits of 11, which is equivalent to converting the signal to a (noise + distortion) level of 68 dB.