General Instructions
The W83194R- 39/-39A is a clock synthesizer that provides all the clocks required for high-speed RISC or CISC microprocessors such as the Intel Pentium II. The W83194R-39 provides eight different frequencies of CPU and PCI clocks and the W83194R-39A provides 16 CPU/PCI frequencies, which are externally selectable for smooth transition. The W83194R-39/-39A also provides 13 SDRAM clocks by a no-delay buffer in the pin.
The w83194r-39/-39a accepts a 14.318mhz reference crystal as input and runs at 3.3v.
supply. Spread spectrum is built in at -0.5% or -0.25% to reduce EMI. Programmable parking via I2C interface for single clock output and frequency selection. The device is compliant with Pentium Power Stability, which requires the CPU and PCI clock to power on steadily within 2ms. Dual function pins are not recommended for sockets (isa, pci, cpu, dim). This add-on card can be pulled up or down.
High-drive 6 PCI and 13 SDRAM clock outputs typically provide greater than 1V/ns transition loading of 30 pf. The two cpu clock outputs typically provide better than 1v/ns slew rate into a 20 power factor load maintaining a 50-5% duty cycle. The fixed frequency output provides better than 0.5V/ns slew rates for REF, 24MHz, and 48MHz.

Product Features · Supports Pentium II CPU with I2C.
2 CPU clocks (one idle running CPU clock)
13 3D SDRAM clocks 6 PCI synchronous clocks One IOAPIC clock for multiprocessor support Optional single or mixed supply: (vddq1=vddq2=vddq3=vddq4=vddl1=vddl2=3.3v) or (vddq1= vddq2=vddq3=vddq4)=3.3V, VDDL1=VDQL2=2.5V)
Skew between CPU and SDRAM clocks < 250ps
Skew between PCI clocks < 250ps
Propagation delay of buffer input is less than 5ns sdram
· Offset from CPU (early) to PCI clock -1 to 4ns, centered at 2.6ns.
Smooth frequency switch, selectable from 50MHz to 133MHz CPU

-0.25% or -0.5% spread spectrum function to reduce EMI
2ms power-up clock stabilization time Power management mode pins One 48MHz for USB and one 24MHz for Super I/O

Pin configuration

Functional Description Power Management Functions All clocks can be individually enabled or disabled through a 2-wire control interface. At power-up, the external circuitry should allow the VCO to settle for 3 ms before enabling the clock output to ensure the correct pulse width. When mode=0, pins 15 and 46 are input terminals (pci_stop), (cpu_stop), when mode=1, these functions are not available. A specific clock can be enabled because both the 2-wire serial control interface and one of the pins indicate that it should be enabled.
According to the table below, the W83194R-39/-39A can be disabled in the low state to reduce power consumption. All clocks are stopped in the low state, but remain active high periods during the transition from run to stop. The CPU and PCI clocks transition between running and stopping by waiting for a positive edge on PCICLK_f, then waiting for a negative edge on the clock of interest, then enabling or disabling the high-level output.

The wire I2C control interface clock generator is a slave i2c component that can read the data stored in the latch for verification. All in-progress bytes must be sent to change one of the control bytes. A 2-wire control interface allows each clock output to be individually enabled or disabled. At power-up, the W83194R-39/-39A initializes with default register settings and then optionally uses a 2-wire control interface.
The sdata signal only changes when the sdclk signal is low and is stable when the sdclk signal is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on sdata, and sdclk is a high used to indicate the start of a data transfer cycle. The other is a low-to-high transition on sdata while sdclk is high to indicate the end of a data transfer cycle. Data is always sent as full 8-bit bytes, and then an acknowledgment is generated.
A byte write begins with a start condition, followed by a 7-bit slave address and write command bits [1101 0010], command code check [0000 0000], and byte count check. After each byte is successfully received, the clock chip will generate an acknowledge (low) on the sdata line. The controller can start writing to the internal I2C registers after the data string.

Serial Control Register
The pin column lists the affected pin numbers, and the @power up column gives the default state when it is actually powered up. "instruction code "byte" and "byte count" bytes MUST be sent after the address byte is acknowledged. Although the data (bits) in these two bytes are considered "don't care", they MUST be sent and will be acknowledged. After that, the sequence described below (register 0, register 1, register 2, ...) will be valid and acknowledged.

PCI stop time graph

For synchronous chipsets, pci_stop_pin is an asynchronous active low input pin used to stop pciclk[0:4] during low power operation. This pin is asserted synchronously on the rising edge of the free-running PCI clock (pciclk_f) by external control logic. When the PCI clock is stopped, all other clocks will continue to run. The PCI clock will always stop in the low state and resume the output with full pulse width. In this case, the PCI clock on latency is less than 2 PCI clocks and the clock off latency is less than 2 PCI clocks.
Operation pins 2, 7, 8, 25 and 26 of the dual function pins are dual function pins used to select different functions in this device (see pin description). During power-up, these pins are in input mode (see Figure 1) and are therefore considered input select pins. When VDD reaches 2.5V, the logic levels on these pins are latched into the corresponding internal registers. Once the correct information is properly latched, these pins become output pins and are pulled low by default. At the end of the power-up timer (within 3 ms), the output starts toggling at the specified frequency.
There is a large pull-up resistor (250 kΩ@3.3V) inside each pin. The default state is logic 1, but when there are long traces or heavy loads on these dual function pins, the internal pull-up resistors may be too large. Under these conditions, if a logic 1 is required, it is recommended to connect an external 10 kΩ resistor to VDD. Otherwise, if a logic 0 is required, go directly to ground. The 10 kΩ resistor should be placed before the heavily terminated resistor. Note that these logics will only be locked on initial power up.
If an optional EMI reduction capacitor is required, it should be placed as close as possible to and after the series termination resistor. Typical values for these capacitors are between 4.7pF and 22pF.