feature

40-channel DAC in 13 mm × 13 mm 108 -lead CSPBGA; guaranteed monotonic to 14 bits; buffered voltage output; output voltage span 3.5V × VREF(+); maximum output voltage span 17.5 volts; system calibration function allows user programming; bias shift and gain; pseudo-differential output relative to refgnd; clear function to user-defined refgnd (clr pin); DAC output synchronous update (LDAC pin); DAC increment/decrement modes; channel grouping and addressing functions; interface options: Parallel interface compatible with 3-wire serial interface for DSP/microcontroller; 2.5V to 5.5V jedec compliant digital level SDO daisy chain option; power-on reset; digital reset (reset pin and soft reset function).

application

Level settings in automatic test equipment (ATE); variable optical attenuators (VOAs); optical switches; industrial control systems.

General Instructions

The AD5379 contains 40 14-bit DACs in one CSPBGA package. The AD5379 provides a bipolar output range determined by the voltages applied to the V+ and V (negative) inputs. The maximum output voltage span is 17.5 V, which corresponds to a bipolar output range of 8.75 V to +8.75 V, and is achieved with reference voltages of V(=) = 3.5 V and V(+) = +5 V.

The AD5379 provides guaranteed operation over a wide V/V supply range of ±11.4 V to ±16.5 V. The headroom requirement for the output amplifier is 2.5 V with a working load current of 1.5 mA, and 2 V with a working load current of 0.5 mA.

The AD5379 contains a double-buffered parallel interface with 14 data bits loaded into an input register Table 1. High channel count, low voltage single supply DAC. a0 to a7 under the control of the wr, cs and dac channel addresses. It also has a 3-wire serial interface, with the spi? , qspi? , microwire? Compatible with dsp interface standards and can handle clock speeds up to 50mhz. The dac output is updated when new data in the dac register is received. All outputs can be updated simultaneously by lowering the ldac input. Each channel has programmable gain and offset adjustment registers. Each dac output is taken and buffered on-chip relative to the external refgnd input. The DAC output can also be switched to REFGND via the CLR pin.

the term

Relative accuracy

Relative accuracy or endpoint linearity is a measure of the maximum deviation of a straight line through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in least significant bits (lsb).

Differential nonlinearity

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum guarantees monotonicity.

Zero scale error

Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register.

Ideally, all 0s are loaded into the DAC, M is 1, and C is 10 0000 0000 0000:

Zero-scale error is the difference between VOUT (actual) and VOUT (ideal) measured in mV. The zero-scale error is mainly caused by the offset of the output amplifier.

full scale error

Full-scale error is the error in the dac output voltage when all 1s are loaded into the dac register.

Ideally, load all 1s to the DAC, M is all 1s, and C is 10 0000 0000 0000:

Full-scale error is measured as the difference between VOUT (actual) and VOUT (ideal) in mV. Zero-scale error is not included.

gain error

Gain error is the difference between full-scale error and zero-scale error, expressed in mV.

Temperature Coefficient

This includes output error contributions from linearity, offset and gain drift.

DC output impedance

The DC output impedance is the effective output source resistance, which is dominated by the package lead resistance.

DC crosstalk

The 40 DAC outputs are buffered by op amps that share the V and V supplies. If the DC load current in one channel changes (due to updates), this can lead to further DC changes in the output of one or more channels. This effect is more pronounced at high load currents and decreases as the load current decreases. For high impedance loads, this effect is practically unmeasurable. Multiple V and V terminals are provided to minimize DC crosstalk.

Output voltage settling time

This is the time required for the output of the DAC to settle to the specified level for a full-scale input change.

Digital-to-analog fault energy

This is the energy injected into the analog output during major code transitions. It is designated as a failure area in NV-S. Measured by toggling the DAC register data between 0x1FF and 0x2000.

Isolation between channels

Channel-to-channel isolation refers to the ratio of the input signal from one DAC's reference input that appears at the output of another DAC operating from another reference. Expressed in decibels, measured at the mid-scale.

DAC-to-DAC crosstalk

dac-to-dac crosstalk is a glitch pulse in the output of one converter due to a digital change and subsequent analog output change of another converter. Specified in NV-S.

digital crosstalk

A glitch pulse transmitted to the output of one converter due to a change in the DAC register code of the other converter is defined as digital crosstalk and specified in nv-s.

digital feedthrough

When no device is selected, high frequency logic activity on the device's digital inputs can capacitively couple across and through the device to appear as noise on the vout pin. It can also be connected along the power and ground wires. This noise is digital feedthrough.

Output Noise Spectral Density

This is random noise generated inside the measurement.

Random noise is characterized by spectral density (voltage per √Hz). It is measured by loading all DACs to midscale and measuring the noise at the output. The unit of measurement is nv/(hz) 1/2.

Function description

DAC Architecture - Overview

The AD5379 contains 40 DAC channels and 40 output amplifiers in a single package. The structure of a single DAC channel consists of a 14-bit resistor string DAC and an output buffer amplifier. The resistor string part is just a string of resistors, each with a value of r, from v(+) to agnd. This structure guarantees the monotonicity of the DAC. The 14-bit binary digit code loaded into the dac register determines at which node on the string the voltage is tapped before the input to the output amplifier. The output amplifier converts the output of the DAC to a wider range. The DAC output is increased by a factor of 3.5 and is compensated by the voltage on the V(-) pin. See the "Transfer Functions" section.

channel group

The 40 DAC channels on the AD5379 are divided into 4 groups (A, B, C, D) of 10 channels each. In each group, eight channels are connected to v1++ and v1(-), and the remaining two channels are connected to v2++ and v2(-). Each group has two independent reference pins. For example, in group A, eight channels are connected to refgnda1 and the remaining two channels are connected to refgnda2. In addition to the input register (x1) and dac register (x2), each channel also has a gain register (m) and an offset register (c). See Table 17. The inclusion of these registers allows the user to calibrate for errors throughout the signal chain, including DAC errors.

Transfer Function

The digital input transfer function for each dac can be expressed as:

where: x2 is the data word loaded into the resistor string dac. (The default is 10 0000 0000 0000.) x1 is the 14-bit data word written to the DAC input register. (The default is 10 0000 0000 0000.)

m is the 13-bit gain factor. (The default is 1111111111111.) c is a 14-bit offset coefficient. (default is 10 0000 0000 0000) n is the DAC resolution. (n=14).

Figure 19 shows a single DAC channel and its associated registers. The power-on values for the M and C registers are full scale and 0x2000, respectively. The user can individually adjust the voltage range on each DAC channel by overriding the power-on values for m and c. The AD5379 has digital overflow and underflow detection circuitry to clamp the DAC output at full or zero scale when the values chosen for x1, m, and c cause x2 to be out of range.

The complete transfer function of the AD5379 can be expressed as:

where: x2 is the data word loaded into the resistor string dac.

VREF(+) is the voltage at the positive reference pin.

VREF(-) is the voltage at the negative reference pin.

Figure 20 shows the output amplifier stage for a single channel. vdac is the voltage output of the resistor string dac, the nominal range of vdac is 1 lsb to full scale.

V function bias

The AD5379 has an on-chip voltage generator that provides a bias voltage of 4.25 V (min). The V pin is provided for bypass and overdrive purposes only. It is not intended to be used as a supply or reference. If V(+) > 4.25 V, then V must be pulled externally to an equal or higher potential (eg 5 V). The external voltage source should be able to drive a current sink load of 50µA (typ).

Reference selection

The voltages applied to V+ and V(-) determine the output voltage range and range from VOUT0 to VOUT39. If the offset and gain characteristics are not used (M and C maintain their energized values), the required reference level can be calculated as follows:

If the offset and gain characteristics of the AD5379 are used, the desired output range is slightly different. The selected output range should take into account the offset and gain errors that need to be trimmed. Therefore, the selected output range should be larger than the actual required range.

The required reference level can be calculated as follows:

1. Determine the rated output range on VOUT.

2. Determine the maximum offset interval and maximum gain required for the full output signal range.

3. Calculate the new maximum output range on VOUT, including the expected maximum offset and gain error.

4. Select the desired new vout and vout, keep the new vout limit centered at the nominal value, and assume that refgnd is zero (or equal to agnd). Note that v and v must provide sufficient headroom. max min DDSS

5. Calculate the values of V(+) and V(-) as follows:

Also, when using reference values other than the recommended values (V(+=5 V and V(-)=-3.5 V), the expected offset error components vary as follows:

where VREF(-) is the new negative reference value. v(+) is the new positive reference value.

If this offset error is too large to calibrate, the negative reference can be adjusted to account for the situation using the following formula:

Reference selection example

Rated Output Range = 10V; (-2V to +8V);

offset error = ±100mV; gain error = ±3%; refgnd = AGN = 0V;

1), = ±3%; gain error; maximum positive gain error = +3%;

=> output range including gain error = 10 + 0.03(10) = 10.3V;

2)、=±100mV; offset error; maximum offset error range=2(100)mV=0.2V;

=> Output range includes gain error and offset error = 10.3+0.2=10.5V;

3) VREF(+) and VVREF(-) calculation:

Actual output range = 10.5 V, i.e. -2.25 V to +8.25 V (centered);

=>V+=(8.25+2.25)/3.5=3VREF;

V-=-2.25/2.5=-0.9VREF;

If the solution produces an inconvenient reference level, the user can take one of three approaches:

(1) Use a resistor divider to divide the convenient and higher reference level to the desired level.

(2) Select a convenient reference level above V+ or below V(-). Modify the gain and offset registers to shrink the reference numerically. In this way, the user can use almost any reference level that is convenient, but may degrade performance due to excessive compression of the transfer function.

(3) Use these two methods in combination.

calibration

The user can perform system calibration by overriding the default values in the M and C registers of any individual DAC channel as follows:

(1) Calculate the nominal offset and gain factor of the new output range (see previous example).

(2) Calculate new m and c values for each channel based on the specified offset and gain errors.

Calibration example

nominal offset factor = 0;

Nominal gain coefficient=10/10.5×8191=0.95238×8191=7801;

Example 1: Channel 0, Gain Error = 3%, Offset Error = 100 mV;

(1), gain error (3%) calibration: 7801×1.03=8035=>load the code "1 1111 0110 0011" into M register 0;

(2), offset error (100 mV) calibration: LSB size = 10.5/16384 = 641 microvolts;

Offset factor for 100 mV offset = 100/0.64 = 156 LSB => load "10 0000 1001 1100" into C register 0;

Example 2: Channel 1, Gain Error = -3%, Offset Error = -100mV;

(1), Gain error R (-3%) calibration: 7801×0.97=7567=>Load code "1110 1000 1111" into M register 1;

(2), offset error (-100 mV) calibration: LSB size = 10.5/16384 = 641 microvolts;

offset factor -100 mV offset = -100/0.64 = -156 LSB;

=> load "01 1111 0110 0100" into C register 1;

Clear function

The clear function on the AD5379 can be implemented in hardware or software.

hardware clear

Turning the CLR pin low switches the outputs VOUT0 to VOUT39 to externally set potentials on the REGND pin. This is achieved by switching and reconfiguring in refgnd.

The output amplifier enters unity-gain buffer mode, ensuring vout=refgnd. The contents of the input registers and DAC registers are not affected by a low CLR. When CLR is turned high, the DAC output remains cleared until LDAC is lowered. When CLR is low, the value of LDAC is ignored.

software clear

Loading the clear code into the x1 register also allows the user to set vout0 to vout39 to refgnd level. The default clear code corresponds to m at full scale and c at midscale (x2=x1).

Default clear code

=2×(——output offset)/(output range)14

=2×2.5×(agnd–-v(–))/(3.5×(v(–-agnd)) A more general expression for the clearing code is as follows:

Clear code=(2)/(M+1)×(default clear code-C)

Busy and LDAC functions

The value of x2 is calculated each time the user writes new data to the corresponding x1, c, or m register. Busy output goes low at Calcutta-x2. When busy is low, the user can continue to write new data to the x1, m or c registers, but no dac output updates. The DAC output is updated by turning the LDAC input low. If ldac goes low while busy, the ldac event is stored and the dac output is updated as soon as it goes high while busy. The user can also hold the ldac input permanently low. In this case, the dac output is updated as soon as busy goes high.

Each time any x1 register is written, the x2 value for a single channel or group of channels, the c register or the m register, is recalculated. While computing x2, busy goes low. The duration of this busy pulse depends on the number of channels being updated. For example, if x1, c, or m data is written to a dac channel, busy will go low by 550 ns (max). However, if data is written to both DAC channels, busy will drop by 700ns (max). Note that there is about a 200 ns overhead due to FIFO access.

The AD5379 includes an additional feature that is unless its X2 register is low since the last LDAC. Normally, when ldac goes low, the dac register is filled with the contents of the x2 register. However, the AD5379 only updates the DAC registers when the x2 data changes, thus eliminating unnecessary digital crosstalk.

FIFO and non-FIFO operation

There are two modes of operation available for loading data into the AD5379 registers: operation with FIFO disabled and operation with FIFO enabled. Disabling the fifo is optimal for a single write to the device. However, if the system requires a large amount of data to be transferred to the AD5379, it is more efficient to enable the FIFO.

When the FIFO is enabled, the AD5379 uses the internal FIFO memory to allow high-speed sequential writes in both serial and parallel modes. This optimizes interface speed and efficiency, minimizes overall conversion time due to internal digital efficiency, and minimizes the overhead of the host controller when managing data transfers. When an instruction in the state machine is executed, the busy signal goes low.

Table 10 compares the operation of enabling and disabling the FIFO for different data transfers of the AD5379. Fifo-enabled operations are more efficient for all but single write operations. When using fifo, the user can continue to write new data to the ad5379 while executing the write command. Up to 128 consecutive instructions can be written to the FIFO at maximum speed. When the fifo is full, additional writes to ad5379 are ignored.

Busy input function

Because the busy pin is bidirectional and open-drain (for proper operation, use a pull-up resistor to the digital supply), a second AD5379, or any other device (such as the system control-LER), can pull busy low, so , delay DAC update, if required. This is a means of delaying LDAC action. This feature allows simultaneous updates of multiple AD5399 devices in the system at maximum speed. All DACs are automatically updated once the last device connected to the busy pin is ready. Connecting the busy pins of multiple devices together allows all DACs to be updated synchronously without the need for additional hardware.

Power-on reset function

The AD5379 contains a power-on reset generator and state machine. During power-on, the CLR becomes active (internal), the power-on state machine resets all internal registers to their default values, and the busy state goes low. This sequence takes 8ms (typical). The outputs VOUT0 to VOUT39 are switched to externally set potentials on the REFGND pin. At power up, the parallel interface is disabled, so the part cannot be written to. To suppress initial ldac pin flicker, any transitions on ldac are ignored during power-up. A rising edge on busy indicates that power-up is complete and the parallel interface is enabled. All dacs remain in their powered state until the dac output is updated with ldac.

Reset input function

The AD5379 can be clocked at any time in the power-on reset state by activating the reset pin. The AD5379 state machine initiates a reset sequence that digitally resets the X1, M, C, and X2 registers to their default power-up values. This sequence takes 95 microseconds (typ), 120 microseconds (maximum), 70 microseconds (minimum). In the process, I was very busy. When reset is low, any transitions on the LDAC will be ignored. As with the CLR input, when RESET is low, the DAC output switches to REFGND. The output is held at refgnd until the ldac pulse is applied. This reset function can also be achieved through the parallel interface by setting the reg0 and reg1 pins low and writing all 1s to db13 to db0.

Increment/decrement function

The AD5379 has a special function register that allows the user to increment or decrement the internal 14-bit input register data (x1) in steps of 0 to 127 lsb. The increment/decrement function can be selected by setting the reg1 and reg0 pins (or bits) low. Address pins (or bits) a7 through a0 are used to select a DAC channel or channel group. The amount by which the x1 register is incremented or decremented is determined by the db6 to db0 bits/pins. For example, for a 1lsb increment or decrement, db6...db0=0000001; and for a 7lsb increment or decrement, db6...db0=0000111. db8 determines whether the input register data is incremented (db8=1) or decremented (db8=0). The maximum amount the user is allowed to increment or decrement data is 127 kilobytes, that is, 1111111. The 0 lsb steps are included to facilitate software looping in user applications.

The AD5379 features digital overflow and underflow detection circuitry that can clamp at full or zero scale when the value selected for increment or decrement mode is out of range.

interface

The AD5379 contains a parallel and serial interface. Active interface is selected by SE/PAR pin.

The AD5379 uses an internal FIFO memory that allows high-speed sequential writes in both serial and parallel modes. While writing instructions, the user can continue to write new data to the AD5379 - the operation is in progress. While executing the instruction in the fifo, the busy signal goes low. Up to 120 consecutive instructions can be written to the FIFO at top speed. When the fifo is full, additional writes to ad5379 are ignored.

To minimize device power consumption and on-chip digital noise, only when the device is being written, i.e. at wr or on the edge of a sync drop. All digital interfaces are compatible with 2.5V LVTTL when operating from a 2.7V to 3.6V supply.

Parallel interface

A pull-down on the SSE/PAR pin makes the parallel interface default. If a parallel interface is used, the SE/PAR pins can be left unconnected. Figure 6 shows the timing diagram for parallel writing to the AD5379. The parallel interface is controlled by the following pins.

CS pin

Active low device select pin.

wr pin

On the rising edge of wr, with cs low, the address value at pins a7 to a0 is latched and the data value at pins db13 to db0 is loaded into the selected AD5379 input register.

REG1, REG0 pins

The reg1 and reg0 pins determine the destination register for data written to the AD5379.

B13 to DB0 pins

The AD5379 accepts a direct 14-bit parallel word db13 on db0, where db13 is msb and db0 is lsb.

A7 to A0 pins

Each of the 40 DAC channels can be individually addressed. Additionally, multiple channel grouping allows users to write the same data to multiple DAC channels simultaneously. Address bits a7 through a4 are decoded to select one or more sets of registers. Address bits a3 to a0 select one of 10 input data registers (x1), offset registers (c), or gain registers (m).

serial interface

The SE/PAR pin must be tied high to enable the serial interface and disable the parallel interface. The serial interface is controlled by five pins as shown below.

sync, din, sclk

Standard 3-wire interface pins.

DCEN Corporation

Select standalone mode or daisy-chain mode.

SDO

Data output pin for daisy-chain mode.

Figure 4 and Figure 5 show the timing diagrams for serial writes to the AD5379 in standalone mode and daisy-chain mode, respectively. The 24-bit data word format for the serial interface is shown in Figure 21.

solo mode

Independent mode is enabled by connecting the DCEN (Daisy Chain Enable) pin low. The serial interface works with both continuous and burst serial clocks. The first falling edge of sync initiates the write cycle and resets a counter that counts the number of serial clocks to ensure the correct number of bits is shifted into the serial shift register. The additional edge on the sync will be ignored until shifted into 24 bits. Once the 24 bits are in, SCLK will be ignored. For another serial transfer, the counter must be reset by a falling sync edge.

Daisy Chain Mode

For systems containing multiple DACs, the SDO pins can be used to chain multiple devices together. This daisy-chain mode can be used for system diagnostics and to reduce the number of serial interface lines.

Connect the DCEN (Daisy Chain Enable) pin high to enable daisy chain mode. The first falling edge of synchronization begins the write cycle. SCLK is continuously applied to the input shift sync low when registered. If more than 24 clock pulses are applied, the data will fluctuate out of the shift register and appear on the SDO line. This data is clocked on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the din input of the next device in the chain, a multi-device interface is constructed. For each AD5379 in the system, 24 clock pulses are required. Therefore, the total number of clock cycles must equal 24n, where n is the total number of AD5379 devices in the chain. If less than 24 clocks are applied, the write sequence is ignored.

Sync should be set high when the serial transfer to all devices is complete. This will lock the input data in each device in the daisy chain and prevent any extra data from being clocked into the input shift register. A continuous SCLK source can be used if the synchronization is kept low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles can be used, and synchronized high after the last clock to lock the data. When the transfer of all input registers is complete, the ldac signal updates all dac registers and simultaneously updates all analog outputs.

data decoding

The AD5379 contains a 14-bit data bus from DB13 to DB0. Depending on the value of reg1 and reg0, this data is loaded into the addressing DAC input register, offset (c) register, gain (m) register or special function register.

address decoding

The AD5379 contains an 8-bit address bus, A7 to A0. This address bus allows each dac input register (x1), each offset (c) register and each gain (m) register to be updated individually.

The reg1 and reg0 bits in the Special Function Register (SFR) (see Table 9) show the decoding of the data, offset and gain registers.

Power decoupling

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5379 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5379 is in a system and multiple devices require an agnd to dgnd connection, this connection should be made at only one point. The star ground point should be as close as possible to the device. For power supplies with multiple pins (V, V, V), it is recommended to tie the pins together and disconnect each power supply once.

The AD5379 should have adequate supply decoupling of 10µF in parallel with 0.1µF on each supply, each as close to the package as possible, ideally close to the device. The 10µf capacitors are of the tantalum bead type. The 0.1µf capacitor should have low effective series resistance (esr) and effective series inductance (esi), such as a common ceramic type that provides a high frequency low impedance path to ground to handle transient currents caused by internal logic switching.

Running digital lines under the equipment should be avoided as these coupled noises can affect the equipment. The analog ground plane should allow operation under the AD5379 to avoid noise coupling. The power lines to the AD5379 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power lines. Fast-switching digital signals should use a digital ground shield to avoid radiating noise to other parts of the board, and must not run near the reference input. Noise must be minimized on all V+ and V (negative) lines. The V pin should be disconnected from the AgNd with a 10 nF capacitor.

Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Microstrip technology is by far the best, but not always possible with double sided. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.

As is the case with all thin packages, care must be taken to avoid bending the CSPBGA package and avoid point loading on the package surface during assembly.

power ups

An on-chip power supply monitor makes the AD5379 robust to power supply sequencing. The power supply monitor powers up the analog section after (V−V) is greater than 7 V (typ). Forces the buffer power-on potential loaded to dutgnd in CLR mode, even if V remains at 0 V. After V is applied, the analog circuit is powered up and the buffered DAC output level is linearly stable over the supply range.

Typical Application Circuit

The high channel count of the AD5379 makes it ideal for applications requiring a high level of integration, such as optics and automatic test equipment (ATE) systems. Figure 22 shows the AD5379 as it will be used in an ATE system. Shown here is a pinout of a typical logic tester. Obviously, many discrete levels are required for pin drivers, active load circuits, parametric measurement units, comparators, and fixtures. In addition to the DAC levels required in the ATE system shown, driver, load, comparator and parametric measurement unit functions are required. Analog devices provide a solution for all of these functions.