feature

With reference and clock; 50 kHz throughput; 61/2 LSB nonlinearity; low noise SHA: 300 mV PP; 32-pin sealed dip; parallel and serial outputs; low power: 900 mW.

application

Medical and analytical instruments; signal processing; data acquisition systems; professional audio; automatic test equipment (ATE); telecommunications.

Product Description

The AD1380 is a complete, low-cost 16-bit analog-to-digital converter that includes an internal reference, clock, and sample/hold amplifiers. Internal thin films on silicon scaling resistors allow analog input ranges of ±2.5 V, ±5 V, ±10 V, 0 V to +5 V, and 0 V to +10 V.

Important performance characteristics of the AD1380 include a maximum linearity error of ±0.003% of FSR (AD1380KD) and a maximum 16-bit conversion time of 14 seconds. The transfer characteristics (gain, offset, and linearity) of s are specified for the ADC/SHA combination, so the total performance is guaranteed for the system. The AD1380 provides data in parallel and serial form with corresponding clock and status outputs. All digital inputs and outputs are TTL or 5V CMOS compatible.

make theory

A 16-bit A/D converter divides the analog input range into 216 discrete ranges or quanta. All analog values within a given quantum are represented by the same numerical code, usually assigned to the nominal mid-range value. In addition to the actual conversion error, the inherent quantization uncertainty associated with the resolution is ±1/2 lsb.

The actual conversion error associated with an A/D converter is a combination of analog errors due to the matching and tracking characteristics of linear circuits, ladder diagrams, and scaling networks, reference errors, and power supply rejection. Matching and tracking errors in the converter are minimized by using a monolithic DAC that includes a scaling network. Initial gain and offset errors are specified as ±0.1%fsr (gain) and ±0.05%fsr (offset). As shown in Figures 2 and 3, these errors can be trimmed to zero by using an external trimming circuit. Linearity error for a unipolar range is defined as the deviation from a true straight line transfer characteristic from a zero-voltage analog input requiring zero digital output to a point defined as full scale. Linearity error is based on dac resistance ratio. It is not adjustable and is the most meaningful indicator of a/d converter accuracy. Differential nonlinearity is a measure of the step width deviation between a code and the ideal least significant bit step size (Figure 1).

Monotonicity requires differential linearity errors to be less than 1 lsb, but monotonic converters may have missing codes. The AD1380 is specified with no missing code over the temperature range specified on the data page.

be careful

There are three types of temperature drift errors: offset error, gain error, and linearity error. Offset drift causes the transfer characteristic on the graph to shift left or right over the operating temperature range. Gain drift causes the transfer characteristic to rotate around zero in the unipolar range, or around the negative full-scale point in the bipolar range. The worst-case accuracy drift is the sum of all three temperature drift errors. Statistically, however, drift error manifests itself as root sum squared (rss), which can be expressed as:

Instructions

Upon receipt of the CONVERT START command, the AD1380 converts the voltage at the analog input to an equivalent 16-bit binary number. The conversion is done as follows: The 16-bit successive approximation register (SAR) has a 16-bit output which is connected to the device bit output pin and the corresponding bit input of the feedback DAC. The analog input is continuously compared with the feedback DAC output, one bit at a time (msb first, lsb last). The decision to reserve or reject each bit is then made at the end of each bit comparison period, depending on the state of the comparator at the time.

Electrostatic discharge sensitive devices. Electrostatic charges of up to 4000 volts build up on the human body and test equipment and can discharge without detection. warn!

Although the AD1380 has proprietary ESD protection circuitry, permanent damage to devices exposed to high-energy electrostatic discharges may occur. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Electrostatic sensitive device

Gain adjustment

The gain adjustment circuit consists of a 100 ppm/°C potentiometer connected to the gain adjustment pin 3 through a 300 kΩ resistor with its slider connected to ±vs, as shown in Figure 2. Pin 5 (offset adjustment) and pin 3 (gain adjustment) may remain open if external trimming is not required.

offset adjustment

The zeroing circuit consists of a 100 ppm/°C potentiometer connected to the comparator input pin 5 of all ranges through a 1.8 MΩ resistor and to its slider across ±VS. As shown in Figure 3, the tolerance of this fixed resistor is not critical, the carbon composition type is usually sufficient. If the offset adjustment potentiometer is set at either end of its adjustment range, using a carbon composition resistor with a temperature of -1200 ppm/°C yields a worst-case offset temperature of 32 lsb14×61 ppm/lsb14×1200 ppm/°C , which is 2.3 ppm/°C of fsr. Since the maximum offset adjustment required is typically no greater than ±16 LSB14, the use of carbon composition offset summing resistors typically contributes no more than 1 ppm/°C of FSR offset TEMPCO.

As shown in Figure 4, if metal film resistors are used (tempco < 100ppm/°C), an alternative bias adjustment circuit for biasing tempco can be ignored.

In either regulation circuit, a fixed resistor connected to pin 5 should be close to this pin to keep the pin connections shorted. The comparator input pin 5 is very sensitive to external noise sensors and should be protected with an analog common line.

opportunity

The timing diagram is shown in Figure 5. Receipt of a conversion start signal sets a status flag to indicate that a conversion is in progress. This in turn removes the inhibition applied to the gated clock, allowing it to run for 17 cycles. All sar parallel bits, state flip-flops, and gated clock inhibit signals are initialized on the trailing edge of the conversion start signal. At time t0, b1 is reset and b2–b16 are set unconditionally. At T1, bit 1 is determined (held) and bit 2 is unconditionally reset. This sequence continues until the bit 16 (lsb) decision (keep) is made at t16. The status flag is reset, indicating that the conversion is complete and the parallel output data is valid. Resetting the status flag will restore the gated clock inhibit signal, forcing the clock output to a low logic "0" state. Note that the clock is kept low until the next conversion. The corresponding parallel data bits become valid on the same positive clock edge.

Digital output data

Parallel and serial data from TTL memory registers are in negative true form (logic "1" = 0 V, logic "0" = 2.4 V). The parallel data output encoding is complementary binary for unipolar ranges and complementary offset binary for bipolar ranges. Parallel data is valid at least 20 ns before the status flag returns to a logic "0", allowing parallel data transfers to be clocked on a "1" to "0" transition of the status flag (see Figure 6).

Serial data encoding is complementary binary encoding for unipolar input ranges and complementary offset binary encoding for bipolar input ranges. Serial output is bitwise (msb first, lsb last) in nrz (does not return zero) format. Serial and parallel data outputs change state on positive clock edges. Serial data is guaranteed to be valid 120 ns after the rising clock edge, allowing serial data to go directly to the receive register on the negative-going clock edge, as shown in Figure 7. There are 17 negative clock edges throughout the 16-bit conversion cycle. The first negative edge shifts an invalid bit into the register, and the register is shifted out on the last negative clock edge. All serial data bits will be transmitted correctly and appear in the receive shift register location at the end of the conversion cycle.

input scaling

To take advantage of the maximum signal resolution of the A/D converter, the AD1380 input should be as close as possible to the maximum input signal range. Connect the input signal as shown in Table 1. See Figure 8 for the circuit.

Calibration (14-bit resolution example)

External zero and gain adjustment potentiometers, connected as shown in Figure 2 and Figure 3, are used for device calibration. To prevent interaction between these two adjustments, always adjust the zero first, then adjust the gain. The zero point is adjusted by the analog input near the most negative end of the analog range (0 for unipolar input range, –fs for bipolar input range). Gain is adjusted through the analog input near the positive end of the analog range.

0 to +10 V range: Set the analog input to +1 LSB14=0.00061 V. Zero the digital output to 11111111110. The zero point is now calibrated. Set the analog input to +fsr–2 lsb=+9.99878 V. Adjust the gain of the 00000000000001 digital output code; now calibrate the full scale (gain). Half-Scale Calibration Check: Set the analog input to +5.00000V; the digital output code should be 011111111111.

–10 V to +10 V range: Set analog input to –9.99878 V; adjust zero for 111111111110 digital output (complementary offset binary) code. Set the analog input to 9.99756 V; adjust the gain of the 00000000000001 digital output (complementary offset binary) code. Half-scale calibration check: Set analog input to 0.00000V; digital output (complementary offset binary) code should be 011111111111.

Other ranges: Typical digital encodings for the 0 V to +10 V and -10 V to +10 V ranges are given above. Coding relationships and calibration points in the 0 V to +5 V, -2.5 V to +2.5 V, and -5 V to +5 V ranges can be achieved by scaling 0 V to +10 V and -10 V to +10 V, respectively. The corresponding code equivalents listed in the range are halved, as shown in Table II.

Using the static adjustment procedure described above, zero and full-scale calibration can be achieved with an accuracy of approximately ±1/2 LSB. By adding a small sine or triangle wave voltage to the signal applied to the analog input, the output can be cycled through each calibration code of interest to more accurately determine the center (or endpoint) of each discrete quantization level. A detailed description of this dynamic calibration technique can be found in "Handbook of Analog to Digital Conversion" edited by DH Sheingold, Prentice Hall, Inc., 1986.

Grounding, Decoupling, and Layout Considerations

Many data acquisition parts have two or more ground pins that are not connected together within the device. These "reasons" are often referred to as logic power return, analog common (analog power return), and analog signal ground. These grounds (pins 8 and 30) must be connected together at one point on the AD1380 as close to the converter as possible. Ideally, a single solid-state analog ground plane under the converter is required. Current flows through the wires and etched stripes on the circuit card, and due to the resistance and inductance of these paths, hundreds of millivolts can be created between the analog ground of the system and the ground pin of the AD1380. A separate wide conductor bar ground return should be provided for high resolution converters to minimize noise and IR losses of current in the path from the converter to the system ground. This way, the AD1380 supply current and other digital logic gate return currents do not add in the same return path as the analog signal, causing measurement errors.

Each AD1380 supply terminal should be capacitively decoupled as close to the AD1380 as possible. A large value capacitor (eg 1µf) in parallel with a 0.1µf capacitor is usually sufficient. The analog power supply is bypassed to the analog power supply return pin, and the logic supply is bypassed to the logic supply return pin. The metal cover is internally grounded with respect to power, ground, and electrical signals. Do not ground the cover from the outside.

Applying AD1380 Dynamic Performance

High-performance sampling analog-to-digital converters like the AD1380 require dynamic characteristics to ensure that they meet or exceed the performance parameters required for signal processing applications. The dynamic characteristics of the signal are analyzed by the fast Fourier transform (fft) analysis technique, and key dynamic parameters such as signal-to-noise ratio (snr) and total harmonic distortion (thd) of the signal are obtained. The results of this characteristic are shown in Figure 11. In testing, a 13.2 kHz sine wave was used as an analog input (FO) at a level of L0dB below full scale; the AD1380 was operated at a word rate of 50 kHz (its maximum sampling frequency).

The 1024-point fft results demonstrate the excellent performance of the converter, especially in terms of low noise and harmonic distortion.

In Figure 11, the vertical scale is based on a full-scale input called 0db. This way, all (frequency) energy cells can be calculated from a full-scale rms input. The resulting signal-to-noise ratio is 83.2 dB, which corresponds to a noise floor of -93.2 dB.

Total harmonic distortion is calculated by adding the rms energy of the first four harmonics and equals -97.5 dB. As shown in Figure 12, increasing the input signal amplitude to -0.4dB of full scale results in an increase in THD to -80.6dB.

However, at lower input frequencies, the thd performance improves. Figure 13 shows the full-scale (–0.3 dB) input signal at 1.41 kHz. THD is now -96.0 dB.

A low-level input signal at any frequency will see the final noise floor. In Figure 14, the noise floor is -94 dB, as shown by the 24 kHz input signal at 39.8 dB.