feature

Unlimited sample and hold capability, with an accuracy of 0.018%; high integration: 32-channel SHA in 12 12 mm2 LFBGA; acquisition time per channel up to 16 seconds; adjustable voltage output range; output voltage span 10V ; output impedance 0.5; Readback capability; dsp/microcontroller compatible serial interface; parallel interface; temperature range -40C to + 85C .

application

Level settings; instrumentation; automatic test equipment; industrial control systems; data acquisition; low-cost I/O.

General Instructions

The AD5533 combines a 32-channel voltage translation function with infinite output hold capability. The analog input voltage is on the common input pin, Vin is sampled, and its digital representation is transferred to the selected DAC register. For this vouch then update the dac to reflect the dac's new content registry. Channel selection is done via parallel address inputs a0–a4 or via the serial input port. The output voltage range is determined by the offset voltage at offs_ in the pin and the gain of the output amplifier. It is limited to a range from vss+2v to vdd–2v because of the output amplifier. Devices at AVCC=5V±5%, DVCC=2.7V to 5.25V, vss=-4.75V to -16.5V, vdd=8V to 16.5V require a stable 3V reference and an offset voltage to turn on disconnect.

Product Highlights

1. Unlimited sag samples and holding capacity.

2. The AD5533 is packaged in a 74-lead LFBGA with a body size of 12 mm × 12 mm.

the term

VIN to VIN nonlinearity

This is a measure of the maximum deviation from a straight line through the VIN endpoint and the VOUT transfer function endpoint. It is expressed as a percentage of full scale.

offset error

This is a way to measure the output error at VIN=70mV. Ideally, when VIN = 70mV:

Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal). It is expressed in mV and can be positive or negative. See Figure 5.

gain error

This is to measure the span error of the analog channel. It is the deviation of the slope of the transfer function. See Figure 5. The calculation is as follows:

in

Output temperature coefficient

This is a way to measure the change in analog output with temperature. Expressed in ppm/°C.

DC power rejection ratio

The DC Power Supply Rejection Ratio (psrr) is a measure of the change in the analog output as the power supply voltage (vdd and vss) changes. It is represented in dbs. Variation in vdd and vss was ±5%.

DC crosstalk

This is a DC change in the output level of one channel in response to a full-scale change in the outputs of all other channels. Expressed in microvolts.

Output stabilization time

This is the time from the busy state going high until the output settles to ±0.018%.

Acquisition time

This is the time it takes to get the VIN input. It's the length of the busy time that keeps a low profile.

settlement time

This is the time from a 0 V–3 V step change in the input voltage until the output settles to within ±0.35%.

digital feedthrough

This is a measure of the pulse injected into the analog output from the digital control input when the part is not written, i.e. when cs/sync is high. It is specified in nv secs and is measured on a digital input pin with a worst-case change, e.g. from 0 to 1 and vice versa.

Output Noise Spectral Density

This is random noise generated inside the measurement. Random noise is characterized by its spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring the noise at the output. The unit is nv/(√)1/2.

AC crosstalk

This is the area where a fault occurs on the output of one channel while the other channel is acquiring. It is expressed in nv secs.

Function description

The AD5533 can be thought of as a package consisting of an ADC and 32 DACs. The input voltage vin is sampled and converted into a digital word. The digital result is loaded into a DAC register and converted to an analog output voltage (VOUT0–VOUT31). Since the channel output voltage is the effective output of the DAC, there is no droop associated with it. As long as power to the device is maintained, the output voltage will remain constant until the channel is addressed again.

To update the output voltage of a single channel, a new voltage level needs to be set on the common input pin, vin. The desired channel is then addressed through the parallel port or serial port. When the channel address is loaded, as long as the track is high, the circuit starts getting the correct code to load into the dac so that the dac output matches the voltage on vin. The busy pin goes low and remains so until the acquisition is complete. During acquisition, the non-converted input of the output buffer is associated with vin to avoid spurious outputs when the DAC gets the correct code. Acquisition is completed within a maximum of 16 microseconds. The busy pin goes high and the updated DAC output assumes control of the output voltage. The output voltage of the DAC is connected to the non-rotating input of the output buffer. As long as the power supply to the device remains the same, the held voltage will remain on the output pin indefinitely without dropping.

At power-up, all DACs (including the offset channel) are loaded with zeros. The output of the DAC is typically 50 mV (negative full scale). If the off_in pin is driven by the on-board offset channel, the outputs vout0 to vout31 are also in 50 mV powered state, because off_in = 50 mV (vout = 3.52 × vdac – 3.52 × voffs = 176 mV – 126 mV =50 mV).

analog input

The equivalent analog input circuit is shown in Figure 11. Capacitor c1 is typically 20pf attributable to pin capacitance and 32 off channels. An additional 7.5 pf (typ) is turned on when a channel is selected. Capacitor C2 is charged to the voltage previously obtained on the particular channel, so it must be charged/discharged to the new level. Crucially, an external power source can charge/discharge this additional capacitor within the 1µs–2µs range of channel selection to enable accurate VIN acquisition. Therefore, a low impedance power supply is recommended.

A large source impedance will significantly affect the performance of the ADC. This may require the use of an input buffer amplifier.

Output buffer stage gain and offset

The function of the output buffer stage is to convert the 0v-3v output of the DAC to a wider range. This is done by increasing the DAC output by 3.52 and offsetting the voltage by a voltage switch in the pin.

VDACI is the output of the DAC, and voffs is the voltage at off in the pin.

The offset voltage can be supplied externally by the user at off-in, or by an additional offset voltage channel on the device itself. The desired bias voltage is set on the VIN (vin) and taken by the bias DAC. The dac output of this offset channel is connected directly to off_out. This offset voltage can be used as the offset voltage for the 32 output amplifiers by connecting off_out to off_. It is important to choose the offset so that VOUT is at the maximum rating.

Reset function

The reset function on the AD5533 can be used to reset all nodes on the device to a power-on reset state. This is accomplished by applying a low-pass pulse of 50 ns to 150 ns on the track/reset pin on the device. If the applied pulse is less than 50ns, a fault is assumed and no action is taken. If the applied pulse is greater than 150ns, the pin adopts its tracking function on the selected channel, the VIN (vin) switches to the output buffer, and the acquisition on the channel does not occur until the rising edge of the track.

Track function

Normally, in SHA mode of operation, the track is held high and the channel starts to be acquired when it is addressed. However, if the track is low when the channel is being addressed, the VIN (vin) is switched to the output buffer and the acquisition on the channel is not performed until the rising edge of the track. At this stage, the busy pin will go low until the acquisition is complete, at which point the DAC assumes control of the output buffer's voltage and the VIN can be changed again without affecting this output value.

This is useful in applications where the user wants to increase the VIN until VOUT reaches a certain level (Figure 12). During the rising process of the VIN, it is not necessary to continuously acquire the VIN. The rail can be held low and only rises when VOUT reaches its desired voltage. At this stage, the acquisition of the vehicle identification number begins.

In the example shown, the output of the pin driver requires a desired voltage. This voltage is represented by an input of the comparator. The microcontroller/microprocessor boosts the input voltage on the VIN through the DAC. When the voltage on the VIN rises, the track remains low so that the VIN is not continuously acquired. When the output of the pin driver reaches the desired voltage, the comparator output switches. The µc/µp then knows what code needs to be entered to get the desired voltage at the dut. The track input is now high and the part starts getting the VIN. The busy state will go low until the vehicle identification number (vin) is obtained. When busy goes high, the output buffer switches from vin to the output of the dac.

operating mode

The AD5533 can be used in three different modes. These modes are set by two mode bits (the first two bits of the serial word). Option 01 (DAC mode) does not apply to the AD5533. If you try to set the DAC mode, the AD5533 will enter a test mode, which will take 24 hours of writing to clear.

1. SHA mode

In this standard mode, a channel is addressed that obtains the voltage on the VIN. This mode requires a 10-bit write to address the relevant channel (VOUT0–VOUT31, offset channel, or all channels). Write msb first.

2. Get and read back mode

This mode allows the user to get the vehicle identification number (vin) and read the data in a specific dac register. The associated channel is addressed (10-bit write, msb first) and vin is acquired in 16 microseconds (max). After acquisition, after the next falling edge of synchronization, the data in the associated dac register is clocked out to the dout line in 14-bit serial format. During readback, din is ignored. The full acquisition time must elapse before the DAC register data can be clocked.

3. Readback mode

Again, this is a readback mode, but no acquisition is performed. The associated channel is addressed (10-bit write, msb first), and on the next falling edge of sync, the data in the associated DAC register is clocked out to the dout row in 14-bit serial format. The user must allow 400 ns (minimum) between the last falling edge of SCLK for a 10-bit write and the synchronous falling edge for a 14-bit readback. Consecutive reading and writing words are shown in Figure 13.

This feature allows the user to read the DAC register code for any channel. Readback is useful if the system is calibrated and the user wants to know which code in the DAC corresponds to the desired voltage on VOUT.

interface serial interface

The SE/PAR pin is tied high to enable the serial interface and disable the parallel interface. The serial interface is controlled by four pins as follows: sync, din, sclk

Standard 3-wire interface pins. The sync pins are shared with the CS function of the parallel interface.

Ding out

Data output pin for reading the contents of the DAC register. Data is clocked on the rising edge of SCLK and valid on the falling edge of SCLK.

calibration bit

When this value is high, all 32 channels acquire the VIN simultaneously. Then, the acquisition time is 45 microseconds (typical) and the accuracy can be reduced.

Offset select bits

If this bit is set high, the offset channel is selected and bits A4–a0 are ignored.

test bit

This value must be set low for the part to function properly.

A4–A0

Used to address any of the 32 channels (A4=msb of address, a0=lsb).

DB13–DB0

In both readback modes, they are used to read 14-bit words from the addressed DAC registers.

The serial interface is designed to allow easy interfacing with most microcontrollers and DSPs such as PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320 and ADSP-21XX without any glue logic. When connected to an 8051, SCLK must be inverted. The Microprocessor/Microcontroller Interface section explains how to interface with some popular DSPs and microcontrollers.

Figures 3 and 4 show the timing diagrams for serial reading and writing to the AD5533. The serial interface can work with both continuous and non-continuous serial clocks. The first falling edge of sync resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift register. Any other edges while synchronizing are ignored until the correct number of bits is shifted in or out. SCLK is ignored once the correct number of bits has been shifted in or out. For another serial transfer, the counter must be reset by a synchronous falling edge. In readback, the first rising sclk edge after the sync falling edge causes dout to leave its high-impedance state, and data is clocked out on the dout line and on subsequent rising sclk edges. On the falling edge of the 14th SCLK, the double pin returns to a high impedance state. Data is latched on the first falling edge of sclk and subsequent falling edges of sclk after the falling edge of the sync signal. Serial interfaces do not shift data in or out until the falling edge of the sync signal is received.

Parallel interface

The SE/PAR bit must be tied low to enable the parallel interface and disable the serial interface. The parallel interface is controlled by 9 pins.

CS

Active low packet select pin. This pin is shared with the synchronization function of the serial interface.

WR

Active low write pin. The value on the address pin is latched on the rising edge of wr.

A4–A0

Five address pins (A4 = msb of address, a0 = lsb). They are used to address related channels (probably 32).

offset selection

Offset selection pin. This has the same function as the offset select bits in the serial interface. When it is high, the offset channel is addressed and addresses on A4–a0 are ignored.

Cal

Same function as the calibration bit in the serial interface. When this pin is high, all 32 channels get the VIN simultaneously.

Microprocessor interface

AD5533 to ADSP-21xx interface

The DSPs of the ADSP-21XX family are easy to interface with the AD5533 without additional logic.

After motion is enabled, data transfer is initiated by writing a word to the TX register. During the write sequence, data is clocked on every rising edge of the dsp serial clock and clocked to the AD5533 on the falling edge of its sclk. In readback, 16-bit data is clocked out of the AD5533 on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK. din is ignored. With this configuration, the valid 14-bit data will be concentrated in the 16-bit RX register. The settings of the motion control registers are as follows:

tfsw=rfsw=1, alternate frames

invrfs=invtfs=1, valid low frame signal

dtype=00, right-aligned data

ISCLK=1, internal serial clock

tfsr=rfsr=1, one frame per word frame

irfs=0, external frame signal

itfs=1, internal frame signal

slen=1001, 10-bit data word (SHA mode write) slen=1111, 16-bit data word (readback mode) Figure 14 shows the connection diagram.

AD5533 to MC68HC11

The Serial Peripheral Interface (SPI) on the MC68HC11 is configured in master mode (MSTR=1), clock polarity bit (CPOL)=0 and clock phase bit (CPHA)=1. SPI is configured by writing to the SPI Control Register (SPCR) - see the 68HC11 User Manual. The SCK of the 68HC11 drives the SCLK of the AD5533, the MOSI output drives the serial data line (DIN) of the AD5533, and the MISO input is driven by DOUT. The sync signal comes from the port line (PC7). When data is sent to the AD5533, the sync line is taken low (pc7). The data displayed on the mosi output is valid on the falling edge of sck. Serial data for the 68HC11 is transmitted in 8-bit bytes, with only 8 falling clock edges during the transmission cycle. First transmit data msb. In order to transfer 10 data bits in SHA mode, the data in the SPDR register must be left aligned. PC7 must be pulled low to start the transfer. It is turned up and down again before any further read/write cycles. The connection diagram is shown in Figure 15.

AD5533 to PIC16C6X/7X

The PIC16C6x Synchronous Serial Port (SSP) is configured as a SPI master with the clock polarity bit set to 0. This is done by writing to the Synchronous Serial Port Control Register (sspcon). Please refer to the User's PIC16/17 Microcontroller User's Manual. In this example, I/O port RA1 is used for pulse synchronization and enables the serial port of the AD5533. The microcontroller transfers only 8 bits of data during each serial transfer operation; therefore, a 10-bit write and 14-bit readback require two consecutive read/write operations. Figure 16 shows the connection diagram.

AD5533 to 8051

The AD5533 requires a clock that is synchronized with the serial data. Therefore, the 8051 serial interface must operate in mode 0. In this mode, serial data is entered and exited through RXD, and a shift clock is output on TXD. Figure 17 shows how the 8051 is connected to the AD5533. Because the AD5533 shifts out data on the rising edge of the shift clock and latches the data on the falling edge, the shift clock must be inverted. AD5533 requires its data to have msb first. Because the 8051 outputs the lsb first, the send routine has to take this into account.

Application circuit

AD5533 in a typical ATE system

The AD5533 infinite sample and hold is ideal for use in automated test equipment. Several SHAs are required to control pin drivers, comparators, active loads and signal timing. Traditionally, a sample-and-hold device with droop has been used in this application. These need to be refreshed to prevent voltage drift.

The AD5533 has several advantages: no refresh required, no droop, elimination of pedestal errors, and no need for additional filtering to eliminate glitches. Overall, a higher level of integration is achieved in a smaller area, see Figure 18.

Typical Application Circuit

The AD5533 can be used to set the voltage levels on 32 channels, as shown in the following figure. The AD780 provides the 3 V reference for the AD5533 and AD5541 16-bit DACs. A simple 3-wire interface is used to write to the AD5541. The DAC output is buffered by the AD820. When laying out this circuit, noise on the VIN and refill must be minimized.

Power decoupling

In any circuit where accuracy is important, careful consideration of power and ground return layout helps ensure rated performance. The printed circuit board on which the AD5533 is mounted should be designed to keep the analog and digital sections separate and confined to certain areas of the board. If the AD5533 is in a system where multiple devices require an AGND to DGND connection, this connection should only be made at one point. The star ground point should be as close as possible to the device. For power supplies with multiple pins (vss, vdd, avcc) it is recommended to tie these pins together. The AD5533 should have ample supply bypassing of 10µF in parallel, and 0.1µF on each supply should be as close to the package as possible, ideally close to the device. The 10µf capacitors are of the tantalum bead type. The 0.1µf capacitor should have low effective series resistance (esr) and effective series inductance (esi), like common ceramic types that provide a high-frequency, low-impedance path to ground to handle transient currents from internal logic switches.

The power lines to the AD5533 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals such as clocks should use a digital ground shield to avoid radiating noise to other parts of the board and must not run near the reference input. A ground wire routed between the din and sclk wires will help reduce crosstalk between them (not needed on multi-layer boards as there will be a separate ground plane, but separating these wires will help reduce crosstalk ). Noise on the VIN and refill lines must be minimized.

Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This reduces feedthrough effects through the board. Microstrip technology is by far the best, but not always possible with double sided. In this technique, the component side of the board is dedicated to the ground plane, while the signal lines are placed on the solder side.