feature

Complete 16-bit converter with reference and clock; 0.003% maximum nonlinearity; no missing codes over temperature over 14 bits; fast conversion; 17 microseconds to 16 bits ( AD1376 ); 10 microseconds to 16 bits (AD1377); short Cycle Capability; Adjustable Clock Rate; Parallel Output; Low Power; 645 mW typical (AD1376); 585 mW typical (AD1377); industry standard pins.

General Instructions

The AD1376/AD1377 are high resolution 16-bit analog-to-digital converters with internal reference, clock, and laser edge thin film application resistors. The AD1376/AD1377 are ideal for use in high-resolution applications requiring moderate speed and high accuracy or stability over the commercial temperature range (0°C to 70°C). They are packaged in a compact 32 lead, ceramic seam sealed (hermetic), dual in-line package (DIP). Thin-film scaling resistors offer bipolar input ranges of ±2.5 V, ±5 V, and ±10 V, and unipolar input ranges of 0 V to +5 V, 0 V to +10 V, and 0 V to +20 V.

Digital output data is provided in parallel with the corresponding clock and status outputs. All digital inputs and outputs are TTL compatible.

For the AD1376, the serial output function is no longer available after date code 0111. For the AD1377, the serial output function is no longer available after date code 0210. The option to apply an external clock on the conversion start pin to reduce the internally set conversion time is no longer supported in any part.

Product Highlights

1. The AD1376/AD1377 provide 16-bit resolution at 25°C with a maximum linearity error of ±0.003% (1/2 LSB).

2. The AD1376 conversion time is 14 microseconds (typical value), the short cycle is 14 bits, and 16 microseconds is 16 bits.

3. The AD1377 conversion time is 8 microseconds (typical value), the short cycle is 14 bits, and 9 microseconds is 16 bits.

4. There are two binary codes on the digital output. They are csb (complementary straight binary) for unipolar input voltage ranges and cob (complementary bias binary) for bipolar input ranges. Complementary Two's Complement (CTC) can be obtained by inverting pin 1 (msb).

Instructions

Upon receiving a conversion start command, the AD1376/AD1377 convert the voltage at the analog input to an equivalent 16-bit binary number. This conversion is done as follows: The 16-bit successive approximation register (SAR) has its 16-bit output, connected both to the device bit output pins and to the corresponding bit input of the feedback DAC. The analog input is compared to the feedback DAC output continuously, one at a time (msb first, lsb last). The decision to reserve or reject each bit is then made at the end of each bit comparison period, depending on the state of the comparator at the time.

Gain adjustment

The gain adjustment circuit consists of a 100 ppm/°C potentiometer connected to pin 29 (gain adjustment) through a 300 kΩ resistor with a slider across ±V, as shown in Figure 5.

Pin 27 (comparator) and pin 29 can be left open if no trim adjustment is required.

Zero offset adjustment

The zero-offset adjustment circuit consists of a 100 ppm/°C potentiometer connected to pin 27 on all ranges through a 1.8 MΩ resistor with a slider across ±V. As shown in Figure 6, the tolerance of this fixed resistor is not critical; the carbon composition type is usually sufficient. If the offset adjustment potentiometer is set at either end of its adjustment range, using a carbon composition resistor with a -1200 ppm/°C temperature coefficient provides a Worst offset temperature coefficient of fsr. Since the maximum offset adjustment required is typically no greater than ±16 LSB, the use of carbon composition offset summing resistors typically contributes no more than 1 ppm/°C of FSR offset temperature coefficient.

As shown in Figure 7, if metal film resistors are used (temperature coefficient <100 ppm/°C), an alternative offset adjustment circuit for offset temperature coefficient can be ignored.

In either regulation circuit, the fixed resistor connected to pin 27 should be close to this pin to keep the pin connections shorted. Pin 27 is very sensitive to external noise sensors and should be protected by the analog common.

opportunity

The timing diagram is shown in Figure 8. Receipt of a conversion start signal sets a status flag to indicate that a conversion is in progress. This in turn removes the inhibition applied to the gated clock, allowing it to run for 17 cycles. All sar parallel bits, state flip-flops, and gated clock inhibit signals are initialized on the trailing edge of the conversion start signal. At time t, b is reset and b–b is set unconditionally. At t, the decision to (hold) bit 1 is made and bit 2 is reset unconditionally. This sequence continues until the bit 16 (lsb) decision (keep) is made at t. Status flags are reset, indicating that the conversion is complete and the parallel output data is valid. Resetting the status flag will restore the gated clock inhibit signal, forcing the clock output to a low logic 0 state. Note that the clock is kept low until the next conversion.

The corresponding parallel data bits become valid on the same positive clock edge.

Digital output data

Parallel data from TTL storage registers is in negative true form (logic 1=0V, logic 0=2.4V). The parallel data output encoding is complementary binary for unipolar ranges and complementary offset binary for bipolar ranges. Parallel data becomes valid at least 20 ns before the status flag returns to logic 0, allowing parallel data transfers to be clocked on the 1-to-0 transition of the status flag (see Figure 9). The parallel data output changes state on the positive clock edge.

short cycle input

Pin 32 (short cycle) allows the timing cycle shown in Figure 8 to terminate after any number of desired bits have been converted, allowing for slightly shorter conversion times in applications that do not require full 16-bit resolution. When 10-bit resolution is required, pin 32 is connected to the 11th bit output pin 11. Then the conversion cycle is terminated and the status flag is reset after the 10th bit decision (Figure 8). Table 3 summarizes the short-cycle connections and associated 8, 10, 12, 13, 14, and 15-bit conversion times for a 1.6MHz clock (AD1377) or a 933kHz clock (AD1376).

input scaling

The ADC input should be as close as possible to the maximum input signal range to use the maximum signal.

Calibration (14-bit resolution example)

External zero trim and gain trim potentiometers, connected as shown in Figure 5 and Figure 6, are used for device calibration. In order to prevent the interaction of the two when adjusting, always adjust the zero point first, and then adjust the gain. Zero is adjusted close to the analog range with the analog input (0 for monopole, negative full-scale input range for bipole). The gain passes near the most positive end of the analog range. The 0 V to 10 V range sets the analog input to +1 LSB14=0.00061 V. Digital zero output = 11111111110. The zero point is now calibrated. Set the analog input to +FSR−2 LSB=9.99878 V. Adjust gain 00000000000001 digital output code; full scale (gain) is now calibrated. Half-Scale Calibration Check: Set the analog input to 5.00000V; the digital output code should be 011111111111.

-10 V to +10 V range

Set analog input to -9.99878 V; set 111111111 0 to zero digital output (complementary offset binary) code. Set analog input to 9.99756 V; adjust 000000000000001 digital gain output (complementary offset binary) code. Half-Scale Calibration Check: Set analog input to 0.00000V; digital output (complementary offset binary) code should be 011111111111.

Other scope

Representative digital codes for 0 V to +10 V and -10 V to + give the 10 V range in the 0 V to 10 V range section, and the -10 V to +10 V range segment. Coding relationships and calibration points for 0 V to +5 V, -2.5 V to +2.5 V, and -5 V to +5 V ranges are listed by halving 0 V to +10 V and -10 V to + 10 V range.

Zero and full-scale calibration can achieve an accuracy of about ±1/2 LSB using the previously described static adjustment procedure. By adding a small sine or triangle wave voltage to the signal applied to the analog input, the output can be cycled through each calibration code of interest to more accurately determine the center (or endpoint) of each discrete quantization level. A detailed description of this dynamic calibration technique can be found in Prentice Hall, Inc., edited by DH Sheingold, 1986.

Grounding, Decoupling, and Layout Considerations

Many data acquisition parts have two or more ground pins that are not connected together within the device. These grounds are often referred to as digital common (logic power return), analog common (analog power return), or analog signal grounds. These grounds (pin 19 and pin 22) must be connected together at a point as close to the torque converter as possible. Ideally, a single solid-state analog ground plane is required under the converter. Current flows through the wires and etched stripes of the circuit card, and due to the resistance and inductance of these paths, hundreds of millivolts can be generated between the analog ground of the system and the ground pin of the ADC. A separate wide conductor bar ground return should be provided for high resolution converters to minimize noise and IR losses of current in the path from the converter to the system ground. This way, the ADC's supply current and the return currents of other digital logic gates do not add in the same return path as the analog signal, and these currents can cause measurement errors.

Each ADC supply terminal should be as close as possible to the ADC for capacitive decoupling. A large value (eg 1µf) capacitor in parallel with a 0.1µf capacitor is usually sufficient. Analog power is bypassed to analog common (analog power return) pin 22 and logic power is bypassed to digital common (logic power return) pin 19.

The internal ground of the metal cover is related to power, ground and electrical signals. Do not ground the cover from the outside.

clock rate control

As shown in Figure 13, the AD1376/AD1377 can be operated with faster conversion times by connecting the clock rate control (pin 23) to an external multi-turn trim potentiometer (TCR < 100 ppm/°C).

High Resolution Data Acquisition System

The basic details of a high-resolution data acquisition system using a 16-bit sample-and-hold amplifier (SHA) and the AD1376/AD1377 are shown in Figure 14. Conversions are initiated by the falling edge of the conversion start pulse. This edge makes the device's status line high. Then, the inverter drives the SHA into holdover mode. The state remains high throughout the conversion and returns low when the conversion is complete. This allows SHA to re-enter tracking mode.

This circuit can show nonlinearity caused by transients at the adc input caused by the falling edge of the conversion start. This edge resets the ADC's internal DAC; the resulting transient depends on the current output voltage of the SHA and the ADC's previous conversion results. In the circuit of Figure 15, the falling edge of conversion initiation also puts the SHA into hold mode (via the ADC's status output), causing a reset transient to occur simultaneously with the SHA's track-and-hold conversion. Timing skew and capacitive coupling can cause some transients to be added to the signal acquired by the SHA, introducing nonlinearity.

A safer approach is to add triggers, as shown in Figure 15. The rising edge at the start of conversion puts the track-and-hold device into hold mode before the ADC reset transient begins. The falling edge of the state puts the SHA back into tracking mode. System throughput will decrease if long conversion start pulses are used. Throughput can be from:

Where? T-type acquisition is track and hold acquisition time. T-convolution and polynomial multiplication is the time required for ADC conversion. is the duration at which the transition starts. The combination of T-type CS AD1376 and 16-bit SHA can provide greater than 50khz throughput. If the transition starts with a width smaller than the ADC's transition time, no significant track-and-hold droop error will be introduced.

application

The AD1376/AD1377 are ideal for high resolution applications requiring moderate speed and high accuracy stability over the commercial (0°C to 70°C) temperature range. Typical applications include medical and analytical instruments, precision measurement of industrial robots, automatic test equipment (ATE), multi-channel data acquisition systems, servo control systems, or any wide dynamic range required. Proprietary monolithic DAC and laser-trimmed thin-film resistors guarantee maximum nonlinearity? 0.003% (1/2 LSB14). Converters may be short-cycled to achieve faster conversion times—15 microseconds to the 14-bit AD1376 or 8 microseconds to 14 bits for the AD1377.