General Instructions
w947d6hb/w947d2hb is a high-speed low-power double data rate synchronous dynamic random access memory (lpddr-sdram), access to lpddr-sdram is burst-oriented. When rows and columns are selected using active commands, contiguous memory locations within a page can be accessed in burst lengths of 2, 4, 8, and 16. In burst operation, the column address is automatically generated by the lpddr sdram internal counter. A random column can also be read by providing its address every clock cycle. The multi-bank nature allows inter-bank staggering to hide pre-charge time. By setting the programmable mode register, the system can vary the burst length, delay period, interleaving or sequential bursts to maximize its performance. The device supports special low-power features such as partial array self-refresh (pasr) and automatic temperature

feature
VDD=1.7~1.95V
vddq=1.7~1.95v;
Data Width: x16/x32 Clock Frequency: 200MHz (-5), 166MHz (-6), 133MHz (-75) Partial Array Self-Refresh (pasr) Automatic Temperature Compensation Self-Refresh (ATCSR) Power Down Mode Deep Power Down Mode (DPD Mode) Programmable Output Buffer Drive Strength Four Internal Banks Simultaneously Operating Data Mask (dm) for Write Data Inputs (CK and CK) bidirectional, data strobe (DQ)

block diagram

Simplified State Diagram

initialization
lpddr sdram must be started and initialized in a predefined way. An operation procedure other than the one specified may result in an undefined operation. If power to the device is interrupted, the initialization procedure should be followed. The steps to be followed for device initialization are as follows.
The mode register and extended mode register have no default values. Unspecified actions may result if they are not programmed during initialization. The clock stop function is not available until the device is properly initialized from steps 1 to 11.
l Step 1: To provide power, the device core power supply (VDD) and the device I/O power supply (VDDQ) must be enabled at the same time to prevent the device from locking. Although not required, it is recommended that VDD and VDDQ come from the same supply. Clock Enable (CKE) while asserting and holding LVCMOS logic high
l Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply a stable clock.
l Step 3: There must be a valid clock of at least 200μs before issuing any command to the dram. During this time, a nop or deselect command must be issued on the command bus.
l Step 4: Issue the precharge all command.
l Step 5: Provide the nops or deselect command for at least trp time.
l Step 6: Issue an automatic refresh command, followed by a nops or deselect command, and execute at least a period of trfc. Issue a second auto-refresh command followed by nops, or at least deselect commands for trfc time. NOTE: As part of the initialization sequence, two auto-refresh commands must be issued. The typical flow is to publish them at step 6, but they may also be published between steps 10 and 11.
l Step 7: Use the mrs command to program the basic mode register. Set the desired operating mode.
l Step 8: Provide nops or deselect commands for at least tmrd time.
l Step 9: Use the mrs command to program the extended mode registers for the desired operating mode. Note: The order in which the Basic and Extended Mode registers are programmed is not important.
l Step 10: Provide the nop or deselect command for at least tmrd time.
l Step 11: The DRAM is properly initialized and ready to execute any valid command.
Initialization Flowchart

Initialize the waveform sequence

The mode register sets the operating mode register used to define the specific operating mode of the lpddr sdram. This definition includes definitions of burst length, burst type, and cas delay, as shown in the following figure.
The mode registers are programmed through the mode register set command (BA0=0 and BA1=0) and will retain the stored information until reprogramming, the device enters deep power-down mode, or the device is powered down.
Mode register bits a0-a2 specify the burst length, a3 specifies the burst type (sequential or interleaved), and a4-a6 specify the cas delay. A logic 0 should be programmed for all undefined address bits to ensure future compatibility.
The mode register must be loaded when all banks are idle and no pulses are in progress, and the controller must wait the specified time tmrd before initiating any subsequent operations. Violating these requirements will result in unspecified actions.
Reserved state should not be used as it may lead to unknown operation or incompatibility with future versions.

Mode Register Definition

burst length

Read and write access to the lpddr sdram is burst-oriented, and the burst length and burst type are programmable.
The burst length determines the maximum column location that can be accessed for a given read or write command. Both sequence and interleaved burst types can use burst lengths of 2, 4 or 8 positions.
When a read or write command is issued, a column block equal to the burst length is effectively selected. All accesses for this burst are made within a block, which means that if a boundary is reached, the burst will be packed within a block.
When the burst length is set to 2, the block is uniquely selected by a1-an; when the burst length is set to 4, the block is uniquely selected by a2-an; when the burst length is set to 8, the block is uniquely selected by a3-an (where an is the most significant column address bits for a given configuration). The remaining (least significant) address bits are used to select the starting location within the block. The programmed burst length applies to both read and write bursts.

Burst Type Accesses within a given burst can be programmed to be sequential or interleaved; this is called the burst type and is selected by bit a3. The order of accesses within a burst is determined by the burst length, burst type, and starting column address, as shown in the table above.
Read Latency Read Latency is the delay between the registration of a read command and the availability of the first output data. The delay should be set to 2 or 3 clocks.
If a read command is registered at clock edge n with a delay of 3 clocks, the first data element will be valid at n+2 tck+tac. If a read command is registered at clock edge n with a delay of 2 clocks, the first data element will be valid at n+tck+tac.
The Extended Mode Registers describe the Extended Mode Registers control functions beyond those controlled by the Mode Registers; these additional functions include output driver strength selection and Partial Array Self-Refresh (PASR). PASR is only valid in self-refresh mode.
The extended mode registers are programmed via the mode register set command (BA1=1 and BA0=0) and will retain the stored information until reprogramming, the device enters deep power-down mode, or the device is powered down.
The extended mode register must be loaded when all banks are idle and no pulses are in progress, and the controller must wait the specified time tmrd before initiating any subsequent operations. Violating these requirements will result in unspecified actions.
Address bits a0-a2 specify pasr and a5-a7 specify driver strength. A logic 0 should be programmed for all undefined address bits to ensure future compatibility.
Reserved state should not be used as it may lead to unknown operation or incompatibility with future versions.

Status Register Read Status Register Read (srr) is an optional feature of jedec and implemented in this device. Using srr, a method is defined to read registers from the device. The encoding of the srr command is the same as mrs with ba[1:0]="01". The address pins (a[n:0]) encode the register to read. Currently only one register is defined at a[n:0]=0. The sequence of executing the srr command is as follows:
l All read/write operations must be completed
l All banks must be closed
l Issue MRS (SRR) with Ba=01
l Waiting for TSRR
l Read to any bank/page
l After the cas delay period, the device returns the register data, just like normal reading. After issuing the read command, the next command tsrc can be issued to the device.
The burst length for srr reads is always fixed to length 2.

srr register (a[n:0]=0)

Status Register Read Timing Diagram

notes:
1. The SRR can only be issued after the power-up sequence is complete.
2. SRR can only be issued if all banks are pre-charged.
3. srr cl and the value in the mode register remain unchanged.
4. SRR BL fixed at 2.
5. tsrr=2 (minimum).
6. tsrc=cl+1; (minimum time from read to next valid command)
7. Commands other than nop and des are not allowed between srr and read.

Local Matrix Auto-Refresh For partial array self-refresh (pasr), the self-refresh can be limited to a variable portion of the entire array. You can choose the entire array (default), 1/2 array, or 1/4 array. Data outside the defined area will be lost. Address bits a0 to a2 are used to set the pasr.
Automatic temperature compensation self-refresh The device has automatic temperature compensation self-refresh function. It automatically adjusts the refresh rate based on the device temperature without any register updates. To maintain backward compatibility, the device has automatic TCSR, ignoring (don't care) the input of address bits A3 and A4 during EMRS programming.
Output Drive Strength The drive strength can be set to full, half, or three-quarter strength through address bits a5 and a6. The half drive strength option is suitable for lighter loads or point-to-point environments.
Command All commands (address and control signals) are recorded on the positive edge of the clock (the intersection of CK goes high and CK falls).

Action deselect The deselect function (CS=high) prevents the lpddr sdram from executing new commands. lpddr sdram is effectively deselected. Operations already in progress are not affected.
Operation prohibited
The no operation (nop) command is used to execute nop = low on the selected lpddr sdram (cs). This prevents unwanted commands from being registered in idle or wait states. Operations already in progress are not affected.
Mode Register Set Mode Register and Extended Mode Register are loaded via address input. The mode register set command can only be issued when all ranks are idle and no pulses are in progress, and subsequent executable commands cannot be issued until tmrd is satisfied.
Mode Register Set Command Mode Register Set Command Timed Active Before issuing any read or write commands to a bank in lpddr sdram, a row in that bank must be opened. This is done with the activation command: ba0 and ba1 select the bank, and the address input selects the row to activate. Multiple banks can be active at any one time.
Once a line is open, read or write commands can be issued to the line according to the trcd specification.
Subsequent active commands on another line in the same line can only be issued after closing the previous line. The minimum time interval between two consecutive activation commands on the same group is defined by trc.
Active commands While visiting the first bank, subsequent active commands can be issued to another bank, which will reduce the overall row access overhead. trrd defines the minimum time interval between two consecutive activation commands on different columns.
The bank is active until a precharge command (or a read or write command with automatic precharge) is issued to the bank.
A precharge (or read with auto-precharge or write with auto-precharge) command must be issued before opening other rows in the same bank.
Bank Activation Command Loop Read
The read command is used to initiate a burst read access to the active row, the burst length is set in the mode register. ba0 and ba1 select the bank, and the address input selects the starting column position. The value of A10 determines whether to use automatic pre-charging. If auto-precharge is selected, the row being accessed is precharged at the end of the read burst; if auto-precharge is not selected, the row will remain open for subsequent accesses.
read command
The basic read timing parameters for DQ are shown in the figure below; they apply to all read operations.
Basic Read Timing Parameters During a read burst, the dqs are driven by the lpddr sdram along with the output data. The initial low state of the dqs is called the read preamble; the low state consistent with the last data output element is called the read tail code. The first data output element is edge-aligned with the first rising edge of dqs, and successive data output elements are edge-aligned with successive edges of dqs. As shown in the figure below, the cas delays are 2 and 3.
On completion of a read burst, dq will go to high-z, assuming no other read commands have been initiated.
Read bursts showing cas latency read to read data from the read burst can be concatenated or truncated by subsequent read commands. The first data from a new burst either follows the last element of the completed burst, or the last required element of a longer burst that was truncated. A new read command should be issued x cycles after the first read command, where x is equal to the number of required pairs of data output elements (pairs are required for 2n prefetch architectures). As shown below.
Continuous Read Pulse Non-Continuous Read Pulse A read command can be initiated on any clock cycle after the previous read command. Non-sequential reading is shown in the figure below.
A random read pulse can perform full-speed random read access in one or more pages, as shown in the following figure.
Read Burst Termination The data in any read burst can be truncated with the burst termination command, as shown. The burst termination latency is equal to the read (cas) latency, i.e. the burst termination command is issued x cycles after the read command, where x is equal to the desired pair of data output elements.
The read and write must complete or truncate the data from the read burst before issuing a subsequent write command. If truncation is required, the burst termination command must be used, as shown in the figure below, for nominal TDQ
A read-to-precharge read burst can be followed by a precharge command in the same bank, or truncated with a precharge command (provided auto-precharge is not activated). The precharge command should be issued x cycles after the read command, where x is equal to the number of required pairs of data output elements. As shown below. After a precharge command, no subsequent commands can be issued to the same bank until the TRP is satisfied. Note that a portion of the row precharge time is hidden during access to the last data output element.
With the read performed to completion, a precharge command issued at the optimal time (as described above) provides the same operation as a read burst with auto-precharge enabled. The disadvantage of the precharge command is that it requires the command and address busses to be available at the appropriate time to issue commands. The advantage of the precharge command is that it can be used to truncate the pulse.
Burst Termination for Reads The burst termination command is used to truncate read bursts (disable automatic precharge). The most recently registered read command before the burst termination command will be truncated. Note that the sudden termination order is not specific to the bank.
This command should not be used to terminate write pulses.
write
The write command is used to initiate a burst write access to the active row, the burst length is set in the mode register. ba0 and ba1 select the bank, and the address input selects the starting column position. The value of A10 determines whether to use automatic pre-charging. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses.
Write command basically writes timing parameters
The basic write timing parameters for the DQ are shown in the figure below; they apply to all write operations.
Input data appearing on the data bus is written to the memory array, depending on the dm input logic level consistent with the data. If a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data input will be ignored and no write will be performed for that byte/column location enter.
Write burst (min and max TDQ)
During a write burst, the first valid data in element will be registered on the first rising edge of the dqs following the write command, and subsequent data elements will be registered on successive edges of the dqs. The low state of the dqs between the write command and the first rising edge is called the write preamble, and the low state on the dqs after the last data in the element is called the post-write amble.
The time between the write command and the first corresponding rising edge of dqs (tdqs) is specified with a relatively wide range, ranging from 75% to 125% of the clock period. The figure below shows the two extremes of TDQ for 4 bursts, at the completion of the burst, assuming no other commands are initiated, DQ will remain high-Z and any additional incoming data will be ignored.
Data from write to write for any write burst can be concatenated or truncated with subsequent write commands. In both cases, a continuous flow of input data can be maintained. A new write command can be issued on any positive edge of the clock following the previous write command.
The first data input element in a new burst should be applied after the last element of the completed burst or the last required data element of a truncated longer burst. A new write command should be issued x cycles after the first write command, where x is equal to the desired number of data in the pair of elements.
Cascading Write Bursts Discontinuous Write Pulses An example of a discontinuous write burst is shown in the figure below.
A random write cycle can perform full-speed random write accesses in one or more pages, as shown in the following figure.
Reads and writes of any write burst can be followed by subsequent read commands.
Non-interrupted read and write To track write operations without truncating write bursts, it should meet the requirements of twtr, as shown in the following figure.
Interrupt read and write As shown in the figure below, any write burst data can be truncated by subsequent read commands. Note that paired data registered before a twtr cycle will only be written to the internal array, any subsequent data in must be masked with DM.
Write Precharge After any write burst of data, subsequent precharge commands can be issued to the same bank (provided that auto-precharge is not activated). In order to track write operations without truncating write bursts, the requirements of twr should be met, as shown in the following figure.
Uninterrupted Precharge Writes Interrupted Precharge Data written to any write burst can be truncated by subsequent precharge commands, as shown in the figure below. Note that only paired data registered before the twr cycle will be written to the internal array, any subsequent data in should be masked with dm as shown. After a precharge command, no subsequent commands can be issued to the same bank until the TRP is satisfied.
Precharge The precharge command is used to deactivate open lines in a specific bank or open lines in all banks. The bank will be accessible to subsequent lines for a specified time (trp) after the precharge command is issued.
Enter a10 to decide whether to precharge one or all banks. If only one bank is to be precharged, enter ba0, ba1 to select the bank. Otherwise, ba0, ba1 are treated as "don't care".
Once the bank is precharged, it is idle and must be activated before issuing any read or write commands. If there is no open row in that row, or if a previously opened row is already in the process of precharging, the precharge command will be treated as a NOP.
Precharge Command Auto Precharge Auto Precharge is a function that performs the same single battery pack precharge function described above, but does not require an explicit command. This is achieved by using A10 (A10 = high) to enable automatic precharge in conjunction with a specific read or write command. Precharging of the bank/row addressed with the read or write command is performed automatically upon completion of a read or write burst. Auto precharge is non-persistent as it can be enabled or disabled for each individual read or write command.
Automatic precharge ensures that precharge starts at the earliest valid stage within the burst. The user must not issue another order to the same bank until the pre-shared time (trp) is complete. This is as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operations section of this specification.
refresh request
lpddr sdram devices need to flush all rows within any scrolling 64ms interval. Each refresh is generated in one of two ways: by an explicit auto-refresh command, or by an internal timed event in self-refresh mode. Dividing the number of device rows by the rolling 64ms interval defines the average refresh interval (trefi), which is a guideline for the controller to do distributed refresh timing.
Auto-refresh uses the auto-refresh command during normal operation of the lpddr sdram. This command is non-persistent, so it must be issued each time a refresh is required.
Refresh addressing is generated by the internal refresh controller. The lpddr sdram needs to execute the auto refresh command at the average period interval of the trefi.
Auto-refresh command The self-recommended self-refresh command can be used to retain data in lpddr sdram even when the rest of the system is powered off. When in self-refresh mode, the lpddr sdram retains data without external clocking. The lpddr sdram device has a built-in timer to accommodate self-refresh operations. The self-refresh command starts in a similar way to the auto-refresh command, except that CKE is low. Input signals other than CKE are "don't care" during self-refresh. The user can stop the external clock one clock after registering the self-refresh command.
After command registration, CKE must be held low to keep the device in self-refresh mode. During self-refresh operation, the clock is disabled internally to save power. The minimum time a device must remain in self-refresh mode is trfc.
Exiting the self-refresh process requires a series of commands. First, the clock must be stable, before CKE goes high. Once a self-refresh exit is registered, a delay of at least TXS must be met before a valid command is issued to the device to allow any ongoing internal refresh to complete.
The use of self-refresh mode introduces the possibility that internal timed refresh events may be missed when CKE exits from self-refresh mode. When exiting self-refresh, an additional auto-refresh command is recommended.
In self-refresh mode, there is an additional power-saving option: Partial Array Self-Refresh (PASR); it is described in the Extended Mode Registers section.
Self Refresh Commands Back to Back Auto Refresh Cycle Self Refresh Entry and Exit
Power down Enters a shutdown state (no access is possible) when CKE is registered low. This mode is called pre-charge power-down if power is lost when all banks are idle, and active power-down if power is lost when one row is active in any bank.
Input power down will disable the input and output buffers, excluding ck, ck, and gram. In power down mode, CKE must be kept low and all other input signals are "don't care". The minimum power-off duration is specified by TCKE. However, the shutdown time is limited by the device refresh requirement.
When the CKE register is high (accompanied by a NOP or DESECUCED command), the power-down state exits synchronously. A valid command can apply TXP after power off.
For clock stop in power-down mode, see the clock stop subsection in this specification.
Power-off entry and Exit
Deep Power Down The deep power down (DPD) mode enables very low standby current. In this mode, all internal voltage generators inside LPDDR SDRAM will be stopped and all memory data will be lost. All information in the mode register and extended mode register will be lost.
A deep power-down was entered using the Burst Terminate command, but CKE was registered low. All banks must be idle with no activity on the data bus before entering DPD mode. In this state, CKE must be held in a constant low state.
To exit DPD mode, after clock stabilization, CKE is taken high and the NoP command must be held for at least 200µs. After 200 μs, a full reinitialization is required after steps 4 to 11 as defined by the initialization sequence.
Deep in Power and Exit

Clock Stop Stopping the clock during idle periods is an effective way to reduce power consumption.
The lpddr sdram supports clock stop in the following cases:
l The last command (activate, read, write, precharge, auto-refresh, or mode register set) has been executed to completion, including any data output during the read burst; the number of clock pulses per access command depends on the device The AC timing parameters and clock frequency of ; l have met the relevant timing conditions (trcd, twr, trp, trfc, tmrd);
l CKE is held high When all conditions are met, the device is in the "idle state" or "line active state", and the clock stop mode can enter the high hold while CK is kept low and CK is held high.
Clock stop mode is exited by restarting the clock. At least one nop command must be issued before the next access command is applied. Depending on system characteristics, additional clock pulses may be required.
The following figure shows the entry and exit of clock stop mode.
l Initially the device is in clock stop mode
l Clock restarts with rising edge of t0 and nop on command input
l For T1, a valid access command is latched; this command is followed by a NOP command to allow the clock to stop when the access command completes
l tn is the last clock pulse required for an access command locked with t1
l Clock can stop clock stop mode entry and Exit after tn