Differential interface application

Dual operation amplifier and four transportation amplifiers are particularly suitable for applications from differential input to differential output. Usually, these computing amplifiers can be divided into ADC input interfaces or line drive applications. The two basic methods of differential I/O are no reversal or reversal configuration. Because the output is different, the polarity of the signal is a bit meaningless. The irreversible term here is suitable for the place where the input is introduced into OPA4830. Pros and cons. Figure 80 shows the basic starting point for non -conversion differential I/O applications.

This method provides a source impedance independent of signal gain. For example, a simple differential filter can be included in the signal path until non -reversing input without interacting with the amplifier. Figure 80's differential signal gain is shown in the same formula 6:

Figure 80 shows the recommended value of 750 However, you can use RG resistors to adjust the gain.

Various combinations of single power supply or AC coupling gain can also be implemented using the basic circuit of Figure 80. Two non -switching -to -input bias bias voltage is transmitted to the output end at a gain of 1V/V, because the equal DC voltage on each inverter node will not generate current through RG, so that the co -mode of the output terminal will be The gain is 1.

FIG. 81 shows the differential I/O of the inverter amplifier. In this case, the gain resistance (RG) becomes the input resistance of the power supply. This configuration provides a better noise performance than no reversal configuration, but it limits the flexibility of separating the input impedance from the gain.

Two non -conversion inputs provide a simple co -mode control input. If the power supply is coupled by a block or a transformer, this control is particularly useful. In any case, the gain of the co -mode input voltage on the two non -conversion input terminals to the output end is 1, thereby providing a simple co -mode control for the single power operation. The input resistance can be adjusted to the expected gain, but it can also change the input impedance. The micro -score gain of the circuit is shown in the same formula 7:

DC coupling single difference division conversion

The previous differential output circuit was set to receive differential input and input and Provide differential output. FIG. 82 illustrates a method of independent output co -mode control that provides a single difference conversion, DC coupling, and an independent output co -mode control using the four -way computing amplifier.

The circuit of FIG. 82 provides several useful features to isolate the input signal from the final output. Using the first amplifier as a simple non -conversion level, it can also be adjusted independently of the R -class. I (set the source load), and the gain can be easily adjusted at this stage to easily adjust the resistor's next stage to allow the setting of separate output co -mold levels. The required output co -mode voltage VCM is cut into two halves and is applied to the second -level non -rotated input. The gain of the signal path in this class is -1V/V, and the gain of the voltage of (1/2 × VCM) is+2V/V. The output of the second level is the reverse signal of the original co -modular voltage plus the first -level output. The second -level output appears directly at the irreversible end output. The inverse output -level inverter node is also biased towards the co -mode voltage, which is equivalent to the co -mode voltage that appears at the second stage of the output. The current is not generated and the required VCM is also placed on the output end of the stage.

Low power consumption, differential input/output, fourth -order active filter

OPA4830 can provide very effective effects for source filters, Gain block. The fourth -order differential filter itself is very suitable for the design of the active filter. When the filter topology finds a simple gain function to implement the filter, in the design, it is best to use an unreal configuration to isolate the filter element and gain element. For 10MHz, the fourth -order Batworth low -pass SALLEN key filter, see Figure 83. The design puts the high Q level at the first level to allow low Q level to reduce the peak noise at the first level. The resistor value has been slightly adjusted to consider the delay of the amplifier group.

Although the circuit is bipolar, using ± 5V power supply can easily adapt to the single power operation. This configuration adds two real zero points to the response to convert the circuit into a band. The frequency response of the filter in FIG. 84 is shown in Figure 84.

Dual -channel differential ADC driver

When a low noise, single power supply, differential input+5V ADC interface, the circuit in Figure 85 can be dual High -performance ADC provides high dynamic range and medium gain interface. The circuit in FIG. 85 uses two amplifiers in the differential inverter configuration. The co -mode voltage is set on the non -conversion input of the middle scale of the power supply. In this example, it is coupled to the transformer through an input end 1: 2. This design not only provides a signal gain, a single difference between a single difference, but also reduces the noise coefficient. To display 50 input impedance at the input terminal, two 200 resistors are required on the transformer. These two resistors are also amplifiers gain components. Because the same DC voltage appears on the two inverter nodes in FIG. 85, there is no DC current flow over the transformer, so that the output of the common modulus voltage VCM has a DC gain of 1.

The circuit of FIG. 85 is particularly suitable for the middle resolution dual ADC sampling of I/Q. If a higher dynamic range is required, you can add optional 500 #8486 on each amplifier output; ground resistance; ground resistance; ground resistance; ground resistance; ground resistance; ground resistance; ground resistance; In order to increase the distortion of the second and third harmonics, gt; 15db.

If necessary, increase the output level of 5mA can significantly improve linearity. For this balance differential design, the two measured twoThe second harmonic distortion is always lower than the three harmonics. If there is no ground in the signal pathway at the low level signal of the transformer input end, this is particularly helpful for this low -power design. Two drop -down resistors do display signal path grounding, which should be connected at the same physical point to eliminate unbalanced ground circuit currents, thereby reducing secondary harmonic distortion.

Video cable driver

Most video distribution system design has 75 series resistors to drive the matching 75 cable. In order to match the net gain of 1 to 75 match the load, the amplifier is usually set to the voltage gain of+2V/V, and compensate the cable at any end and connect the parallel 75

If all the reference values u200bu200bof 50 the resistance of the resistor are replaced by 75 then the circuit in Figure 72 is suitable for this requirement. Generally, the amplifier gain further increases to 2.2, which restores the additional DC loss of the typical long cable line. This change requires that the gain resistor (RG) in Figure 72 decreases from 750 to 625 . In these two cases, OPA4830's gain flat and differential gain/phase performance provides excellent results in video distribution applications. Differential gain and phase measurement of color sub -carrier frequency (3.58MHz in the NTSC system) compared to the overall small signal gain and changes in phase of the phase signal gain and changes in the phase of the large signal output level (representing the brightness information in the composite video signal). OPA4830 In the standard brightness range of a single matching video cable 150 under the load of the positive video (negative synchronization) signal, the differential gain/phase error displayed by the display is less than 0.07%/0.17 °. For multiple video signals, similar performances can be observed (see Figure 86).

4 -channel DAC interoperability

High -frequency modulus converter (DAC) requires a low -disturbed output amplifier to keep the SFDR in the SFDR in Performance in actual load. Figure 87 illustrates the implementation of the single -end output drive. In this circuit, only one side of the complementary output drive signal is used. The figure shows the signal output current connected to OPA4830. The OPA4830 is set to a cross-resistant or I-V converter. DAC's unused current output grounding. If the DAC requires its output to be connected to a non -connected compliance voltage, the appropriate voltage level can be applied to the non -conversion input terminal of OPA4830.

The DC gain of this circuit is equal to radio frequency. At high frequency, the DAC output capacitor (CD) generates zero in the noise gain of OPA4830, which may cause the peak of the closed -loop frequency response. Add CF to the RF to compensate for the peak of noise gain. In order to achieve a flat cross -resistance frequency response,The pole point in the feedback network should be set to:

The corner frequency F -3DB is about:

Design Tools

Demonstration fixed device

Print circuit board (PCB) can help the use of OPA4830 preliminary assessment of circuit performance. The fixture provides free PCB for free PCB and has a user guide. The summary information of this device is shown in Table 2.

Demonstration fixture can be requested on the Texas instrument website to obtain through the OPA4830 product folder.

Macro models and applications support

Computer simulation of OPA4830 and its circuits with SPICE software is a fast method design to analyze OPA4830 and its circuit performance. This method is particularly suitable for video and radio frequency amplifiers. Among them, parasitic capacitors and inductors play a main role in the performance of the circuit. The Spice model about OPA4830 can be obtained through the Ti webpage. Please note that this model is an OPA830 model applied to the OPA4830 Quad version. The application department can also provide design assistance. These models predict typical small signal communication, transient jump, DC performance and noise under various working conditions. The model includes noise items in the electrical specifications of the data meter. This model does not try to distinguish the small signal communication performance of the packaging type.

Operation suggestion

Optimized resistance value

Since OPA4830 is a stable voltage feedback amplifier with a stable unit gain, feedback and gain setting resistors can use a wide range of resistors with wide range of resistors. value. The main limitations of these values u200bu200bare set by dynamic range (noise and distortion) and parasitic capacitors. Direct feedback is applied to non -vertical integration.

When it is lower than 200 the feedback network will generate additional output loads, which will reduce the harmonic distortion performance of OPA4830. When it is higher than 1K at the time, the typical parasitic capacitance (about 0.2pf) on the feedback resistance may cause the non -due frequent band restrictions in the amplifier response.

A good rule of experience is to set the parallel combination of RF and RG (see Figure 74) to less than 400 . The combination impedance RF | | RG interacts with inverter input capacitors, adding a pole to the feedback network, so that the positive response is zero. Assuming the parasitic 2PF on the reverse node, keep RF | | RG LT; 400 it can keep the pole above 200MHz. As far as it is concerned, this constraint means that the feedback resistance RF can increase to several K under high gain. As long as the parasitic capacitance formed by RF formation is not interested in the frequency of interestWithin the range, this increase is acceptable.

In the reverse configuration, you must pay attention to the additional design considerations. RG becomes the input resistance, so it becomes a load impedance of the driver source. If the impedance match is required, the RG can be set to the required terminal value. However, at low reverse gains, the feedback resistance value generated can provide an important load for the amplifier output. For example, if the inverter gain is 2 and the input matching resistance is 50 (u003d rg), a feedback resistor of 100 this will help the output load connect with the external load. In this case, it is best to increase the RF and RG values u200bu200bat the same time, and then use the third ground resistance to input matching impedance (see Figure 88). The total input impedance becomes a parallel combination of RG and an additional parallel resistor.

Bandwidth and gain:

irreversible operation

With the increase of signal gain, the closed -loop bandwidth of the voltage feedback of the op amp gradually decreased. Theoretically, this relationship is described by the gain bandwidth (GBP) shown in the figure to describe the electrical characteristics. Ideally, in addition to GBP, in addition to the gain without reversing signal (also known as noise gain, or NG), a closed -loop bandwidth can be predicted. In practice, this calculation is established only when the phase's badness is close to 90 °, just like in a high -gain configuration. In low -gain (increase feedback factors), most amplifiers show more complicated response and lower phase habits. The OPA4830 was compensated, and a minor peak response was given under the non -reversible gain of 2V/V (see Figure 74). This compensation makes the typical gain of 110MHz is+2V/V bandwidth, which far exceeds the gain with 110MHz GBP divided by 2V/V. Increasing gain can make the phase margin close to 90 °, and the bandwidth is closer to the predicted value (GBP/NG). When the gain is+10V/V, the 11MHz bandwidth shown in the electrical characteristics is consistent with the bandwidth of the simple formula and the typical GBP forecast of 110MHz.

The frequency response of the gain to+2V/V can achieve a special flatness by increasing the noise gain to 3V/V. Without affecting the+2V/V signal gain, one method is to add a 2.55k #8486 to the two input terminals (see Figure 78). In the application of unit gain (voltage follower), similar technologies can be used to reduce peak values. For example, by using a 750 feedback resistor and a 750 resistor at the input terminal of the two computing amplifiers, the voltage follower response is similar to the+2V/V response gain in FIG. 73. Due to the increase in noise gain, the resistance value of the input end of the op amp was further suppressed to further suppress the frequency response. Compared with ± 5V, OPA4830 shows the minimum bandwidth decrease when working in a single power supply (+5V). This minimum reduction is because the total power supply voltage of the internal bias control circuit between the power pins maintains almost constant static current.

Reverse amplifier operation

All familiar computing amplifiers application circuits can be provided to the designer with OPA4830. FIG. 88 is a typical inverse configuration. The input/output impedance and signal gain in FIG. 72 retains the configuration in the inverter circuit. Reversal operation is one of the more common requirements, and it provides some performance advantages. It also allows input to bias to VS/2 without any net empty problem. The output voltage of the electric container or capacitor can be adjusted independently within the output voltage range.

In the reverse configuration, you must pay attention to three key design considerations. First of all, the gain resistance (RG) becomes part of the input impedance of the signal channel. If you need to input impedance matching (when the signal is coupled with cables, twisted wiring, long PCB trace lines, or other transmission wire conductors, this is beneficial), you can set RG to The required gain. This method is the simplest method to get the best bandwidth and noise performance.

However, at low reverse gains, the feedback resistance value generated can provide an important load for the amplifier output. For the reverse gain to 2, set RG to 50 for input matching, no RM, but 100 feedback resistance. This structure has an interesting advantage, that is, for 50Ω source impedance, noise gain is equal to 2, which is the same as the non -conversion circuit considered above. The amplifier output is now seeing 100 the feedback resistance is connected in parallel with the external load. Generally, the feedback resistance should be limited to the range of 200 to 1.5k In this case, it is best to increase the RF and RG values, as shown in Figure 88, and then use the third resistor (RM) ground to achieve the input matching impedance. The total input impedance becomes a parallel combination of RG and RM.

The second main consideration mentioned in the previous paragraph is that signal source impedance becomes part of the noise gain equation, which affects the bandwidth. For the examples in FIG. 88, the RM value is combined with the external 50 source impedance (under high frequency) to generate 50 | | 57.6 u003d 26.8 This impedance is connected in series with RG to calculate noise gain. For Figure 88, the noise gain generated is 2.87, and if the RM can be eliminated as mentioned above, only 2. Therefore, the bandwidth (NG u003d+2.87) of the circuit with the gain in FIG. 88 is lower than the bandwidth of the gain +2 circuit in Figure 72.

The third important consideration in the design of the inverter amplifier design is to set the bias current to offset the resistor (RT u003d 750 parallel combination) in the non -transient input terminal. If the resistance is set to the total DC resistance from the inverter node, the output DC error (because the input bias current) is reducedSmall (input offset current) multiplied by RF. In the figure, the impedance of a capacitor with an impedance of 88Ω in the figure is 88Ω. In order to reduce the additional high -frequency noise introduced by resistance and power feedback, RT is bypass the capacitor.

Output current and voltage

OPA4830 provides excellent output voltage capacity. For the+5V power supply, under the air load conditions of+25 ° C, the output voltage is usually less than 90mV compared to the Renyi Electric Source Rail.

The minimum output voltage and current specifications are set at the coldest temperature limit through the worst case. Only when the cold starts, the output current and voltage will be reduced to the value shown in the specification table. When the output transistor provides power, the knot temperature increases, reducing the VBE (increasing the effective output voltage swing) and increasing the current gain (increasing the available output current). In the steady -state operation, the output voltage and current that available output voltage and current are greater than the value shown in the ultra -temperature specification because the output -level knot temperature is higher than the lowest specified.

In order to maintain the maximum output level linearity, it does not provide short -circuit protection. This lack of protection is usually not a problem, because most applications include a series matching resistor on the output end. If the output end of the resistor is short -circuited, the internal power consumption is limited. However, in most cases, the output pins are directly connected to the adjacent positive power supply foot (8 pins packaging), which will destroy the amplifier. If you need additional short -circuit protection, consider a small string of connected resistors in the power cord. This resistance reduces the available output voltage under high output load.

Drive capacitance load

For the operational amplifier, the most demanding and most common load conditions are the capacitor load. Generally, the capacitance load is an additional external capacitance that is recommended to improve the linearity of ADC. When the capacitance load is directly applied to the output pin, the high -speed and high -open ring gain bleach (such as OPA4830) is easily affected by the decrease in stability and the peak of closed -loop response. When the frequency response is flat, the pulse response and/or distortion are mainly considered, the simplest and most effective solution is to output and capacitance load at the amplifier.

The typical feature shows the recommended RS and the frequency response generated by the RS and capacitance loads and the frequency generated under the load. Parasitic capacitance load greater than 2PF will begin to reduce the performance of OPA4830. Long PCB trajectory, non -matching cables, and connections to multiple devices can easily exceed this value. Always consider this impact carefully, and add a recommended series resistor (see the circuit board layout guide) as close as possible to the output pins.

The standard for setting the RS resistor is the maximum bandwidth and flat frequency response at the load. When the gain is +2, the frequency response at the output pins has slightly reached its peak without a capacitance load, and a relatively high RS value is required to flatten the response under flat load. Increasing noise gain will also reduce peaksValue (see Figure 78).

distortion performance

OPA4830 has good distortion performance under 150Ω load. Compared with other solutions, it provides excellent performance on lighter load and/or on single+3V power supply. Generally, before the base wave signal reaches a very high frequency or power level, the second harmonic is dominant, and the three harmonic components can be ignored. Then focus on the second harmonic to increase the load impedance directly to improve the distortion. Keep in mind that the total load includes the feedback network; in the non -reversing configuration (see Figure 74), this is the sum of RF+RG, and in the reverse configuration, you only need to connect the RF with the actual load. Running differential inhibition of secondary harmonics is shown in the typical characteristics of differentials.

Noise performance

High conversion rate, stable unit gain, voltage feedback computing amplifier usually achieve conversion rate at the cost of high input noise voltage. However, the 9.2NV/√Hz input voltage noise of OPA4830 is much lower than that of similar amplifiers. The input voltage noise is combined with the two input reference current noise items, which can provide low output noise under various working conditions. Figure 89 shows the noise analysis model containing all noise items. In this model, all noise items are considered noise voltage or current density items, and the unit is NV/√Hz or PA/√Hz.

The total output spots noise voltage can be calculated as a square root of all square output noise voltage contributors. Formula 8 shows the general form of the output noise voltage shown in FIG. 89:

Divide this expression with noise gain [ng u003d (1+rf/ 方/ RG)] That is the equivalent input reference point noise voltage when the input is not input; the result is shown in the equal form 9:

The total output point noise voltage of the total output point of the total output point and the total output point of 9.65nv/√Hz and the total output point noise voltage of 9.65NV/√Hz are evaluated. This value includes noise in the resistor. This SPNOISE voltage that enters a reference is not much higher than the 9.2NV/√Hz specifications of 9.2NV/√Hz of only computing amplifier voltage noise.

DC accuracy and offset control

The balance input stage of broadband voltage feedback amplifier allows good DC output accuracy in various applications. Compared with similar products, the power current of OPA4830 provides stricter control. Although a relatively high input bias current requires a high -speed input level (usually the input bias current of each input terminal is 5μA), the close match between them can be used to reduce the output DC error caused by the current. This reduction is achieved by matching the DC source resistance that appears at two inputsof. Use the worst case+25 ° C input offset voltage and current specifications, evaluate the configuration of Figure 74 (its matched DC input resistance), and obtain the output offset voltage in the worst case equal to equal formula 10:

Generally, you need to fine -tune the output offset or DC working point adjustment. There are many technologies to introduce DC offset control in the computing amplifier circuit. Most of these technologies are based on increasing DC current resistance through feedback. When the inch selection of the mitigation method, a key consideration is the effect on the frequency response of the expectation signal path. If the signal path is non -reversible, it is best to use offset control as inversion and signal applications to avoid interaction with the signal source. If the signal path is reversed, you can consider the offset control of the input application of non -turbulent input. The DC bias current is introduced into the inverter input node by the resistance value of much significant channel resistance. This configuration ensures that the regulatory circuit has the least effect on the width gain and frequency response.

Thermal analysis

Maximum expected maximum internal power consumption allowed, as described below. In any case, the highest knot temperature must not exceed+150 ° C.

The working knot temperature (TJ) is given by TA+PD θJa. The total internal power consumption (PD) is the sum of the additional power consumed by static power (PDQ) and output (PDL). Just multiply the total voltage of the power supply to the non -load part. PDL depends on the required output signals and loads; however, for the resistance load connected to the intermediate power supply (VS/2), when the output is fixed at a voltage equal to VS/4 or 3VS/4, the PDL is at the maximum value. In this case, PDL u003d VS2 (16 × RL), where RL includes feedback network load.

It determines that it is dispersed at the power level, not the power level.

As the worst case, the maximum TJ is calculated using the OPA4830 (TSSOP-14 package) in Figure 72. Drive 150 load.

Although the value is still far lower than the highest prescribed temperature, due to system reliability considerations, a lower guarantee temperature may be required. If the load is required to enter the output end under high output voltage, or obtain an current from the output end at a low output voltage, the highest internal loss may occur. This allows high current through a large internal voltage drop in the output transistor.

Circuit plate layout guide

To obtain the best performance and high -frequency amplifier, such as OPA4830 needs to pay close attention to the plate layout parasitic and external component types. Suggestions for optimization include:

A), minimize parasitic capacitance all signal input/output pins. Output and reverse input terminalParasitic capacitors will cause unstable: at non -switching input terminals, it will react with source impedance, resulting in unintentional bandwidth restrictions. In order to reduce unnecessary capacitors, a window should be opened on all the ground and power plane around the signal I/O pins. Otherwise, the ground and power aircraft should remain complete elsewhere.

B), minimize the distance between the power pins and the high frequency 0.1 μF decoupling capacitor ( lt; 0.25 "") to the minimum. At the equipment pins, the ground layout of the grounding and power supply should not be close to the signal Input/output pins. Avoid narrow power and ground marks to minimize the inductance between the pin and the decoupled capacitor. Each power connection should always be disconnected with one of the capacitors. The options between the two power supply should be available. Power -coupled capacitor (0.1 μF) (for bipolar operations) can improve the second harmonic distortion performance. The main power supply should also use larger (2.2 μF to 6.8 μF) decoupled capacitor, at a lower frequency Effective. These can be placed in a slightly far away from the device and can be shared between multiple devices in the same area of u200bu200bPCB.

C), carefully select and place external components to maintain high frequency performance to maintain high frequency performance . The resistor should be a very low type of electricity resistance. The surface sticker is the best work and allows more compact overall layout. Metal film or carbon component axial binding resistor can also provide good high -frequency performance. Similarly, maintain the leading leader With the PCB trajectory as short as possible. Do not use a wire winding resistor in high -frequency applications. Because the output tube foot and inverter input tube foot are the most sensitive to the parasitic capacitance, the feedback and series output resistance are always exhausted (if there is) exhaustion) It may be close to the output pipe foot. Other network components, such as non -converting input terminal connection resistors, should also be placed near the package. If double -sided elements are allowed to install, the feedback resistor is placed directly on the other side of the circuit board below the package below the package below the packaging board. , Between the output and reverse input pins. Even if the low -parasitic capacitor is diverted in the external resistance, the high resistance value will generate significant time constant, thereby reducing the performance. There are about 0.2pf when the resistor is connected in parallel. For resistance gt; 1.5k , the parasitic capacitor will add one pole and/or zero below 500MHz, which will affect the circuit operation. Keep the resistance value as low as possible to meet the load load Driven consideration. 750 is a typical feedback starting point.

D), the connection with other broadband devices on the board can be performed through a short direct re