Features and Benefits

±750mA, 30V output rating; Satlington® sink driver; automatic current decay mode detection/selection; 3.0 to 5.5 V logic supply voltage range; mixed, fast and slow current decay modes; internal UVLO and thermal shutdown circuitry; Cross current protection.

illustrate

The A3967 is a complete microstepper motor driver with built-in translation. It is designed to operate bipolar stepper motors in full, half, fourth and eighth order modes with an output drive capability of 30V and ±750MA. The a3967 includes a fixed off-time current regulator capable of operating in slow, fast or mixed current decay modes. This current decay control scheme can reduce the audible noise of the motor, improve step accuracy, and reduce power consumption.

Translation is the key to the ease of implementation of the A3967. By simply putting a pulse on the step input, the motor will perform a step (full, half, quarter or eighth depending on the two logic inputs). There are no phase sequence tables, high frequency control lines or complex programming interfaces. The a3967 interface is ideal for applications where complex µPs are unavailable or overburdened.

Internal circuit protection includes hysteretic thermal shutdown, undervoltage lockout (uvlo), and crossover overcurrent protection. No special power-up sequence is required.

The A3967 features a 24-pin SOIC, 100% matte tin plated lead frame, and is lead free. Four pins are internally fused to enhance heat dissipation. The pins are at ground potential and do not require isolation.

Function description

The A3967 is a complete microstepper motor driver with built-in translation for easy operation and minimal control lines. It is designed to operate bipolar stepper motors in full-step, half-step, four-step and eight-step modes. The current in each of the two output full bridges is regulated by a fixed-time pulse width modulation (pwm) control circuit. The full-bridge current for each step is set by the value of the external current sense resistor (RS), the reference voltage (VREF), and the DACS output voltage controlled by the converter output.

On power-up or reset, the converter sets the DAC and phase current polarity to the initial initial state (see the initial state conditions diagram), and sets the two-phase current regulator to mixed decay mode. When a step command signal appears on the step input, the converter automatically sequences the DAC to the next stage (see Table 2 for current stage order and current polarity). The microstep resolution is set by the inputs ms1 and ms2, as shown in Table 1. If the new DAC output level is lower than the previous level, the decay mode of that full bridge will be set by the pfd input (fast, slow or mixed decay). If the new dac level is higher than or equal to the previous level, the decay mode of the full bridge will be slow decay. This automatic current decay selection will improve microstepping performance by reducing current waveform distortion caused by motor BEMF.

Reset input (reset). The reset input (active low) sets the converter to a predefined master state (see master state conditions diagram) and turns off all outputs. The step input is ignored until the reset input goes high.

Step input (step). A low-to-high transition step input puts the translator in sequence and advances the motor by one increment. The converter controls the input to the DAC and the direction of current flow in each winding. The size of the increment is determined by the state of the inputs ms1 and ms2 (see Table 1).

Microstep selection (ms1 and ms2). Input terminals ms1 and ms2 select the microstep format according to Table 1. Changes to these inputs remain until the STEP command takes effect (see figure).

Direction Input (DIR). The state of the direction input will determine the direction of rotation of the motor.

Internal PWM current control. Each full bridge is controlled by a fixed off-time pwm current control circuit that limits the load current to the desired value (itrip). Initially, a pair of diagonal source and sink outputs are enabled and current flows through the motor windings and RS. When the voltage on the current sense resistor equals the DAC output voltage, the current sense comparator resets the PWM latch, turning off the source driver (slow decay mode) or the sink and source drivers (fast decay mode or mixed decay mode) . The maximum value of the current limit is achieved by selecting the voltages at the RS and VRF inputs, and the transconductance function is approximated by:

The DAC output reduces the VREF output to the current sense comparator in precise steps (see Table 2 for %ITRIMPax for each step).

fixed rest periods. An internal PWM current control circuit uses one trigger to control how long the driver remains off. The primary off-time toff depends on the choice of external resistor (rt) and capacitor (ct) connections from the rc timing terminal to ground. The off time, over the range of CT = 470 pF to 1500 pF and rT = 12 KΩ to 100 KΩ, is approximately:

Reinforced concrete cutting. In addition to the fixed off-time PWM control circuit, the ct element sets the blanking time of the comparator. This function will blank the output of the current sense comparator when the internal current control circuit switches the output. The comparator output is shielded to prevent false overcurrent detection due to reverse recovery current of the clamp diode and/or switching transients related to load capacitance. Blank time can be approximated as:

Enable input (enable). This low input activates all outputs. When logic high, the output is disabled. The inputs of the converter (step, direction, ms1, ms2) are all active regardless of the enable input state.

closure. In the event of a fault (excessive junction temperature), the output of the device will be disabled until the fault condition is removed. At power-up, if VCC is low, an under-voltage lockout (UVLO) circuit disables the driver and resets the converter to its initial state.

Fast decay input percentage (pfd). When the step input signal commands a lower output current from the previous step, it switches the output current decay to slow, fast or mixed decay according to the voltage level of the pfd input. If the voltage at the pfd input is greater than 0.6vcc, the slow decay mode is selected. If the voltage on the pfd input is less than 0.21vcc, the fast decay mode is selected. Mixed decay is somewhere in between these two levels.

Mixed decay operations. If the voltage at the pfd input is between 0.6vcc and 0.21vcc, the bridge will operate in mixed decay mode according to the step sequence (see diagram). When the trigger point is reached, the device will enter a fast decay mode until the voltage on the RC terminal decays to the voltage applied to the PFD terminal. The time that the device operates in rapid decay is approximately:

After this fast decay portion tfd, the device will switch to slow decay mode for the remainder of the fixed off period.

Sleep mode (sleep). An effective low control input to minimize power consumption when not in use. This disables most of the internal circuitry, including the output. A logic high allows the device to function and start normally in its initial position.

a. Minimum command activation time before step pulse (data set time)... 200 ns

b. After the minimum command activation time step pulse (data hold time) ...... 200 ns

c. Minimum step pulse width…………1.0μs

d. Minimum step low time…………1.0μs

E. Maximum wake-up time………… 1.0 ms

layout. Printed wiring boards should use heavy duty ground planes. For best electrical and thermal performance, the driver should be soldered directly to the board.

The load power terminal vbb should be separated from the electrolytic capacitor (recommended greater than 47µf) placed as close as possible to the unit.

To avoid problems due to capacitive coupling of high dv/dt switching transients, move the bridge output traces away from the sensitive logic input traces. Always drive logic inputs with low source impedance for improved noise immunity. A star grounding system close to the driver is recommended. ground.

The 24-wire SOIC has an analog ground and a power ground, which is internally connected to the package's power tabs (wires 6, 7, 18, and 19).

current sensing. To minimize inaccurate sensing of output current levels caused by ground tracking IR drops, the current sense resistor (RS) should have a separate ground return return to the device's star ground. This path should be as short as possible. For low value sense resistors, the IR drop in the traces of the printed circuit board sense resistor is significant and should be considered. Sockets should be avoided as the contact resistance of the sockets can cause variations in RS. Allegro Microsystems recommends:

Thermal Protection. Typically, the circuit shuts down all drivers when the junction temperature reaches 165°C. Its purpose is only to protect the device from faults caused by excessive connection temperature and should not imply that the output is short-circuited. Thermal shutdown has about 15°C hysteresis.

The mixed decay mode is controlled by the fast decay voltage percentage (vpfd). If the voltage at the pfd input is greater than 0.6vcc, the slow decay mode is selected. If the voltage on the pfd input is less than 0.21vcc, the fast decay mode is selected. Mixed decay is somewhere in between these two levels.

The mixed decay mode is controlled by the fast decay voltage percentage (vpfd). If the voltage at the pfd input is greater than 0.6vcc, the slow decay mode is selected. If the voltage on the pfd input is less than 0.21vcc, the fast decay mode is selected. Mixed decay is somewhere in between these two levels.

The mixed decay mode is controlled by the fast decay voltage percentage (vpfd). If the voltage at the pfd input is greater than 0.6vcc, the slow decay mode is selected. If the voltage on the pfd input is less than 0.21vcc, the fast decay mode is selected. Mixed decay is somewhere in between these two levels.