illustrate
The WM8770 is a high performance codec for multi-channel audio devices. The WM8770 is ideal for surround sound processing in home hi-fi, car audio and other audio applications. Stereo 24-bit multi-bit Sigma-Delta ADC with eight stereo channel input selectors. Each channel has analog domain mute and programmable gain controls. 16-32 bit digital audio output word length and supports sample rates from 8kHz to 96kHz. Four stereo 24-bit multi-bit Sigma-Delta DACs with oversampling digital interpolation filters. Digital audio input 16-32 bit word length and 8kHz sample rate support up to 192kHz. Each DAC channel has independent analog volume and mute controls, with a set of input multiplexers allowing the selection of an external 3 channel stereo analog input to these volume controls. Audio data interface supports I2
S, left and right justified to adjust the digital audio format. The device is controlled via a 3-wire serial interface. This interface provides access to all functions including channel selection, volume control, muting, de-emphasis and enhancement management facilities. The device has 64 lines available in TQFP package.
Characteristic Audio Performance
-106dB SNR ('A' weighted @48kHz) DAC
-102dB SNR ('A' weighted @48kHz) ADC
DAC sampling frequency: 8kHz–192kHz
ADC sampling frequency: 8kHz–96kHz
3-Wire SPI or CCB MPU Serial Control Interface Master-Slave Clock Mode Programmable Audio Data Interface Mode - I2 Type S, Left Justified or Right Justified - 16/20/24/32-bit Word Length Four Independent Stereo DAC Outputs Analog and Digital volume control Analog bypass channel feature Six-channel optional auxiliary input for volume control
8 stereo ADC inputs with analog gain from +19dB to -12dB in 1dB steps
2.7V to 5.5V analog, 2.7V to 3.6V digital supply operation
5V Tolerant Digital Input Application Block Diagram

Surround Sound AV Processor and Hi-Fi System Car Audio

Internal power-on reset circuit schematic diagram of internal power-on reset circuit

The WM8770 includes an internal power-on reset circuit to reset the digital logic to its default state after power-on.
Schematic of the internal por circuit. The por circuit is powered by avdd. This circuit monitors DVDD and VMIDADC if DVDD or VMIDADC falls below the minimum threshold vpor_off.
When powered up, the por circuit requires the presence of the avdd to work. porb is asserted low until avdd, dvdd and vmidadc are established. When avdd, dvdd and vmidadc have been established, porb is released high, all registers are in their default state and writing to the digital interface may occur.
On power down, PORB is asserted to the low threshold vpor_off whenever DVDD or VMIDADC falls below the minimum value. If avdd is removed at any time, the internal power-on reset circuit will power down and porb will follow AVDD.
In most applications, the time it takes for the device to release porb high will be determined by the charging time of the vmidadc node.

Typical power-up sequence for DVD to power up before AVDD.

Typical power-up sequence for AVDD to power up before DVD

In practical applications, the designer is unlikely to control AVDD and DVD. Use the por circuit to monitor the vmidadc to make sure the device is ready when power is applied to it.
Typical power-up scenarios in real systems. AVDD and DVD must be established and vmidadc must have reached the threshold vporr before the device is ready to write to. Any writes to the device before the device is ready will be ignored.
The dvdd was powering up before the avdd. In both cases, the time from power-on to device readiness is determined by the time of the vmidadc by the charge.
It is recommended to use 10uf caps on vmidadc for decoupling. The vmidadc's charge time will control how long it takes the device to be ready after powering up. The time required for the vmidadc to reach the threshold is a function of the vmidadc resistor string and decoupling capacitor. The typical equivalent resistance of the resistor string is 50kohm (+/-20%). Assuming a 10uf capacitor, the time it takes for the vmidadc to reach the 1v threshold is about 110ms.

Device Description 1. Introduction is a complete 8-channel DAC, 2-channel DC audio encoder, including digital interpolation and resolution filters, multi-bit sign delta stereo ADC, and switched capacitor multi-bit sign delta on each channel and output smoothing DACS with similar volume control on the filter.
The device is implemented as four discrete stereo DACS and a stereo ADC with flexible inputs.
Multiplexer, in a single package and controlled by a single interface. Four stereo channels can be used to implement a 5.1 channel peripheral system.
A stereo mix download channel for additional stereo channels, or a similar BYPASS path option for a complete 7.1 channel peripheral system is available to allow any 8 stereo analog signals.
Stereo input to stereo output via master volume control. This is purely a similar input to similar output high quality signal path to achieve if desired. This would be Allow, for example, the user to play back a 5.1 channel surround movie through 6 of the DACS, whilst put a divider model or digital signal back into the remote room installation.
Each stereo DAC has its own data input DIN1/word clock is shared and they have their own data output point for the stereo ADC, the word clock. Bitclk and McLKA are shared between the ADCS and DAC. The audio interface can be configured to operate here.
Master or Slavic In Slavic mode ADCLRC, DACLRC and BCLK are all inputs. Master mode ADCLRC, DACLRC and BCLK are all outputs.
The ADC input multiplexer is configured to allow large signal levels to be input to the ADC, using external resistors to reduce large signal amplitudes within the normal operating range OF the ADC. The input PGA also allows input signal gain to +19DB and attenuation down to The present invention allows maximum flexibility for the user using the ADC.
An optional stereo record output is also provided on the DC/R and is considered the DC/R output.
For driving high impedance buffers only.
Each DAC has its own model and separate digital volume controls. Similar volume control adjustable 1DB step and 0.5DB step digital volume control. Analog and digital Volume controls may be operated independently. A zero-crossing detection circuit is added to each DAC for both analog and digital volume controls. The only update of the attenuation value is achieved when the volume-like zero-crossing detection is performed on the input signal to the gain stage.
Close similar to ground level. The digital volume control detects this little click and zipper noise as the gain value changes by zero transitions before refilling the volume plus, 6, the DAC output contains an input selector and mixer to assign an external 6-channel, or 5.1-channel signal, in DAC signal or mixed with DAC signal before volume control. This device can be used as a 6-channel volume control that provides 5.1 type-like inputs externally. The use of external resistors allows maximum input levels to be accepted by the device, giving maximum user flexibility. The control of the internal functions of the device is carried out by the 3-wire serial control interface. Or a CCB type interface can be used, selectable by the CE PIN state on the rising edge of Resetb. The control interface may be asynchronous to the audio data interface, as the control data will be resynchronized to the audio processing
EC, CL, DI and Resetb are 5V controlerant with TTL Input Thresholds, allowing the WM8770 to usedWith DVDD=3.3V and be controlled by a controller with 5V output. Offers systems using 128fs, 192fs, 256fs, 384fs, 512fs or 768fs operation of the clock. Mode selection between Slavic clock rates is automatically controlled. The sample rate ratio is set by the control bits Binder and DACRATE in master clock mode. ADC and DAC may run at different ADC and DACS when the mouse is under the constraints of the normal master. Taking for example a master clock of 24.576MHz, a DAC sample rate of 96KHz (256fs mode) and an ADC sample rate of 48khz (-512fs mode) can be accommadated. master clock. sample rate (.FS) from less than 8ks//s up to provide the proper system clock is input.
Audio data interface supports right, left and i2 interface formats

Audio Data Sampling Rate In a typical digital audio system, only one central clock source generates the reference clock and all audio data processing is synchronized. This clock is often referred to as the master clock of the audio system. The external main system clock can be applied directly through the MCLK input pin without software configuration. For the reference clock in a system with many possible sources, it is recommended to optimize ADC and DAC performance using the clock source with the least jitter.
The main clock of the WM8770 supports DAC and ADC audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (daclrc or adclrc), usually 32khz, 44.1khz, 48khz or 96kHz (DAC also supports 128fs, 192fs and 192kHz sampling rates operation below). The master clock is used to operate the digital filters and noise shaping circuits.
In slave mode, the WM8770 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sample rate (within +/-32 system clocks). If there are more than 32 clock errors, the interface will be disabled and keep outputting the level of the last sample. The master clock must be synchronized with ADCLRC/DACLRC, although the WM8770 can tolerate phase variation or jitter on this clock. A typical masterWM8770 clock frequency input.
The signal processing of the WM8770 typically operates on both the ADC and DAC at an oversampling rate of 128fs. The exception to the dac is operating with a 128/192fs system clock, eg.
For 192kHz operation, the oversampling rate is 64fs. It is recommended that the user set the adcosr bit for ADC operation at 96kHz. This changes the ADC signal processing oversampling rate to 64fs.

Power down mode
The wm8770 has a power down control bit that allows to shut down certain parts of the wm8770 when not in use. The 8-channel input source selector and input buffer may be powered down using control bit ainpd. Switches to buffered vmidadc when AINPD is set to all inputs of the source selector (AIN1L/R to AIN8L/R). Control bits adcpd turn off adc and adc input The four stereo DACs each have a separate power down control bit, DACPD[3:0] allows the individual steteo DACs to be turned off when not in use. The analog output mixer and EVR can also be powered off by setting outpd[3:0]. Output[3:0] also switches the analog output VOUTL/R to VMIDDAC to maintain the DC level on the output. Setting AINPD, ADCPD, DACPD[3:0] Output[3:0] will turn off all references except vmidadc, adcref and vmidDAC. These can be turned off by setting pdwn. Setting pdwn overrides all other power down control bits. It is recommended that the 8-channel input multiplexers and buffers, ADCs, DACs, and output mixers and EVRs be powered down before setting the PDWN. Defaults to all power-down bits to be set, except PDWN.
Power-down control bits allow parts of the device to be powered down when not in use. For example, if only an analog bypass path from AINL/R to VOUTL/R is required, the ADCPD and DACPD[3:0] control bits can be set to power up the analog input and analog output.
Digital Audio Interface Master and Slave Mode The audio interface operates in slave or master mode, selectable using the MS control bits. In master mode and slave mode DACDAT is always the input of WM8770, ADCDAT is always the output. Default is slave mode.
In slave mode (ms=0), ADCLRC, DACLRC and BCLK are inputs to the WM8770.
DIN1/2/3/4, ADCLRC and DACLRC are sampled by the WM8770 on the rising edge of BCLK. The analog-to-digital converter data is output on DOUT and changes on the falling edge of BCLK. The polarity of BCLK can be reversed by setting the control bit bclkinvBCLK so that DIN1/2/3/4, ADCLRC and DACLRC transition sharply on the falling edge of BCLK and on the rising edge of BCLK.

In master mode (ms=1), ADCLRC, DACLRC and BCLK are outputs of WM8770
ADCLRC, DACLRC and BITCLK are generated by WM8770. DIN1/2/3/4 are on the rising edge of BCLK by WM8770, so the controller must output on the falling edge of BCLK. ADCDAT is output on DOUT and changes on the falling edge of BCLK. The polarity of bclk can be reversed by setting control bit bclkinv so that din1/2/3/4 are sampled BCLK falling edge and falling edge change on BCLK rising edge.
Master Mode Audio Interface Format Audio data is applied to the internal DAC filter via digital audio, or from the ADC filter output interface. 3 popular interface formats are supported:
8226 ; Left-aligned mode • Right-aligned mode • I2 class

All 3 formats in S mode send msb first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32-bit right-justified mode.
In left justified, right justified and i2 in S mode, the digital audio interface inputs and outputs ADC data on DOUT on DIN1/2/3/4. The audio data for each stereo channel is time multiplexed with ADCLRC/DACLRC, indicating whether a left or right channel is present.
adclrc/daclrc is also used as a timing reference to indicate the start or end of data.
In left-justified, right-justified, and i2 mode S, the minimum number of BCLK periods per DACLRC/ADCLRC is 2 times the selected word length. ADCLRC/DACLRC must be at least up to a word length of bclks, and a minimum word length of bclks. ADCLRC/DACLRC is acceptable for any mark-to-space ratio above as long as the above requirements are met.

Left-justified mode In left-justified mode, the msb of din1/2/3/4 is the BCLK converted by the wm8770 at DACLRC. The msb of ADC data is output on dout and is the same as ADCLRC on the falling edge of BCLK and can be sampled on the rising edge of BCLK.
ADCLRC and DACLRC are high when sampled on the left and low when sampled on the right.
Left Aligned Mode Timing Diagram

Right-Justified Mode In right-justified mode, the LSBs of DIN1/2/3/4 are sampled by the WM8770 on the rising edge of BCLK before the daclrc transition. The LSB of ADC data is output on DOUT and is available on BCLK on the falling edge of BCLK prior to the ADCLRC conversion. ADCLRC and DACLRC High when Left Sampling and Low Right Sampling Right-Justified Mode Timing Diagram

S mode in I2
In S mode, the most significant bits of DIN1/2/3/4 are sampled by the WM8770 on the second rising edge of BCLK after the daclrc conversion. The msb of ADC data is output on dout and is available on BCLK on the first falling edge of BCLK after ADCLRC conversion. ADCLRC and DACLRC are low when sampled on the left and high when sampled on the right.
S-mode timing diagram

Control interface operation
The WM8770 is used in a three-wire serial interface in an SPI compatible configuration or a CCB (Computer Control Bus) configuration.
The interface is configured by the reset pin. If the CE pin is low on the rising edge of Reset B, the CCB configuration is selected. If CE is high on the rising edge of resetb, the spi compatible configuration is selected.
The control interface allows 5V voltage, which means that when the control interface input signal is CE, CL and DIDVDD is 3V, the input high level is 5V. The input threshold is determined by DVDD.
resetb is also 5v tolerant.