Adjustable Switching Frequency Up to 200 kHz Current Mode Control Soft-Start and Shutdown Control Automatic Burst Mode Operation Standby Conditions Capable of Meeting "Blue Angel" Standards (<1W Total Power Consumption) Internal Trim Nano Reference Low Voltage Lock-in Hysteresis Integrated Startup Power Supply Thermal Protection Low Standby Current Adjustable Current Limit Description
The Viper50-E, manufactured with Vipower M0 technology, combines a state-of-the-art pwm circuit with an optimized, high-performance voltage, vertical power mosfet (620v/1.5a) on the same silicon die.
Typical applications include off-line power secondary power 25W wide range conditions and single range 50W or double configuration. Both are compatible with either primary or secondary regulation loops when compared to discrete solutions. Burst mode operation is an additional feature of this device that provides the ability to operate in standby mode with no additional components.

Pin Description
3.1 Drain pin (integrated power mosfet drain): Integrated power mosfet drain pin. It is turned off during normal operation by integrating a high voltage current source. The device is able to handle unwinding currents during normal operation, ensuring itself against voltage surges, PCB stray inductance and allowing unbuffered operation with low output power.
3.2 Source pin: Power mosfet source pin. Primary side circuit common ground connection.
3.3 VDD pin (power supply):
This pin provides two functions:
●Corresponding to the low voltage power supply of the circuit control part. If VDD is lower than 8V, the startup current source is activated and the output power mosfet is turned off until the VDD voltage reaches 11V . At this stage, the internal current consumption is reduced, the VDD pin draws about 2 mA, and the comp pin is tied to ground. After that, the current source is turned off and the device tries to switch again by passing.
● This pin is also connected to the error amplifier to allow primary and secondary regulation configurations. In case of one-stage regulation, an internal 13V trim reference voltage is used to keep VDD at 13V. For secondary regulation, A between 8.5V and 12.5V will be put on the VDD pin through a transformer design to trap the output of the transconductance amplifier in a high state. The compressor pin acts as a constant current source and can be easily connected to an optocoupler. Note that any overvoltage due to a fault in the regulation loop is still passed by the error amplifier through the vdd voltage, which cannot exceed 13v. The output voltage will be slightly higher than nominal, but still within the controllable range.
Compensation pin This pin provides two functions:
● It is the output of the error transconductance amplifier, allowing the connection of a compensation network to provide the transfer function required for the regulation loop. Its bandwidth can be easily adjusted to the required value and the usual component values. As mentioned above, the secondary regulation configuration also goes through the compressor pins.
● When the compressor voltage is lower than 0.5V, the circuit is turned off and the power mosfet has zero duty cycle. This function can be used to switch off the converter and is automatically activated by the regulation loop (regardless of configuration) at negligible output power or open load conditions.

OSC pin (oscillator frequency): RT Corporation
- Coiled tubing must be connected on the network to define the switching frequency. Please note that despite having RT connected to VDD, there will be no noticeable frequency change in VDD changes from 8V to 15V. When connected to an external frequency source, it also provides a synchronization function.

Operating Instructions Current Mode Topology:
The current mode control method is the same as that integrated in the Viper50-E, using two control loops - an inner current control loop and an outer voltage control loop. When the power mosfet output transistor is turned on, the inductor current (primary side of the transformer) is monitored using sensor mesh technology and converted into a voltage proportional to this vs current. When vs reaches vcomp (amplified output voltage error), the power switch is off. Therefore, the outer voltage control loop defines the inner loop to regulate the peak current through the power switch and the transformer primary winding.
Due to the inherent input, good open-loop DC and dynamic line regulation voltage feed-forward characteristics of current-mode control are ensured. This improves line regulation, instantaneous correction for line changes, and better stability of the voltage regulation loop.
The current mode topology also ensures good confinement in short circuit conditions. During the first stage, the output current increases slowly with the dynamics of the regulation loop.
Then it hits the max limit current internal setting and eventually stops because the power on VDD is no longer correct. For specific applications, the maximum peak current internal setting can be overridden by externally limiting the voltage offset on the comp pin.
The integrated blanking filter is turned on in the integrated power mosfet. This feature prevents switching pulse termination capacitors or secondary rectifier reverse recovery times during abnormal or premature primary current spikes.
Standby Mode Standby operation at near on-load conditions automatically results in Burst Mode operation allowing secondary side voltage regulation. Burst mode operation from normal transition power pstby is given by: where?
lp is the primary inductance of the transformer. fsw is the normal switching frequency. Istby is the smallest controllable current that corresponds to the device functioning properly. This current can be calculated as: TB+TD is the sum of the blanking time and the propagation time of the internal current sensing. and comparators, and roughly represent the minimum turn-on time of the device. NOTE: PSTBY may be affected by converter efficiency at low loads and must include power drawn on the primary auxiliary voltage.

Once the power falls below this limit, the auxiliary secondary voltage begins to increase. regulation level above 13V, forcing the output voltage of the transconductance amplifier to a low state (vcomp High voltage startup current source The integrated high voltage current source is in the startup phase. This current is partially absorbed by the internal control circuit into standby mode, reducing power consumption, and supplied to an external capacitor connected to the VDD pin. Once the voltage on this pin reaches the high voltage threshold vddon's uvlo logic, the device goes into active mode and starts switching. The start-up current generator is turned off and the converter should normally supply the required current on the VDD pin, through the auxiliary winding of the transformer. In the event of an abnormal condition where the auxiliary winding cannot supply a low voltage supply current to the VDD pin (i.e. the converter output is shorted) the external capacitor discharges the uvlo logic to the low threshold voltage vddoff, and the device returns to the inactive state , where the internal circuitry is in standby mode and the startup current source is activated. The converter enters an endless start-up cycle with a start-up duty cycle defined by the ratio of charge current to discharge at Viper100-E try to start. By design, this ratio is fixed between 2A and 15A, providing a 12% startup duty cycle with an input voltage of 1kV although the power dissipation at startup is about 100V.
This low start-up duty cycle prevents the application of stress on the output rectifier and the transformer in the event of a short circuit.
An external capacitor CVDD on the VDD pin must be activated according to the converter when the device starts switching. This time tss relies on many parameters, among which the transformer design, output capacitor, soft-start characteristics and compensation network are implemented on the comp pin. The following formula can be used to define the minimum capacitor required: where?
IDD is the current consumption on the VDD pin when switching.
tss is the startup time of the converter when the device starts switching. Worst case is usually full load.
vddhyst is the voltage hysteresis of the uvlo logic (referenced to the minimum specified value). The soft-start feature can be implemented with a simple capacitor on the comp pin which will also be used as a compensation network. In this case, the regulation loop bandwidth is quite low because of the large value of this capacitor. A schematic diagram can be used if a large bandwidth of the regulation loop is required. It mixes a performance compensation network with a separate high value soft-start capacitor.
Soft-start time and regulation loop bandwidth can be adjusted independently.
If the device is intentionally shut down by tying the compressor pin to ground, the device also performs a start-up cycle with the VDD voltage oscillating between VDDON and VDDOFF.
This voltage can be used to provide external functions as long as it does not consume more than 0.5mA. A typical application of this function is shown with a latch off. Once the "shutdown" signal is activated, the device will remain off until the input voltage disappears.

Electrical overstress intensity due to severe fluctuations in input voltage or lightning. Following layout considerations is sufficient to prevent catastrophic damage most of the time. However, in some cases, a voltage surge through the transformer-coupled auxiliary winding can exceed the absolute maximum voltage rating of the VDD pin. Such an event may trigger the VDD internal protection circuit, which may be damaged by the high voltage discharge current of the VDD bulk capacitor. A simple rc filter can be used to increase the immunity of the application to such surges.

Layout Considerations A few simple rules ensure proper operation of a switching power supply. They may be divided into two categories:
– Minimize the power loop: The corresponding path of the switching power supply current must be carefully analyzed and the inner loop area must be as small as possible. This avoids radiated EMC noise, magnetically couples conducted EMC noise, and provides improved efficiency by eliminating parasitic inductances, especially on the secondary side.
- Use different tracks for low level and power signals: Interfering signals and power due to mixing can cause instability and/or abnormal behavior of the unit in the event of severe power surges (input overvoltage, output short circuit...). For vipers, these rules apply as shown. – Loops C1-T1-U1, C5-D2-T1 and C7-D1-T1 must be minimized.
– C6 must be as close as possible to T1.
– Signal parts C2, ISO1, C3 and C4 are connected directly to the power supply of the device using dedicated rails connected.