General Instructions

The FMS7401L is a digital power controller designed for applications that require easy digital control for analog-based implementations. The FMS7401L is an ideal solution for ballast control, motor control and battery management functions. It integrates a variety of analog modules with an 8-bit microcontroller core, providing high performance, low power consumption, and a small footprint in one chip. It is powered by CMOS technology and full static technology. The FMS7401L is available in 8-pin and 14-pin PDIP, SOIC and TSSOP packages.

feature

8-bit microcontroller core 1K bytes on-board code EEPROM 64 bytes data EEPROM 64 bytes SRAM reset Multiple input wakeup on all general purpose I/O pins Fast 12-bit PWM timer with dead-band control and half-bridge output drive – Input capture mode 5-channel 8-bit analog-to-digital converter – 20 microsecond conversion time – sample and hold – internal reference voltage (1.21V) – gated auto-sampling mode Generator (1 mA) On-Chip Oscillator – No External Components – 1 µs Instruction Cycle Time On-Chip Power-On Reset Programmable Read-Write Disable Functions Memory-Mapped I/O Programmable Comparator (63 Levels) Brown Reset O option Push-pull output with tri-state option Weak pull-up or high impedance input Fully static CMOS – Power Save Stop Mode – <1.3µA @ 3.3V – Power Save Idle Mode – < 180µA @ 3.3V Single Supply Operation – 2.7V – 3.6V 40-year data retention 100,000 data changes In-circuit programming in 8/14-pin PDIP, SOIC, and TSSOP packages – Fast page write programming mode Reset circuit The reset circuit in the FMS7401L contains four input conditions that trigger a main system reset. Triggered when the main system resets, a series of events occurs that defaults all memory-mapped registers (including initialization registers) and I/O to their initial state (see Table 1). During system reset, instruction core execution is suspended, allowing the internal oscillator and other analog circuits to stabilize. Once the system reset sequence is complete, the device will begin its normal operation by executing the program of instructions residing in the code eeprom memory. The time required to complete the system reset sequence (treset) depends on a single trigger condition and is defined in the electrical system's characterization section of the data sheet. The four reset trigger conditions are as follows: Power-on reset (POR) External reset 1 Brown reset (BOR) See reset 2

1.1 Power-on-reset circuit The power-on-reset (por) circuit holds the device in reset until the vcc reaches a voltage level sufficient for the device to function properly. The por circuit is sensitive to different vcc ramp rates and must be within the svcc as in the electrical characteristics section of the datasheet. When VCC falls, the POR circuit does not generate a system reset. This function is performed by the brown out reset (bor) circuit and must be enabled by the boren bit of the initialization register 1.4. If VCC does not drop to 0V before the next power-up sequence, the BOR circuit must be enabled and/or externally reset via reset pin 11.2. 1 If not Properly reset devices in applications using por/bor circuits. The reset input pin contains an internal pull-up resistor, making it an active low signal. Therefore, to issue a device system reset, the reset input should remain low for at least 10 microseconds (ie, return to a high state) before releasing it. When the reset input is held low, the internal oscillator and other analog circuits are held in a low power state reducing the current consumption of the device (similar to the stop mode state). Additionally, the I/O pins are initialized to an input tri-state configuration unless otherwise specified. 5 On the rising edge of the reset input signal, the main system reset sequence is triggered to release the internal oscillator and other analog circuits so that they can be initialized and begin normal operation. 1.3 Brown output reset circuit The brown out reset (bor) circuit is one of the on-chip analog comparator peripherals and must be initialized by initializing the born bit of the register 1.4 The bor circuit is used to keep the device in reset when vcc drops below the datasheet Fixed thresholds defined in the Electrical Characteristics section. On reset, the device remains in its initial state until VCC rises above the fixed/power-up threshold. Shortly after VCC rises to the fixed/power-up threshold, an internal system reset sequence is initiated. Once the system reset procedure is completed, the device will begin normal operation executing the program of instructions in the code EEPROM memory. In situations where VCC rises and falls slowly and VCC does not drop to 0V, a BOR circuit should be used before returning to the normal operating range of the device. A bor circuit can be seen as a Por circuit if VCC is not lower than 0.7V.

The fs[1:0] bits of pscale register 4 select the division factor for the fpwmclk output (see Table 3). The fs bits can be changed by software at any time; however, if the PWM Timer 1 circuit is in run mode, the fs[1:0] value does not change the FPWMCLK output frequency until the end of the PWM period (once the TMR1 counter overflows). The last fs[1:0] value at the end of the PWM cycle will indicate the division factor of the fpwmclk output for the next PWM cycle. When reading fs[1:0], the value reported will be the last value written by software (it may not necessarily reflect the current PWM period). The main system instruction clock (ficlk) source can be provided by the internal oscillator (fosc) or the f (fs=0) output of the pll using the same division factor as selected by fs[1:0]=00. 6 The fmode bit of pscale register 4 selects between f (fs=0). (if fmode=1) or frclk1 divided by 2 signal. With the fmode bit enabled, instructions can be executed up to 8 times faster than the standard at a given speed. The fmode bit cannot be set if the PLL is not enabled. 5 Any attempt to write when pllen=0, fmode will force fmode=0 to ignore any set instructions. Once the PLL is enabled, software may dynamically change the source code of ficlk during normal instruction execution to speed up specific operations. In order to disable the PLL clock structure synchronously, software must clear the pllen bit in order to successfully disable the PLL, for example using a separate instruction such as "rbit pllen, pscale". The special conditions of the shutdown/idle energy saving mode must also be considered.

Eight I/O pins (six on the 8-pin package option) are bidirectional. Bidirectional I/O pins can be individually configured by software as high-impedance inputs, weak pull-up inputs, or push-pull outputs. This operating state is determined by the contents of the corresponding bits in the data and configuration registers. Each bidirectional I/O pin can be used for general purpose I/O or, in some cases, for a specific alternate function hardware as determined by the chip.

Multiple Input Wakeup Circuit: Multiple Input Wakeup (MIW) circuit can be used to wake the device from stop or idle mode1 with an external event, generated by any or all I/O ports (g0–g7) for software monitoring and microcontroller use Flag for hardware interrupt. MIA uses wake-enable (wken), wake-edge (wkedge), wake-suspend (wkpnd), and t0cntrl memory-mapped registers. 2 wken, wkedge, and wkpnd are 8-bit registers where each bit corresponds to an I/O port pin (see Table 21). All four registers are initialized to 0x00 on system reset. The pwmoff output signal can also be programmed as the input to the G6 port MIW circuit. If the PWMOFF/G6 input MIW circuit is enabled and configured to trigger its microcontroller hardware interrupt (EDGEI). Bit 6 (pwmint) of the DDELAY register, if set to 1, selects the pwmoff signal in place of its G6 input to the MIW circuit. Software must then enable the miw pwmoff/g6 circuit by setting the wken[6] bit. The WKEDG[6] bit must also be cleared to select the rising edge transition of the pwmoff signal as its wkpnd[6] bit flip-flop. Software can monitor the wkpnd[6] flag or enable the miw hardware interrupt (edgei) to help detect when the pwmoff signal is triggered. Refer to the Programmable Comparator Circuits section of the datasheet for more details. 9.1 MIW Configuration Register The Wake-Up Enable (WKEN) register individually enables edge transitions of I/O ports to trigger the wake-up/interrupt pending flag. If the wken register bit is 1, the corresponding I/O port's MIW circuit (defined by its bit number) is enabled; otherwise, the port circuit remains disabled and the suspend flag may not be triggered. The wake-up edge (wkedge) register bit is used to program the pending flag of an enabled I/O port that will transition from a rising/falling edge. If the wkedge register bit is 1, a falling edge transition of an enabled I/O port will trigger the pending flag.

If zero, a rising transition on an enabled I/O port will trigger the pending flag. The MIW circuit shares a hardware interrupt (EDGEI) among all pending flags, and the enable (wkinten) bit of the t0cntrl register is enabled by the wake-up interrupt. 2 If the wkinten bit is set, hardware interrupts are enabled for the MIW circuit to 1.3 Wake-up Pending (wkpnd) register contains a pending flag corresponding to each I/O port pin. If a wkpnd register bit is 1, the programming I/O port edge transition has triggered its pending flag. If zero, the flag is not pending and no transition has occurred since the last pending reset. The pending flag can only be triggered by an enabled I/O port (if its wken register bit is 1). Once a suspend flag is triggered, all flags are logically OR'ed together to trigger a wake-up mode and/or hardware interrupt (if enabled) while in a "suspend/idle" state. If software is to re-enter suspend/idle mode, all suspend flags must be cleared, otherwise the command will be ignored. Since all MIW pending flags share a hardware interrupt, software must take care of the handling of pending flags when multiple pending flags are enabled. As long as the MIW pending flag is set, hardware interrupts will continue to execute the software's MIW interrupt service routine at the highest priority until all pending flags have been cleared. 4 The RIT instruction can be used before exiting suspend/idle mode or before leaving the software's MIW interrupt service routine.

Clear specific pending flags. The rbit instruction requires two instruction clock cycles to complete its execution. On the first loop, all 8 register bits are automatically read to get their latest value. In the second loop, the bit to be cleared is given its new value, and then all bits are rewritten to the register. Clearing a single suspend flag with the rbit instruction is not potentially dangerous if only one wakeup I/O port is enabled. However, if multiple I/O ports are enabled, software may inadvertently clear the most recently triggered pending flag execution if the trigger occurs during the second stage of the RBIT instruction. To avoid this, the set pending flag must be cleared using the ld instruction. The miw circuit is designed such that software cannot trigger the pending flag by writing a 1 to the wkpnd register bit, it can only clear it. Action Writing a 1 to a wkpnd register bit will retain the current bit value. Writing a 0 to a wkpnd register bit will clear that bit value. Therefore, the "ld wkpnd, 0f7h" instruction will clear wkpnd[3], leaving all other bits unchanged.