feature

Pin with ADS7841 ; single supply: 2.7V to 5V; 4-channel single-ended or; dual-channel differential input; up to 100kHz slew rate; 86dB SINAD; serial interface; SSOP-16 package.

application

data acquisition; test and measurement; industrial process control; personal digital assistants; battery powered systems.

illustrate

The ADS8341 is a 4-channel 16-bit sampling analog-to-digital converter with a synchronous serial interface. Typical power consumption is 8MW rate and +5V supply at 100kHz throughput. The reference voltage (VREF) can be varied between 500V and VCC, providing a corresponding input voltage range of 0V to VREF. The device includes a shutdown mode that reduces power consumption to less than 15 microwatts. The test voltage for the ADS8341 is 2.7V.

The low-power, high-speed, and on-board multiplexer ADS8341 is ideal for battery-operated systems such as personal digital assistants, portable multi-channel data loggers, and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The ADS8341 is available in an SSOP-16 package and is guaranteed over a temperature range of -40°C to +85°C.

theory of operation

is a classic successive approximation register (SAR) A/D converter. The architecture is based on capacitive redistribution, which essentially includes sample-and-hold functionality. The converter is fabricated using a 0.6 μm CMOS process.

The basic operation of the ADS8341 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference voltage can be any voltage between 500MV and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the slew rate of the ADS8341.

The analog inputs to the converter are differential and provided through a four-channel multiplexer. Inputs can be supplied referenced to the voltage on the COM pin (usually ground) or differentially using two of the four input channels (CH0-CH3). Specific configurations can be selected via the digital interface.

analog input

Figure 2 shows the block diagram of the input multiplexer on the ADS8341. The differential input to the converter comes from one of the four inputs, referenced to the COM pin or two of the four inputs. Tables 1 and 2 show the relationship between the a2, a1, a0, and sgl/dif control bits and the analog multiplexer configuration. Control bits are provided serially via the DIN pin, see the Digital Interface section of this datasheet for details.

When the converter enters holdover mode, as shown in Figure 2, the voltage difference between the +In and –In inputs is captured on the internal capacitor array. The voltage at the input is limited to between -0.2V and 1.25V, allowing the input to reject small signals shared by the input and the input. The + input has a range of -0.2V to +VCC+0.2V.

The input current on the analog input depends on the slew rate of the device. During sampling, the power supply must charge the internal sampling capacitor (typically 25pF). After the capacitor is fully charged, there is no more input current. The charge transfer rate from the analog source to the converter is a function of the slew rate.

reference input

The external reference sets the analog input range. The ADS8341 will operate from a reference voltage range of 500mV to +VCC. Remember that analog input is the difference between + input and – input, see Figure 2. For example, in single-ended mode, when the COM pin is grounded, a 1.25V reference, the selected input channel (CH0-CH3) will correctly digitize signals in the 0V to 1.25V range. If the COM pin is tied to 0.5V, the input range on the selected channel is 0.5V to 1.75V.

There are several key terms for the reference input and its wide voltage range. As the reference voltage decreases, the analog voltage weighting for each digital output code also decreases. This is often referred to as the lsb (least significant bit) size and is equal to the reference voltage divided by 65536. Any offset or gain error inherent in the A/D converter will increase with the size of the lsb as the reference voltage decreases. For example, if the offset for a given converter is 2LSB (with a 2.5V reference), it will typically be 10LSB (with a 0.5V reference). In each case, the actual offset of the device is the same, 76 microvolts.

Likewise, as the size of the LSB decreases, the noise or uncertainty of the digitized output increases. At a reference voltage of 500 mV, the dimension of the LSB is 7.6 microvolts. This level is lower than the internal noise of the device. Therefore, the digital output code will be unstable and vary by several lsb around the average value. The distribution of the output codes will be Gaussian, and noise can be reduced by simply averaging successive conversion results or applying a digital filter.

In the case of low reference voltages, care should be taken to provide a clean layout, including adequate bypassing, clean (low noise, low ripple) power supplies, low noise references, and low noise input signals. Due to the smaller size of the LSB, the converter will also be more sensitive to nearby digital signals and electromagnetic interference.

The voltage at the VREF input is unbuffered and directly drives the capacitor digital-to-analog converter (CDAC) portion of the ADS8341. Typically, the input current is 13 microamps and the reference voltage is 2.5V. Depending on the conversion result, this value will vary in microamps. The reference current decreases with increasing slew rate and reference voltage. Since the current from the reference is drawn on every bit decision, clocking the converter faster during a given conversion does not reduce the overall current consumption from the reference.

digital interface

Figure 3 shows the typical operation of the ADS8341 digital interface. This diagram assumes that the digital signal source is a microcontroller or digital signal processor with a basic serial interface (note that the digital inputs can tolerate overvoltages up to 5.5V regardless of +VCC). Each communication between the processor and the converter consists of eight clock cycles. A complete conversion can be done with three serial communications for a total of 24 clock cycles on the dclk input.

The first eight cycles are used to provide control bytes through the din pin. When the converter has enough information about the following conversions to properly set the input multiplexer, it enters acquisition (sampling) mode. After another three clock cycles, the control byte is complete and the converter enters conversion mode. At this point, enter sample and hold to enter hold mode. The next 16 clock cycles complete the actual analog-to-digital conversion.

control byte

Figure 3 also shows the position and order of the control bits in the control byte. The details of these bits are given in Tables 3 and 4. The first bit 's' must always be high and indicates the start of the control byte. The ADS8341 will ignore the input on the DIN pin until a start bit is detected. The next three bits (a2 a0) select one or more valid input channels of the input multiplexer (see Tables 1 and 2 and Figure 2).

The SGL/DIF bit controls the multiplexer input mode: single-ended (high) or differential (low). In single-ended mode, the selected input channel is referenced to the COM pin. In differential mode, two selected inputs provide differential input. See Table 1, Table 2 and Figure 2 for details. The last two bits (PD1-PD0) select the power-down mode, as shown in Table V. If both inputs are high, the device is always powered. If both inputs are low, the device goes into power-down mode between transitions. When a new transition is initiated, the device will immediately resume normal operation, power up the device without delay, and the first transition will be valid.

clock mode

The ADS831 can be used with an external serial clock or an internal clock to perform successive approximation conversions. In both clock modes, an external clock shifts data in and out of the device. When PD1 is high and PD0 is low, internal clock mode is selected.

If the user decides to switch from one clock mode to another, additional conversion cycles are required before the ADS8341 switches to the new mode. Additional cycles are required since the pd0 and pd1 control bits need to be written to the ads8341 before the clock mode is changed.

When the ADS8341 is first powered up, the user must set the desired clock mode. This can be done by writing pd1=1 and pd0=0 for internal clock mode or pd1=1 and for external clock mode, PD0=1. After enabling the desired clock mode, the ADS8341 should only be set to power down between conversions (ie, PD1=PD0=0). The ADS8341 maintains the clock mode it was in before entering power-down mode.

external clock mode

In external clock mode, the external clock not only shifts data in and out of the ADS8341, but also controls the A/D conversion steps. Busy will go high for one clock cycle after the last bit of the control byte is shifted in. Consecutive approximate bit decisions are made on each DUT for the next 16 falling edges of DLK (see Figure 3). Figure 4 shows busy timing in external clock mode.

Since one clock cycle of the serial clock is consumed when busy high (when making the msb decision), 16 additional clocks must be given to clock all 16-bit data; therefore, a conversion requires at least 25 clock cycles to fully read fetch data. Since most microprocessors communicate in 8-bit transfers, this means that additional transfers must be made to capture the lsb.

There are two ways to handle this requirement. One of them is shown in Figure 3. The LSB is clocked out of the ADS8341 at the same time the start of the next control byte occurs. This method allows maximum throughput and 24 clock cycles per conversion.

Another approach, shown in Figure 5, uses 32 clock cycles per conversion; the last 7 clock cycles simply shift zeros on the output line. Busy High-impedance state when CS goes high; busy will go low after the next CS falling edge.

Internal clock mode

In internal clock mode, the ADS8341 generates its own conversion clock internally. This frees the microprocessor from having to generate the SAR conversion clock and allows the conversion results to be read at any clock rate from 0MHz to 2.0MHz at the convenience of the processor. busy goes low at the start of a conversion and returns high when the conversion is complete. During the transition, busy will remain low for a maximum of 8 seconds. Also, DCLK should be kept low during conversions for best noise performance. The conversion result is stored in an internal register; data can be clocked from this register at any time after the conversion is complete.

If cs is low when busy goes low after conversion, the next falling edge of the external serial clock will write out the msb on the dout line. The remaining bits (D14-d0) will be clocked after the msb on each successive clock cycle. If cs high goes low when busy

The dout line will then be tri-stated low until cs runs, as shown in Figure 6. CS does not need to be held low after a conversion has started. Note that busy is not tri-stated when CS goes high in internal clock mode.

Data can be shifted in and out of the ads8341 at clock rates over 2.4mhz as long as the minimum acquisition time tacq is kept above 1.7µs.

digital timing

Figure 4 and Tables VI and VII provide the detailed timing of the ADS8341 digital interface.

Data Format

The ADS8341 output data is in direct binary format, as shown in Figure 7. This graph shows the ideal output code for a given input voltage, excluding the effects of offset, gain, or noise.

When the ADS8341 is in auto power-down mode, if DCLK is active and CS is low, the device will continue to consume some power in the digital logic. Power can be reduced by keeping CS high to a minimum. The difference in supply current in these two cases is shown in Figure 9.

Power consumption

The ADS8341 has three power modes: full power (PD1-PD0=11B), automatic power-off (PD1-PD0=00B). off (shdn low). The effect of these modes depends on how the ADS8341 operates. For example, at full slew rate and 24 clocks per slew, there is little difference between full power mode and auto shutdown, shutdown (shdn low) does not reduce power consumption.

When operating at full speed and 24 clocks per conversion (as shown in Figure 3), the ADS8341 spends most of its time acquiring or converting. Assuming this mode is active, the time for automatic shutdown is short. Therefore, the difference between full power mode and automatic shutdown is negligible. If the slew rate is reduced by simply slowing down the frequency of the input, the two modes remain roughly equal. However, if the DCLK frequency remains at the maximum rate during transitions, but transitions are generally less frequent, the difference between the two modes is significant. Figure 8 shows the difference between reducing the dclk frequency (“scaling” the dclk to match the slew rate) or keeping the dclk at its highest frequency and reducing the number of conversions per second. In the latter case, the converter spends an increasing percentage of time in power-down mode (assuming auto power-down mode is active).

Figure 8. Supply current as a ratio of direct sampling DCK frequency or keeping DCLK at maximum possible frequency.

Operating the ADS8341 in auto power-down mode results in the lowest power consumption and no transition time "penalty" at power-up. The first conversion will be valid. shdn can be used to force an immediate power down.

noise

As can be seen from Figures 10 to 13, the noise floor of the ADS8341 itself is extremely low and much lower than that of competing A/D converters. The ADS8341 was tested at 5V and 2.7V and in internal and external clock modes. The analog input pin adopts low-level DC input, and the converter undergoes 5000 conversions. The digital output of the A/D converter will vary in the output code due to the internal noise of the ADS8341. This applies to all 16-bit SAR type A/D converters. Use a histogram to plot the output codes, the distribution should be bell-shaped, with the peaks of the bell-shaped curve representing the nominal codes of the input values. The ±1σ, ±2σ and ±3σ distributions will represent 68.3%, 95.5% and 99.7% of all codes, respectively. Transition noise can be calculated by dividing the number of codes measured by 6, which yields a ±3σ distribution or 99.7% of all codes. According to statistics, up to 3 codes may not be in the distribution when performing 1000 conversions. The ads8341 will produce transition noise less than ±0.5lsb when working at 5v, and its output code is a ±3σ distribution. Remember, to achieve this low noise performance, the peak-to-peak noise of the input and reference signals must be less than 50 microvolts.

average value

The noise of the a/d converter can be compensated by averaging the digital code. By averaging the conversion results, the transition noise will be reduced by a factor of 1/√n, where n is the average. For example, averaging 4 transitions will reduce transition noise by 1/2 to ±0.25 lsb. Average can only be used for input signals with frequencies close to DC.

For AC signals, a digital filter can be used for low-pass filtering and decimation of the output code. This method works similarly to the averaging method; every 2 decimations increases the signal-to-noise ratio by 3db.

layout

For best performance, attention should be paid to the physical layout of the ADS8341 circuit. This is especially true if the reference voltage is low and/or the slew rate is high. The basic SAR structure is very sensitive to faults or sudden changes in power, reference, ground connections, and digital inputs that occur before the outputs of the analog comparators are locked. Therefore, in any conversion process of the N-bit synthetic aperture radar converter, there are N "windows", in which a large external transient voltage easily affects the conversion result. Such failures can originate from switching power supplies, nearby digital logic, and high-power equipment. The degree of error of the digital output depends on the reference voltage, layout, and precise timing of external events. The error may change if the time of the external event changes relative to the dclk input.

With this in mind, the supply to the ADS8341 should be clean and well bypassed. A 0.1µf ceramic bypass capacitor should be placed as close to the device as possible. Additionally, 1µf to 10µf capacitors and 5Ω or 10Ω series resistors can be used to low pass filter noise power supplies.

Again, the reference should be bypassed with a 0.1µf capacitor. Again, series resistors and bulk capacitors can be used as the reference voltage for the low pass filter. If the reference voltage is sourced from an op amp, make sure it can drive the bypass capacitor without oscillation (a series resistor can help in this case). On average, the ADS8341 draws very little current from the reference circuit, but it does place more demands on the reference circuit for short periods of time (during transitions, on every rising edge of DCLK).

The ADS8341 architecture does not provide inherent rejection of noise or voltage variations associated with the reference input. This is especially of concern when the reference input is connected to the power supply. Any noise and ripple from the power supply will appear directly in the digital results. While high frequency noise can be filtered out as described in the previous paragraph, voltage variations due to line frequency (50 Hz or 60 Hz) can be difficult to remove.

The ground pin should be connected to a clean ground point. In many cases this will be the "analog" ground. Avoid making connections too close to the microcontroller or digital signal processor ground. If required, ground trace directly from the converter to the power entry point. An ideal layout would include an analog ground plane dedicated to the converter and associated analog circuitry.