4k spi eeprom cpu manager These devices combine four common functions, power-on reset control, watchdog timer, power supply voltage monitoring, block lock protection serial eeprom memory package. This combination reduces system cost, reduces board space requirements, and increases reliability. Applying power to the device will activate the power-on reset circuit time that holds the reset/reset active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code.
The watchdog timer provides an independent mechanism to protect the microcontroller. When the microcontroller fails to restart the timer within a selectable timeout interval, the device activates the reset/reset signal. The user selects the interval from three preset values. Once selected, the interval does not change even after cycling power. The device's low VCC detection circuit protects the user's system from a low voltage state and resets the system when VCC falls below the minimum VCC trigger point.
reset/reset is asserted until VCC returns to normal operating levels and stabilizes. Four industry standard VTRIP thresholds, however, intersil's unique circuitry allows the thresholds to be reprogrammed to meet custom requirements or fine-tune the thresholds for applications requiring greater precision.
The memory portion of the device is a cmos serial EEPROM array with Intersil block lock protection. This array is internally organized as 512 x 8. Device Features Serial Peripheral Interface (SPI) and its software protocol allow operation on a simple four-wire bus The device utilizes Intersil's proprietary Direct Write unit, providing an endurance of at least 100,000 cycles and a minimum data retention period of 100 years .
feature
8226 ; Low VCC detection and reset assertion
- Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V
- Use reprogram low VCC to reset the threshold voltage special programming sequence.
-Reset signal valid for VCC=1V
• Selectable timeout watchdog timer • Long battery life and low power consumption
-<50µA maximum standby current with watchdog on
-<10µA maximum standby current with watchdog off 4-bit EEPROM – 1M write cycle Use Block Lock™ memory to preserve critical data
- Protects 1/4, 1/2, all or none of the EEPROM array Built-in accidental write protection
- Write enable latch
-Write protect pin
• SPI interface - 3.3MHz clock frequency • Minimized programming time
-16 byte page write mode
-5ms write cycle time (typical)
• Available packages
-8 ld MSOP, 8 ld SOIC, 8 ld PDIP
-14 LD TSSOP
• Available lead-free plus annealed (RoHS compliant)
Applications • Communication Equipment
-Routers, hubs, switches
- Set-top boxes • Industrial systems
- Process control
-Intelligent meter • Computer system
-Desktop computer
- Web server • Battery powered device

Pin Description Serial Out (SO) Push/Pull serial data output pins as well. During a read cycle, data is shifted on this pin. data by the falling edge of the serial clock.
Serial Input (SI) Si is the serial data input pin. All opcodes, byte addresses, and data written to memory are input on this pin.
Data is latched on the rising edge of the serial clock.
Serial Clock (SCK) The serial clock controls the serial bus timing of data input and output. The opcode, address, or data pins on the SI are latched on the rising edge of the clock input, while the data on the so pin changes after the falling edge of the clock input.
Chip Select (CS/WDI) When CS is high, X5043 , X5045 are deselected, and so output pins are high impedance, X5043, X5045 will be in standby power mode unless a write operation is in progress internally. CS low starts X5043, X5045, putting it into active power mode. It should be noted that after power up, a high-to-low transition on CS is required for the start of any action.
Write Protect (wp) When wp is low, non-volatile writes to x5043, x5045 are disabled, but parts work normally. when? wp is held high and all functions, including non-volatile writes, function normally. When Cs is still low, Wp will go low to interrupt writing to X5043, X5045. If the internal write loop has started, wp going low will have no effect on writing.
Reset (reset, reset) X5043, X5045, reset/reset is active low/high, turns on the drain output whenever VCC falls below the minimum VCC detect level. It will remain active until VCC rises 200 meters above the minimum VCC sensing level. If the watchdog timer is enabled and CS remains high or low longer than the watchdog timeout period. A falling edge of CS will reset the watchdog timer.
Working principle Power-on reset Power on X5043, X5045, start power-on reset circuit. This circuit pulls the reset/reset pin active. Reset/Reset prevents the system microprocessor from under voltage or oscillator stabilization. The circuit releases a 200ms (nominal) reset/reset of the vtrip value when VCC exceeds the device, allowing the processor to start executing code.
During low voltage monitoring operation, X5043, X5045 monitor the VCC level if the supply voltage is lower than the preset minimum vtrip. The reset/reset signal prevents the microprocessor from being in a power-down or power-off state. The reset/reset signal remains active when the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP by 200ms.
A watchdog timer circuit monitors the activity of the microprocessor by monitoring the WDI input. The microprocessor must periodically toggle the CS/WDI pin to prevent the reset/reset signal from being activated. The CS/WDI pin must be toggled from high to low for the time-out period before the watchdog expires. Two nonvolatile control bits in the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits.

Pin Name Symbol Description
CS/WDI Chip Select Input SO Serial Output Serial Input SCK Serial Clock Input wp Write Protect Input vss Ground VCC Supply Voltage Reset/Reset Reset Output X5043, X5045
With no microprocessor action, the watchdog timer control bits remain unchanged even in the event of a complete power-down.
VCC Threshold Reset Procedure X5043, X5045 come with standard VCC threshold (vtrip) voltage. This value does not alter normal operating and storage conditions. However, in applications where the standard vtrip is not exactly correct, or if the vtrip value requires higher precision, the x5043, x5045 thresholds can be adjusted. The procedure is described below and uses high voltage control signals.
Set vtrip voltage This procedure is used to set the vtrip to a higher voltage value. For example, if the current vtrip is 4.4v and the new vtrip is 4.6v, this program will directly make the change. If the new setting will be lower than the current setting, then set the new value.
To set a new vtrip voltage, apply the desired vtrip to connect the threshold voltage to the VCC pin and the WP pin to the programming voltage Vp. Then send a wren command, then write data 00h to address 01h.cs high write operation starts the vtrip programming sequence. Turn wp down to finish. Note: This operation also writes 00h to the array address 01h.
Reset vtrip voltage This procedure is used to set the vtrip to the "native" voltage level. For example, if the current vtrip is 4.4v and the new vtrip must be 4.0v, then the vtrip must be reset. when? The vtrip is reset and the new vtrip is below 1.7v.
This step must be used to set the voltage to a lower value.
To reset the vtrip voltage, apply at least 3v to the vcc pin and connect the wp pin to the programming voltage vp. Then send the wren command and then write data 00h to address 03h.cs when the write operation starts the vtrip programming sequence. Bring wp down to finish the operation.

The memory portion of the serial memory device is a cmos serial EEPROM array with Intersil block lock protection. The array is internally organized as 512 x 8 bits. The device features a Serial Peripheral Interface (SPI) and software protocols allowing operation on a simple four-wire bus.
The device utilizes Intersil's proprietary Direct Write unit, offering at least 1,000,000 cycles and a minimum data retention period of 100 years.
The device is designed to interface directly with multiple synchronous serial peripheral interfaces (SPIs) of popular microcontroller families.
The device contains an 8-bit instruction register that controls the operation of the device. The script is written to the device entered via si. There are two write operations that require only instruction bytes. There are two read operations that use the instruction byte to initiate the output of the data. The rest of the operations require an instruction byte, an 8-bit address, and then a data byte. All command, address and data bits are clocked in by SCK. All instructions, addresses and data are transferred msb first.
SCK goes low after the clock and data timing SI lines are locked on the data input at Cs. Data is passed on the falling edge of SCK. sck is static, allowing the user to stop the clock, then restart to resume operation last. CS must be low during the entire operation.

A write-enable lock device contains a write-enable latch. This lock must be set before initiating a write operation. The wren instruction will set the latch and the WRDI instruction will reset it is not necessary to send byte addresses or data when a wren, wrdi or rdsr command is issued.
Status Register The Status Register contains four nonvolatile control bits and two volatile status bits. Control bits set watchdog timer and memory block lock protection.
The format of the status register is as shown in "Status Register".
The Work In Process (WIP) bit is a volatile read-only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit uses the RDSR instruction. When set to '1', a nonvolatile write operation is in progress. When set to "0", no progress is written.
The Write Enable Latch (WEL) bit indicates a "write enable" latch. When Wel=1, the latch is set and when Wel=0, the latch is reset. Velbits are volatile, read-only bits. The wren instruction sets the wel bit and the WRDS instruction resets the WEL bit.
The block lock bits bl0 and bl1 set the level protection of the block lock. These non-volatile bits use the wrsr instruction and allow the user to protect quarter, half, full or none of the EEPROM array. Any array protected by a partial block lock can be read, but not written. Change the BL bit to disable block lock protection for that section of memory.
Watchdog timer bits WD0 and WD1 select the watchdog timeout period. These nonvolatile bits are programmed with the wrsr instruction.
Reading the Status Register To read the status register, pull CS low to select the device, then send the 8-bit rdsr instruction. Then the status register is shifted on the SO line, by Clark. The status register can be read at any time, even during a write cycle.
Writing to the Status Register must be passed through before attempting to write data to the Status Register.
First pull CS low, then clock the wren command into the device and pull CS high.
Then lower cs again and enter the wrsr instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. CS was rising at the end of surgery. If CS is not high between wren and wrsr then ignore the wrsr instruction.

Read Memory Array When reading from the eeprom memory array, cs is the first to be pulled low to select the device. An 8-bit read command is sent to the device followed by an 8-bit address. Bit 3 reads the upper or lower half of the instruction device. After the read opcode and address are sent, the data stored in the memory at the selected address is shifted on the SO line. The next data address to be stored in memory can be supplied by continuing to clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter rolls back to address 000h, allowing the read cycle to continue indefinitely. The read operation is terminated by bringing CS high.
Writing to the memory array Before attempting to write data to the memory array, you must first pull CS low, then time the wren instruction into the device and pull CS high by issuing.
Then lower cs again and enter the write command followed by the 8-bit address, then the data to be written.
Bit 3 of the write instruction contains address bit A8, which selects the upper or lower half of the array. If CS does not go between wren and write, the write command is ignored.
Write operations require at least 16 clocks. CS must be held low during operation. This host can continue to write up to 16 bytes of data.
If the byte address reaches the last byte on the page, the clock continues and the counter will roll back to the first address of the page and overwrite all data that was previously written.
To complete a write operation (byte or page write), cs must be clocked after the last completed bit 0. The byte of data to be written has been timed. If it is brought high any other time, the write operation will not complete.
When a write is made after the status register, or a memory array write sequence, the status register can be read to check the WIP bit. WIP high and not volatile is writing.

Packaging Information
8 Lead Micro Small Outline Gull Wing Package M Type

Packaging Information
P-type 8-lead plastic dual in-line package

Packaging Information
S Type 8 Lead Plastic Small Outline Gull Wing Package

Packaging Information
14 Lead Plastic, TSSOP, Package Type V