feature

24-bit - no missing codes; 19-bit effective resolution up to; 20kHz data rate; low noise: 1.8ppm; four differential inputs; inl: 15ppm (max); external reference (0.5V to 5V); power down mode; Synchronous mode; low power: 8MW at 20kHz, 5MW at 10KHz.

illustrate

The ADS1253 is a high precision, wide dynamic range Deltasigma analog-to-digital converter with 24-bit resolution and a single +5V supply. The delta-sigma architecture is used for wide dynamic range and 24-bit omission-free code performance. For conversion rates up to 20khz, an effective resolution of 19 bits (1.8ppm rms noise) is obtained.

The ADS1253 is designed for high-resolution measurement applications in cardiac diagnostics, smart transmitters, industrial process control, weight scales, chromatography, and portable instruments. The converter includes a flexible, 2-wire synchronous serial interface with low cost isolation.

The ADS1253 is a 4-channel converter available in an SSOP-16 package.

theory of operation

The ADS1253 is a high precision, high dynamic range, 24-bit, delta-sigma, A/D converter capable of achieving very high resolution digital results at high data rates. The sampling rate of the analog input signal is determined by the frequency of the system clock (clk). The sampled analog input is modulated by a delta-sigma a/d modulator, followed by a digital filter. A sinc5 digital low-pass filter processes the output of the delta-sigma modulator and writes the result to the data output register. The DOUT/DRDY pin is pulled low to indicate that new data can be read by an external microcontroller/microprocessor. As shown in the block diagram on the previous page, the main functional blocks of the ads1253 are the fourth-order delta-sigma modulator, digital filter, control logic, input multiplexer, and serial interface. Each of these function blocks is described in the following sections.

analog input

The ADS1253 contains fully differential analog inputs. To provide low system noise, 98db common mode rejection and excellent power supply rejection, the design topology is based on a fully differential switched capacitor architecture. The bipolar input voltage range is -4.096 to +4.096V when the reference input voltage is equal to +4.096V. Bipolar range is related to -vin but not gnd.

The input impedance of the analog input varies with the ADS1253 system clock frequency (CLK). The relationship is: AIN impedance (Ω) = (8MHz/clk) • 210000.

For analog input signals, the overall analog performance of the device is affected in three ways: First, the input impedance affects accuracy. If the source impedance of the input signal is significant, or if passive filtering is present before the ads1253, a significant portion of the signal can be lost through this external impedance. The magnitude of the effect depends on the desired system performance.

Second, the current to or from the analog input must be limited. Under no circumstances should the current into or out of the analog input exceed 10mA.

Third, to prevent aliasing of the input signal, the analog input signal must be band-limited. The bandwidth of the A/D converter is a function of the system clock frequency. When the system clock frequency is 8MHz, the data output rate is 20.8kHz, and the A–3dB frequency is 4.24kHz. The -3db frequency is proportional to the system clock frequency.

To ensure the best linearity of the ADS1253, it is recommended to use a fully differential signal with equal capacitance to ground on both sides.

For more information on the input structure of the ADS1253, see application note SBAA086 on .

input multiplexer

The chs1 and chs0 pins are used to select the analog input channel, as shown in Table 1. The recommended way to change the channel is to change the channel after completing the conversion and reading of the previous channel. When a channel is changed, internal logic senses the change on the falling edge of CLK and resets the conversion process. The conversion data for the new channel is valid for the first day after the channel change.

When multiplexing the inputs, sampling rates close to 4kHz can be achieved. This is because it requires five internal conversion cycles to fully resolve the data and must also be read before changing the channel. The DRDY signal indicates the valid result after five cycles.

Bipolar input

Each differential input of the ADS1253 must be maintained between AgNd–0.3V and VDD+0.3V. When the reference voltage is lower than half of VDD, one input can be tied to the reference voltage and the other input can be from 0V to 2•Vref. By using a three-op-amp circuit with a single amplifier and four external resistors, the ADS1253 can be configured to accept bipolar inputs referenced to ground. Using the resistor values shown in Figure 1, traditional ±2.5V, ±5V, and ±10V input ranges can be connected to the ADS1253.

Delta-Sigma Modulator

The ADS1253 operates at a nominal system clock frequency of 8MHz. The modulator frequency is fixed relative to the system clock frequency. The system clock frequency is divided by 6 to get the modulator frequency. So when the system clock frequency is 8mhz, the modulator frequency is 1.333mhz. Furthermore, the oversampling rate of the modulator is fixed relative to the modulator frequency. The oversampling ratio of the modulator is 64, and when the modulator frequency is 1.333mhz, the data rate is 20.8khz. As shown in Table 2, using a slower system clock frequency will result in a lower data output rate.

reference input

At an 8MHz system clock, the average current of the reference input is 32µA. This current will be proportional to the system clock. Buffered references are recommended for the ADS1253. The recommended reference circuit is shown in Figure 2.

A reference voltage higher than 4.096V will increase the full-scale range while the absolute internal circuit noise of the converter remains the same. This will reduce the noise of the full-scale PPM, thereby increasing the effective resolution (see Typical Characteristics, RMS Noise vs. VREF Voltage).

digital filter

The digital filter of the ads1253, called the sinc5 filter, calculates the digital result based on the latest output from the delta-sigma modulator. At the most basic level, a digital filter can be thought of as simply averaging the modulator results in a weighted form and representing that average as a digital output. The digital output rate or data rate scales directly with the system clock frequency. This allows changing the data output rate over a very wide range (five orders of magnitude) by changing the system clock frequency. However, it is important to note that the –3db point of the filter is 0.2035 times the data output rate, so the data output rate should have enough margin to prevent the associated signal from decaying.

Since the conversion result is essentially an average value, the data output rate determines the location of the notches created in the digital filter (see Figure 3). Note that the first notch filter is located at the data output rate frequency, and the subsequent notch filters are located at integer multiples of the data output rate to suppress not only the fundamental frequency, but also harmonic frequencies. In this way, the data output rate can be used to set specific notch frequencies in the digital filter response.

Figure 2. Recommended external voltage reference circuit for optimal low noise operation with the ADS1253.

For example, if you need to suppress the power line frequency, you can simply set the data output rate to the power line frequency. For 50 Hz rejection, the system clock frequency must be 19.200 kHz, which sets the data output rate to 50 Hz (see Table 1 and Figure 4). For 60Hz rejection, the system CLK frequency must be 23.040kHz, which sets the data output rate to 60Hz (see Table I and Figure 5). If both 50 Hz and 60 Hz are required to be rejected, the system CLK must be 3.840 kHz; this sets the data output rate to 10 Hz and rejects 50 Hz and 60 Hz (see Table 1 and Figure 6).

There is an added benefit of using a lower data output rate. It can better suppress the signal range of interest over frequencies. For example, at a data output rate of 50 Hz, a valid signal at 75 Hz can alias back into the passband at 25 Hz. This is because at 75Hz, where the stopband frequency is higher than the first notch frequency, the rejection may only be 66dB (see Figure 4). However, setting the data output rate to 10Hz provides 135dB rejection at 75Hz (see Figure 6). Similar benefits are obtained at frequencies close to the data output rate (see Figures 7, 8, 9 and 10). For example, for a data output rate of 50 Hz, the rejection at 55 Hz may be only 105 dB (see Figure 7). However, at 10Hz data output rate, the rejection at 55Hz is 122dB (see Figure 8). If the slower data output rate does not meet the system requirements, the analog front end can be designed to provide the required attenuation to prevent aliasing. Additionally, the data output rate can be increased and additional digital filtering can be performed in the processor or controller.

Application Note: The spreadsheet for calculating the frequency response of the ADS1250-54 (SBAA103), which can be downloaded from the TI website, provides a simple tool for calculating the frequency response of the ADS1250 for any CLK frequency.

A digital filter is described by the following transfer function:

The digital filter requires five conversions to be fully stable. The modulator has an oversampling ratio of 64, so it takes 5•64 or 320 modulator results (or clocks) to fully resolve. Since the modulator clock is derived from clk (modulator clock = clk ÷ 6), the number of system clocks required for the digital filter to fully stabilize is 5•64•6 or 1920 clk. This means that any significant step change in the analog input requires five complete conversions to resolve. However, if the analog input has a step change with the DOUT/DRDY pulse, six conversions are required to ensure full settling.

control logic

Control logic is used for communication and control of the ADS1253.

Power up sequence

All digital and analog input pins must be low before power is applied. At power-up, these signal inputs may be biased to voltages other than 0V, however, they should not exceed +VDD.

Once the ADS1253 is powered up, the DOUT/DRDY line will pulse low on the first conversion, for which the data on the analog input signal is valid.

Dutt / Dudi

The dout/drdy output signal alternates between two modes of operation. The first mode of operation is Data Ready Mode (DRDY), which indicates that new data has been loaded into the data output register and is ready to be read. The second mode of operation is the data out (dout) mode, which is used to serially shift data out of the data out register (dor). The time domain partition is shown in Figure 11 - ing of the drdy and dout functions. The basic timing of dout/drdy is shown in Figure 13. The function of the dout/drdy pin in DRDY mode for the time defined by t2, t3 and t4. Status of the dout/drdy pins.

High until new data is internally transferred to DOR. The result of the A/D conversion is written from the most significant bit (msb) to the least significant bit (LSB) within the time specified by T1. The dout/drdy line is then pulsed low for a time defined by t2 and then driven high for a time defined by t3 to indicate that new data can be read. At this point, the function of the dout/drdy pins changes to dout mode. Data is shifted on the pins after t7. If msb is high (due to negative result) after time t3, the dout/drdy signal will remain high. A device communicating with ads1253 can provide sclk to ads1253 after a time specified by t6. The normal mode of reading data from the ADS1253 is that the device reading the ADS1253 latches the data on the rising edge of SCLK (as data is shifted out of the ADS1253 on the falling edge of SCLK). In order to retrieve valid data, it is necessary to revert to drdy mode at the dout/drdy pin.

If no SCLK is provided to the ADS1253 during DOUT mode, the msb of DOR appears on the dout/drdy line until the time defined by t4 begins. If an incomplete read is made to ads1253 in dout mode (i.e. less than 24 sclks are provided), there is a state of the last bit read on the dout/drdy line until the time defined by t4 begins. If more than 24 SCLKs are supplied in DOUT mode, the DOUT/DRDY line will remain low until the time defined by T4.

The internal data pointer used to shift out data on dout/drdy is reset on falling edges at times defined by t1 and t4. This ensures that in drdy mode is always msb of new data.

Synchronize multiple converters

The normal state of SCLK is low; however, multiple ADS1253S can be synchronized by keeping SCLK high. This is achieved by keeping SCLK high for at least four, but less than 20, consecutive DOUT/DRDY cycles. After the ADS1253 circuit detects that SCLK has been held high for four consecutive dout/drdy cycles, the dout/drdy pin pulses low for one clk cycle, then remains high, and the modulator remains in reset. The modulator will be released from reset and synchronization occurs on the falling edge of SCLK. For multiple converters, falling edge transitions of SCLK must occur simultaneously on all devices. It is important to note that the timing of the DOUT/DRDY pulses of multiple ADS1253S in the system within a DRDY cycle may differ before synchronization. Therefore, to ensure synchronization, SCLK must be held high for at least 5 Dr. Dai cycles. The edge of the first pulse sclk after the fall occurs at t14. The first dout/drdy pulse indicates valid data.

Power down mode

The normal state of SCLK is low; however, keep SCLK high and the ADS1253 will enter power-down mode. This is achieved by keeping SCLK high for at least 20 consecutive dout/drdy cycles. After the ADS1253 circuit detects that SCLK has been held high for four consecutive dout/drdy cycles, the dout/drdy pin pulses low for one clk cycle, then remains high, and the modulator remains in reset. If SCLK is held high for an additional 16 dout/drdy cycles, the ADS1253 will enter power-down mode. The part will be released from power down mode on the falling edge of SCLK. It is important to note that after four dout/drdy cycles, the dout/drdy pin remains high, but does not enter power-down mode for another 16 dout/drdy cycles. The first dout/drdy pulse after the falling edge of sclk occurs at t16, indicating valid data. Subsequent dout/drdy pulses will occur normally.

serial interface

The ADS1253 includes a simple serial interface that can be connected to microcontrollers and digital signal processors in a variety of ways. Communication with the ADS1253 controller area network begins when the first DOUT/DRDY pulse is detected after power-up.

It is important to note that the data from the ADS1253 is the 24-bit result msb sent first in offset binary 2's complement format.

Data must be clocked into drdy mode before the ADS1253 enters to ensure valid data is received, as described in the dout/drdy section of this datasheet.

isolation

The serial interface of the ADS1253 provides a simple method of isolation. The CLK signal can be the ADS1253, only two signals (SCLK and dout/drdy) are needed for isolated data acquisition. The channel select signals (chs0, chs1) also need to be isolated, unless the channels are automatically multiplexed using counters.

layout

power supply

The power supply must be well regulated and low noise. Power supply rejection will be an issue for designs that require the very high resolution of the ADS1253. Avoid running digital lines under the device as they may couple noise onto the die. High-frequency noise can capacitively couple into the analog portion of the device and alias back into the passband of the digital filter, affecting the conversion result. This clock noise can cause offset errors.

ground

The analog and digital parts of the system design should be carefully and cleanly divided. Each section has its own ground plane with no overlap between them. GND should be connected to the analog ground plane, as well as all other analog grounds. Instead of connecting the analog and digital ground planes to the board, connect the two ground planes with medium signal traces. For multiple converters, connect both ground planes to the center of all converters in one location as much as possible. In some cases, experimentation may be required to find the best point to connect the two planes together. Printed circuit boards can be designed to provide different analog/digital ground connections via shorts. An initial prototype can be used to determine which connection will work best.

decoupling

Good decoupling practices should be used for the ADS1253 and all components in the design. All decoupling capacitors, especially 0.1µf ceramic capacitors, should be placed as close as possible to the pins being decoupled. A 1µf to 10µf capacitor should be used in parallel with a 0.1µf ceramic capacitor to separate VDD from GND.

System Considerations

Power and grounding recommendations will vary based on overall system requirements and specific design. Achieving 24-bit noise performance is much more difficult than achieving 12-bit noise performance. Generally speaking, a system can be divided into four distinct phases:

(1), simulation processing

(2), the analog part of ADS1253

(3), the digital part of ADS1253

(4), digital processing

For the simplest system consisting of minimal analog signal processing (basic filtering and gain), a microcontroller, and a clock source, high resolution can be achieved by powering all components from a common supply. Additionally, all components can share a common ground plane. Therefore, there is no distinction between analog power and ground, and digital power and ground. The layout should still include a power plane, a ground plane, and careful decoupling. In more extreme cases, designs can include:

(1), multiple ADS1253S

(2), a wide range of analog signal processing

(3), one or more microcontrollers, digital signal processors or microprocessors

(4), many different clock sources

(5) Interconnection with various other systems

High resolution is difficult to achieve with this design. The approach is to divide the system into as many different parts as possible. For example, each ads1253 can have its own analog processing front end.

Definition of Terms

An attempt has been made to be consistent with the terminology used in this data sheet. In this regard, each term is defined as follows:

Analog Input Differential Voltage - For a fully differential analog signal, the voltage range can be compared to that of an instrumentation amplifier. For example, if both analog inputs to the ADS1253 are 2.048V, the differential voltage is 0V. If one analog input is 0V and the other analog input is 4.096V, the differential voltage magnitude is 4.096V. In this case, it doesn't matter which input is 0V and which is 4.096V. However, the digital output results are quite different. The analog input differential voltage is given by the equation: +VIN – (–VIN)

A positive digital output is produced when the analog input differential voltage is positive, and a negative digital output is produced when the differential is negative. For example, when the converter is configured with a 4.096V reference, a positive full-scale output is produced, while the analog input differential is 4.096V. A negative full-scale output is produced when the differential voltage is -4.096V. In each case, the actual input voltage must remain constant within the -0.3V to +VDD range.

Actual Analog Input Voltage - The voltage of any one of the analog inputs with respect to GND.

Full-Scale Range (FSR) - As with most A/D converters, the full-scale range of the ADS1253 is defined as the input that produces a positive full-scale digital output minus the input that produces a negative full-scale digital output. For example, when the converter is configured with a 4.096V reference, the differential full-scale range is:

[4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V

Least Significant Bit (LSB) Weight - This is the theoretical amount by which the differential voltage at the analog input must change in order to observe a change in the output data of one LSB. The calculation is as follows:

where n is the number of bits in the digital output. Transition Period - Transition period as used here refers to the time period between the dout/drdy pulses.

Effective Resolution - The ADs1253 in a specific configuration can be expressed in two different units: Bit rms (reference output) and µvrms (reference input). Calculated directly from the output data of the converter, each is a statistical calculation based on a given number of results. Noise occurs randomly; the rms value represents a statistical measure of one standard deviation. er in bits can be calculated as follows:

2•vref in each calculation represents the full-scale range of the ADS1253. This means that both units are absolute expressions of resolution and performance in different configurations can be directly compared regardless of the unit. FMOD - The frequency of the modulator and the sampling frequency of the input.

Data - Data output rate:

Noise Reduction - For random noise, averaging can improve er. The result is that the noise is reduced by a factor √n, where n is the mean, as shown in Table 5. This can be used to achieve true 24-bit performance at lower data rates. To achieve 24-bit resolution, more than 24 bits must be accumulated. A 36-bit accumulator is required to implement a 24-bit er. The following uses VREF=4.096V, the ADS1253 output data is 20kHz, and the average value of 4096 points takes 204.8ms. If the input signal drifts during this period, the benefit of the averaging will be reduced by 200 meters.