Z8018X microprocessor operation display function, general description, pin description, block
Diagrams, registers and details of the operating modes of the Z8018X microprocessor.
The software architecture provides the instruction set and CPU registers for the Z8018X microprocessor.
DC Characteristics presents DC parameters and absolute maximum ratings for the Z8x180 mph.
AC Characteristics describes the AC parameters of the Z8018X microprocessor.
The timing diagram contains the timing diagram of the Z8018X and standard test conditions for the MPU.
Addendum to the Z8018X series of Zilog MPUs:
• Instruction Set • Instruction Summary Table • Operation Code Map • Bus Control Signal Condition in Each Machine Cycle and Interrupt • Operating Mode Summary • Status Signals • I/O Registers and Ordering Information

Z80180, Z8S180, Z8L180 MPU Operating Characteristics • Operating frequency is 33 MHz
• On-chip mmu supports extended address space • Two DMA channels • On-chip wait state generator • Two Universal Asynchronous Receiver/Transmitter (UART) channels • Two 16-bit timer channels • On-chip interrupt controller • On-chip clock oscillator / Generator • Clocked Serial I/O Ports • Code Compatible with Zilog Z80 CPUs • Extended Instructions General Instructions The advantages of system cost and low cost provide higher performance and maintenance of power operation and compatibility with a large number of industry standard software around the Zilog Z8X CPU.
Higher operating frequencies allow for higher performance, reduced instruction execution time, an enhanced instruction set, and an on-chip memory management unit (MMU) with the ability to address up to 1 MB of memory.
By consolidating several key systems, the system cost is reduced using the CPU to implement on-chip functions. These key functions include I/O devices such as DMA, UART, and timer channels. The chip also includes dynamic RAM refresh control, various glue functions such as wait state generator, clock oscillator and interrupt controller.
Not only is the Z8x180 in normal operation, but processors in the Z8S180 and Z8L180 classes also offer two modes of operation designed to further reduce power consumption significantly. Sleep mode reduces power consumption by putting the CPU in a stopped state, which consumes less current while the on-chip I/O devices are still working.
System Stop mode puts the CPU and on-chip peripherals into a stopped state, reducing power consumption even further.
When combined with other cmos vlsi devices and memories, the Z8x180 is designed for high performance, low power operation.
Three-pin package family in Z8x180 MPU:
• 64-pin dual in-line package (DIP)
• 68-pin plastic leaded chip carrier (PLCC)
• 80-pin Quad Flat Pack (QFP)
Pin-out package descriptions for other Z8x180-based products are included in their respective product specifications below.
Configuration of Z8x180.

Z80180/Z8S180/Z8L180 Block Diagram

Pin Description
Grades a0-a19. Address bus (output, high, 3 states). a0-a19 form a 20-bit address bus. The address bus provides address bus exchange for memory data, up to 1 MB, and I/O data bus exchange, up to 64K. The address bus enters a high-impedance state during reset and the external bus acknowledge cycle. Address line A18 with PRT channel 1 (TOUT, selected as address output at reset) and address line A19 are not available in the DIP version of the Z8x180.
Bussack. Bus ack (output, active low). BUSACK indicates that the requesting device, microprocessor address and data buses, and control signals, have entered a high impedance state.
Bus Request Bus Request (input, active low). This input is requested by an external device such as a DMA controller to access the bus system. This request has higher priority than NMI and is always recognized at the end of the current machine cycle. This signal stops the CPU from executing further instructions and places the address and data bus and other control signals into a high impedance state.
cka0, cka1. Asynchronous clocks 0 and 1 (bidirectional, active high).
These pins are the transmit and receive clocks for the asci channel.
cka0 is multiplexed with dreq0, cka1 is multiplexed with dreq0 trend 0g! Serial clock (bidirectional, high). This line is the bell CSIO channel.
clock (phi) system clock (output, high). Use the output as a reference clock for the MPU and external systems. The frequency of this output is equal to half of the crystal or input clock.
frequency.
cts0. cts1. Clear to send 0 and 1 (input, active low). These lines are modem control signals for ASCI channels. CTS1 is multiplexed with RX.

d0–d7. Data bus (bidirectional, high, tri-state). d0-d7 form an 8-bit bidirectional data bus for transferring information to and from I/O and memory devices. The data bus enters the state during a high-impedance reset and external bus acknowledgment cycle.
DCd0 number. Data carrier detect 0 (input, active low). This input is the programmable modem control signal for ASCI channel 0.
Drake, Drake. DMA requests 0 and 1 (input, low). Drake is used to request DMA transfers from an on-chip DMA channel.
The DMA channel monitors these inputs to determine that the external device is ready for a read or write operation. These inputs can be programmed for level or edge sensing. DREQ0 is multiplexed with CKa0.
e. Enable clock (output, active high). Output during synchronous machine cycle clock bus transactions.
foreign language. External Clock/Crystal (input, high). Crystal oscillator connection. An external clock can be input to the Z8x180 when the crystal is not used through this pin. This input is Schmitt triggered.
stop. stop/sleep state (output, low). This output is asserted after the CPU has executed a HALT or SLP instruction, before the operation waits for a non-maskable or maskable interrupt to continue. halt is also used with the m1 and st signals to decode the state of the CPU computer cycle.
internationality. Mask interrupt request 0 (input, low). This signal is generated by an external I/O device. The CPU accepts this request at the end as long as the NMI and BUSREQ signals are not active. The CPU acknowledges the cycle with an interrupt. During this cycle, the m1 and iorq signals are activated.
International 1, International 2. Masks interrupt requests 1 and 2 (input, low).
This signal is generated by an external I/O device. The CPU honors these requests at the end of the current instruction cycle as long as the NMI, BUSREQ and INT0 signals are not active. The CPU acknowledges these interrupt requests with interrupt acknowledgement cycles. Unlike the ack for int0, neither m1 nor iorq are signaled active during this cycle.
IORQ Corporation. I/O request (output, active low, 3 states). IORQ indicates that the address bus contains valid I/O address operations for I/O reads or I/O writes. iorq is also in the acknowledgement of the INT0 input signal with m1 to indicate that the interrupt response vector can be placed on the data bus. This signal is similar to the IOE signal of the Z64180.
M1. Machine cycle 1 (output, active low). Along with mreq, m1 indicates that the current cycle is instruction execution. Together with iorq, m1 represents the current loop for interrupt acknowledgement. It is also used for braking and the ST signal used to decode the state of the CPU machine cycle. This signal is similar to the LIR signal of the Z64180.
gentlemen. Memory request (output, active low, 3 states). mreq indicates that the address bus reserves effective addresses for memory reads or memory writes. This signal is similar to the ME signal of the Z64180.
NMI Corporation. Non-maskable interrupt (input, negative edge triggered). NMI has priority over int and is always on instruction regardless of the state of the interrupt enable flip-flop. This signal forces the CPU to continue execution at location 0066H.
Read (output active low, 3 states). rd indicates that the cpu needs to read data from memory or an I/O device. Addressing I/O or memory devices must use this signal to transfer data to the CPU data bus.
RFSH. refresh(output, activity low). Together with MREQ, RFSH indicates that the current CPU computer cycle and the address bus must be used for dynamic memory refresh. The 8 bits of the lower order address bus (A7–a0) contain the refresh address.
This signal is similar to the reference signal of the Z64180.

PRT channel 1. This line is multiplexed with A18 of the address bus. txa0, txa1. Transmit data 0 and 1 (output, high). These signals are the transmitted data from the asci channel. Transmit data changes are related to the falling edge of the transmit clock.
TXS. The clock transfers data serially (output, high). This line is the data transmitted from the CSIO channel.
wait. wait(input; active low). wait indicates to the cpu that the address memory or I/O device is not ready for data transfer. This input is used to introduce extra clock cycles into the current machine cycle. Wait for the input to be sampled on the falling edge of t2 (and subsequent wait states). If the input is sampled low, a wait state is inserted until the wait input is sampled high, at which point time execution continues.
gross weight. write(output, low, 3-state). wr means that the cpu data bus holds valid data to be stored at the address I/O or memory location.
XTAL Corporation. Crystal (input, high activity). Crystal oscillator connection. This pin must remain open if an external clock is used instead of a crystal. This oscillator input is not TTL level (refer to DC characteristics)

architecture
The Z8x180 combines a high-performance CPU core with a variety of system and I/O resources useful in a wide range of applications. The central processing unit core consists of five functional modules: clock generator, bus state controller (including dynamic memory refresh), interrupt controller, memory management unit (MMU) and central processing unit (CPU). This integrated I/O resource forms the remaining four functional blocks: • Direct Memory Access (DMA) control (2 channels)
• Asynchronous Serial Communication Interface (ASCI, 2 Channels) Table 2. Multiplexed Pin Descriptions Multiplexed Pin Descriptions When reset, this pin is initialized to 18 pins. If the TOC1 or TOC0 bit in the timer control register (TCR) is set to 1, the TOUT function is selected. If the toc1 and toc0 bits are cleared to 0, the A18 function is selected.
During CKa0/Drake0 reset, this pin is initialized as the CKa0 pin.
If dm1 or sm1 in the dma mode register (dmode) is set to 1, the DREQ0 function is always selected.
When CKA1/Trend 0 is reset, this pin is initialized as the CKA1 pin. If the cka1d bit in the asci control register ch 1 (cntla1) is set to 1, the Tend0 function is selected. If the cka1d bit is set to 0, the CKA1 function is selected.
RXS/CTS1 type During reset, this pin is initialized as rxs pin. If the CTS1E bit is in the ASCI status register, ch 1 (stat1) is set to 1, and the cts1 function is selected. If the cts1e bit is 0, the rxs function is selected.
Z 8018X Home Manual Model UM005001-ZMP0400 Programmable Reload Timer (PRT, 2 Channels)
• Clock Serial I/O (CSIO) channel.
Other Z8x180 family members (such as Z80183, Z80S183, Z80185/195) in addition to these modules also include other peripherals and clock generators in the relevant product specifications. The logic is input from an external crystal or clock. The external clock is divided by 2 and provided to both internal and external devices.
Bus Status Controller This logic performs all relevant status and bus control activities with the CPU and some on-chip peripherals. This includes wait state timing, reset cycles, DRAM refreshes, and DMA bus swaps.
Interrupt Controller This block monitors and prioritizes various interrupts and traps, both internal and external, to provide proper responses from the CPU. To remain compatible with the Z80 CPU, there are three different interrupt modes supported.
The memory management unit mmu allows the user to map the memory used by the cpu (logically only 64K) into the 1MB addressing range supported by the Z8x180. The organization features of this mmu object code are compatible with the z80 CPU, while providing access to the extended memory space. This capability is accomplished through the use of effective common area library areas.
UM005001-ZMP0400 type central processing unit
The CPU is microcoded to provide object code compatible cores using the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply and divide. This core has been enhanced to allow many instructions to execute in fewer clock cycles.
DMA controller
DMA controller in memory and I/O devices. The supported transfer operations are memory to memory, memory to/from I/O and I/O to I/O. The supported transfer modes are Request, Burst, and Loop Steal. DMA transfers can access the full 1MB addressing range with block lengths up to 64KB and can cross over 64K boundaries.
The asynchronous serial communication interface asci logic provides two independent full duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. asci channels can also support multiprocessor communication formats.
Programmable Reload Timer (PRT) This logic consists of two independent channels, each containing a 16-bit counter (timer) and count reload register. The time base of the counter is reaching the counter. PRT channel 1 provides an optional output that allows waveform generation.
Clocked Serial I/O (CSIO) The CSIO channel provides a half-duplex serial transmitter and receiver.
This channel can be used for a simple high-speed data connection to another microprocessor or microcomputer

CPU timing • Instruction (opcode) fetch timing • Operand and data read/write timing • I/O read/write timing • Basic instruction (fetch and execute) timing • Reset timing • BUSREQ/BUSACK bus exchange timing Basic cpu An operation consists of one or more machine cycles (mc).
A machine cycle consists of three system clocks: T1, T2, and T3, which access memory or I/O, or a system clock (T1) that consists of CPU internal operations. The system clock is a crystal oscillator (ie, an 8 MHz crystal produces 4 MHz or 250 nanoseconds).
For connecting slow memory or peripherals, an optional wait state (TW) can be inserted between T2 and T3.
The fetch time country that the instruction (opcode) does not wait for. when the m1 output pin is low.
In the first half of T1, the address bus (a0–a19) is controlled by the contents of the program counter (PC). This address bus is the address output of the Z8x180 on-chip MMU.
In the second half of T1, MREQ. (memory request) and rd (read) signals are asserted low, enabling memory.

When the MMU and reset are reset, all bits of the CA field of CBAR are set to 1, and in the ba field of all bits cbar, cbr and bbr are reset to 0. The logical 64KB address space corresponds directly to the first 64kb 0000h to ffffh) 1024kb00000h. to fffff h) physical address space. Therefore, after reset, the Z8x180 starts executing at logical and physical address 0.
mmu register access timing When data is written to CBAR, CBR, or BBR, the value is valid from the cycle immediately following the I/O write cycle that updates these registers.
During mmu programming, make sure that the execution of the cpu program is not interrupted. The next cycle after programming the mmu register is usually to get the opcode from the newly translated address. One technique is to localize all mmu programming routines to regions that are always enabled.

physical address generation