feature

Provides the best backup power in the industry Under 10 MW; much lower than ENERGY STAR 5 star (<30MW) The constant current control frequency of the secondary feedback circuit is 85kHz The fixed pulse width modulation frequency hopping method solves the problem of electromagnetic interference Low operating current: 3.5mAcv regulation in the peak current mode control cycle by cycle current limiting Latch Mode) VDD Under Voltage Lockout (UVLO) Maximum Voltage Clamp at 15V Gate Output Fixed Over Temperature Protection (Latch Mode) Available in 8 Lead SOIC Package

application

Cell phone battery chargers, cordless phones, PDAs, digital cameras and power tools. Replacement of linear transformers and RCC switching power supplies.

illustrate

This highly integrated PWM controller, the FAN302HL, provides some performance-enhancing features for a typical flyback converter. Constant current control, proprietary topology, simplifies the design of battery charging applications without secondary feedback circuits. A proprietary Burst Mode feature of low operating current minimizes standby power consumption. The FAN302HL controller also provides protection measures. The circulating current limit ensures a fixed peak current limit level even if a short circuit occurs. The gate output is clamped at 15V to protect the power mos under high gate-source voltage conditions. If the vs ovp or internal otp is triggered, the circuit goes into latch mode until the AC power is disconnected. With the fan302hl, it is possible to use conventional designs or linear transformers with fewer external components and at the lowest cost in comparison. A typical output Cv/Cc characteristic is shown in the figure.

Operating Instructions: Constant voltage regulation operation FAN302HL is a high frequency ultra-low standby constant voltage constant current power integrated circuit (cc) regulation. When the FAN302HL operates under Cv regulation, the feedback voltage (VFB) acts as the output load and regulates the PWM duty cycle as shown, resulting in a fixed switching frequency (85kHz). Once vfb falls below vfb-g, frequency hopping is disabled and operating current is reduced.

Constant Current Regulation Operation During CC operation, a proprietary Primary Side Regulation (PSR) topology simplifies circuit design for battery charger applications without secondary feedback circuits. cc regulation via psr This technique uses a mixed-signal algorithm to sense the primary current and calculate the average secondary current through the primary auxiliary winding. The figure shows the basic circuit diagram of a flyback converter with typical waveforms as shown. In general, discontinuous conduction mode (DCM) operation is preferred for constant current control as it allows for better output regulation. The principle of the surgical DCM flyback converter is: During the mosfet turn-on time (ton), the input voltage (vdl) is applied to the primary side inductor (lm). Well, the mosfet current (ids) goes from zero to peak value (IPK). During this time, energy is absorbed from the input and stored in the inductor. When the mosfet turns off, the stored inductance forces the rectifier diode (D) to turn on. When the diode is conducting, the output voltage (VO) along with the diode forward voltage drop (VF) is applied to the secondary side inductor (lm × ns2 new product 2) The diode current (id) from the peak value (ipk × np/ns) zero. Inductor end current discharge time (TDIS), stored in the inductor has been sent to the output. When the diode current is zero, the voltage drop is fast: if it is greater than the VVS offset drop, the IC gets TDIS for CC regulation. The output voltage and diode forward voltage drop during the inductor current discharge time is (VO+VF)nA/ns reflected to the auxiliary winding side. This voltage signal is related to the secondary winding. In constant current output operation, this voltage signal is regulated by a precision constant current controller. On determines the timing of the mosfet to control the input power and provide constant current output characteristics. The controller obtains power through the current sensed feedback voltage VCS resistor. Therefore, the output operation in the constant current region can be adjusted by the current sensor, as shown in Equation (1). During CC regulation, the VS voltage decreases with the output voltage. The switching frequency decreases linearly with voltage from fosc to fosc ccm from VSN-CC to VSG-CC. The graph shows the relationship between frequency and voltage. Number 28 shows the output vi curve and vs voltage.

The high voltage startup diagram shows the FAN302HL application. The high voltage pin is connected to the line input through a resistor or bulk capacitor. At startup, the internal startup circuit is enabled and the line input supplies current, IHV, to charge the hold capacitor, CVDD, through Rstart. When the VDD voltage reaches VDD-ON, the internal high voltage startup circuit is disabled, preventing IHV from flowing into the high voltage pins. Once the IC is turned on, CVDD is the only energy supply for the IC to consume current before the PWM starts to switch. Therefore, CVDD must be large enough to prevent VDD from powering down until VDD-off can be delivered from the auxiliary winding.

Frequency hopping EMI reduction is achieved by frequency hopping, which spreads energy over a wider frequency range than the measured bandwidth of EMI testing devices. The internal frequency hopping circuit of fan302hl changes the switching frequency between 82kHz and 88kHz and one cycle, as shown in the figure.

Burst Mode Operation The power supply enters a "Burst Mode" condition at no load. As shown, when VFB falls below VFBL, the PWM output turns off and the speed at which the output voltage falls depends on the load current. This raises the feedback voltage. Once VFB exceeds vfbh, the internal circuitry begins to provide switching pulses. Then the feedback voltage drops and the process repeats. Burst Mode operation alternately enables and disables switching MOSFETs, reducing switching losses in standby mode.

Working current The typical working current is 3.5mA. This low operating current improves efficiency and reduces the vdd holding capacitor requirement. Once FAN302HL enters burst mode, the working current is reduced to 200μA, so that the power supply can meet the energy saving requirements. The gate output FAN302HL BiCMOS output stage is a fast compound gate driver. Avoiding cross conduction reduces heat dissipation, improves efficiency, and improves reliability. The output driver is protected by a Zener diode inside the power mosfet gate signal transistor against overvoltage. The induced voltage on the slope-compensated current sense resistor is used for current mode control and pulse-by-pulse current limiting. Built-in slope compensation, a synchronous positive slope ramp is built into each switching cycle, improving stability and preventing sub-harmonic oscillations due to peak current mode control. Constant power mode control When vs is lower than vs-cm-min, fan302hl enters constant power mode control, the primary side current limit voltage (VCS) is changed from VSTH to VSTH-VA to avoid false sampling by zero current detection vs (ZCD) . Once vs is higher than vs-cm-max, vcs goes back to VSTH. Protection FAN302HL's self-protection features include VDD over-voltage protection (vdd ovp), internal over-temperature protection (otp), US over-voltage protection (VS ovp), current cutout protection and pulse-by-pulse current limit. vdd ovp protection is implemented as automatic restart. Fashion. Once something unusual happens, the switch terminal and mosfet stay off, causing the vdd to be a drop. When the VDD drops to the VDD shutdown voltage of 5V, the internal start-up circuit is activated, and the current drawn from the high voltage pin charges the capacitor. When VDD reaches 16V, FAN302HL resumes normal operation. In this mode, auto-restart alternates the switches enabling and disabling the mosfet until the anomaly has been eliminated (see figure).

vs ovp and internal otp protection is implemented as latch mode. If an abnormal condition occurs, the PWM switch is terminated and the mosfet remains off. In this case, VDD drops, but keeps working as auto-restart (VDD auto-restart behavior does not trigger PWM). The FAN302HL goes into latch mode, disables the pwm switch of the mosfet until vdd is below VDD-LH (AC power disconnected), and powers up again to resume normal operation (see picture).

vs over voltage protection (ovp) vs over voltage protection against over voltage conditions due to output. Figure shows the ovp protection method. When a system abnormality occurs that causes Vs to exceed 2.8V, after the debounce time period; PWM is disabled FAN302HL enters latch mode until VDD drops to the left side of undervoltage VDD-. By that time, PWM resumes. VS overvoltage conditions are usually caused by an open feedback loop or abnormal behavior of the VS pin voltage divider resistor.

vdd overvoltage clamp VDD overvoltage protection against overvoltage conditions due to overvoltage. When the VDD voltage exceeds 26.5V due to abnormal conditions, the PWM pulses are disabled until the VDD voltage drops below UVLO, and then starts again. Overvoltage conditions are usually caused by open feedback loops. Over-Temperature Protection (OTP) FAN302HL temperature sensing circuit shuts down output PWM (total) if junction temperature exceeds 140°C. PWM is disabled before the VDD voltage drops below VDD-LH. Leading Edge Blanking (LEB) Every time the power mosfet is turned on, a spike occurs at the sense resistor. To avoid premature switching pulse termination, the leading edge 350ns blanking time is built-in. The conventional RC filter canister is therefore omitted. During the blank period, the current limit comparator is disabled and cannot switch the gate driver. Undervoltage lockout (UVLO) turn-on and turn-off thresholds are fixed internally at 16V and 5V, respectively. During startup, the capacitor must be charged to 16V through the startup resistor to enable the fan 302HL. The capacitor continues to supply VDD until the auxiliary winding of the main transformer can be powered. The video monitor must not drop below 5V during this startup. This uvlo hysteresis window ensures that the hold-up capacitor is sufficient to provide VDD during startup. Noise immunity Current induced or control signal noise causes significant pulse width jitter, especially in continuous conduction mode. Precautions should still be taken when slope compensation helps further alleviate these problems. Good placement and layout practices should be followed. Avoid long PCB traces and component leads, position compensation and filter assemblies near fan 302HL, and recommend increasing power mos gate resistors.