LMX2335 1.1 Giggami Hhe/1.1 Giggami H He

lmx2336 2.0 Giggami Hhe /1.1 Gigga H He

lmx2337 550 MM/550 MPA ] LMX2335, LMX2336, and LMX2337 are single -chip integrated dual -frequency synthesizers, including two high -frequency pre -scorers, which are designed to use applications that require two RF locks. They are the national Abic IV silicon BICMOS process. LMX2335/36/37 contains two dual -mode pre -scorers. You can select 64/65 or 128/129 pre -scoreter synthesizer for each RF. The second reference partition includes an integrated circuit that improves systemic noise. LMX2335/36/37, which uses digital lock ring technology, combined with a high -quality reference oscillator and ring circuit filter to provide a very stable low noise radio frequency vibration signal generated by the voltage control oscillator. Serial data is transmitted to LMX2335/36/37 wired interface (data, enable, clock). The range of power voltage from 2.7V to 5.5V. LMX2335/36/37 is characterized by low -current consumption; at 3V, LMX2335/37 10 ma, LMX2336 13 ma, 3V voltage. LMX2335/37 can be installed with plastic parcels on Jedec SO and Tssop 16 -pin surface. LMX2336 uses TSSOP 20 stitching plastic packaging.

Features

2.7V to 5.5V operation

Low -current consumption

Optional power off mode: ICC u003d 1 μA (typical value)

Dual-mode pre-scoring device: 64/65 or 128/129

optional charge pump Tri-State #174; mode

Optional charge pump current level

Optional fast lock #8482; mode

Application

Honeycomb telephone system (AMPS, ETAC, RCR-27)

DECT, ISM , PHS, CT-1+)

Personal communication system (DCS-1800, PCN-1900)

dual-mode PC phone

Cable TV

Other wireless communication systems

Note: VCC1 is powered by the RF1 pre -scorer, N counter, R counter, and phase detector. VCC2 preview to RF2Frequency division, N counter, phase power supply detector, R-counter and OSCIN buffer, microwir

Absolute maximum rated value (Note 1, 2)

If you need military/aerospace dedicated Equipment,

Please contact the National Semiconductor Sales Office/

The availability and specifications of dealers.

Power voltage

VCC 0.3V to+6.5V

vp 0.3V to+6.5V

Any pins on any pin Voltage

ground u003d 0V (vi

)-0.3V to VCC+0.3V

Storage temperature range (TS) 65 ° C to +150 ° C

Lead temperature (4 seconds) (TL)+260 ; C

Suggesting

Condition

Power voltage

VCC 2.7V to 5.5V

VP VCC to+5.5V

Work temperature (TA) 40 ° C to+85 ° C

Electrical characteristics

VCC u003d 5.0 volts, VP u003d 5.0 volts; TA u003d 25 degrees Celsius, unless there are other regulations

Electric characteristics (continued)

VCC u003d 5.0 volts, VP u003d 5.0 volts; TA u003d 25 degrees Celsius, unless there are other regulations

Note 1: Absolute maximum rated value indicates that the device may be damaged by the device that may be damaged by the device that may be damaged by the device. The limit value. The proposed operating conditions indicate that the device is designed to play a function, but does not guarantee specific performance restrictions. Please refer to the electrical characteristics about the specifications and test conditions of the guarantee. The guarantee specifications are only applicable to the test conditions listed.

Note 2: This device is high -performance radio frequency integrated circuit, ESD rated value lt; 2 KEV, sensitive to ESD. The handling and assembly of this device are carried out in the anti -static workstation.

Note 3: ICPO description see programming mode.

Note 4: clocks, data and les do not include Fin1, Fin2 and OSCIN.

Typical performance characteristics (continued)

Label 1 u003d 1 gHz, real number u003d 94, virtual value u003d 118

[123 ] Label 2 u003d 1.2 GHz, real number u003d 72, virtual value u003d 88

LabelRemember 3 u003d 1.5 GHz, real number u003d 53, virtual value u003d 45

Mark 4 u003d 500 mHz, real number u003d 201, virtual value u003d 224

Tag 1 1 u003d 1 gHz, real u003d 97, virtual u003d 146

Mark 2 u003d 1.89 gHz, real number u003d 43, virtual value u003d 67

Mark 3 u003d 2.5 gHz, real number u003d 30 , Virtual value u003d 33

Mark 4 u003d 500 mHz, real number u003d 189, virtual value u003d 233

Function description

The simplified frame diagram below shows 22 -bit data registers, two 15 -bit R counters, and two 18 -bit N counters (the middle lock is not displayed). The data stream is entered into the data register by the clock (at the rising along the clock), and MSB is preferred. The stored data is loaded to one of the 4 appropriate locks on the rising edge of the LE in the shift register. The last two are the control level. The data is transmitted to the counter in the following way:

Aeraable reference pressure division (RF1 and RF2 R counter)

If the control bit is 00 or 01 ( RF2 is 00 and RF1 is 01), then the data is transmitted from 22 -bit displacement register to a 15 -bit R counter. The serial data format is shown below.

Note: The prohibited division ratio is less than 3.

Diversion ratio: 3: 32767

R1 to R15: These positions select the frequency ratio of programmable reference frequency division.

The data is first shifted in MSB.

Function description (continued)

A programmable divider (n counter)

Each N counter is a 7 -digit swallow counter (A counter) and 11 -digit programmable can be programmable The counter (B counter) is composed. If the control position is 10 or 11 (10 for the RF2 counter, 11 for the RF1 counter) data is transmitted from 20 displacement registers to 7 -bit locks (setting swallow (A) counter) and 11 -bit locks (settings settings 11 -bit programmable (B) counter), MSB is preferred. The serial data format is shown below.

注：分流比：3～2047（禁止小于3的分流比）

脉冲吞咽功能

fVCOu003d[（ P x b)+A] x fosc/r

FVCO: output frequency of external pressure control oscillator (VCO)

b: binary 11The preset division ratio of the programmable counter (3 to 2047)

A: The preset frequency ratio of the 7 -bit swallow counter (0 ≤A≤P; a≤b)

FOSC: The output frequency of the external reference frequency oscillator

R: The preset division frequency of the 15 -bit programmable reference counter (3 to 32767) of the binary Preset mode (P u003d 64 or 128)

Available mode

A variety of operating modes can be used in R16 – R20 programming, including the polarity of the phase detector, the three state of charge pumps, and folding folding The output of the needle. Use bits N19 and N20 to select the premature frequency and power off mode. The programmable mode is shown in Table 1. The programming mode and folding output are shown in Table 2 and 3.

Note 5: ICPO low current status u003d 1/4 x ICPO large current.

Note 6: Activating RF2 PLL or RF1 PLL power off mode will cause the corresponding N counter removal and make their respective FIN inputs (high impedance status). The power -off function is selected by the charge pump to prevent unnecessary frequency jump. Once the power -off program mode is loaded, the component will enter the power -off mode when the charge pump reaches a three -state state. The R counters and oscillator functions are disabled before RF2 and RF1 potential activation. Oscin is connected to VCC through 100 k #8486; the resistor is connected to the VCC. When the condition exists, OSCIN becomes higher. Microwire controls the activation state and can load and lock data in all power -off modes.

Note 7: Phase detectors should be set according to the characteristics of VCO: When the characteristics of the voltage control oscillator are positive (1), the R16 should be set as a high -duty VCO characteristic such as (2) When negative, the R16 should be set to low.

Function description (continued)

Note 9: When the folding output is disabled, it is actively pulled to the low logic state.

Note 10: Lock the detection output to indicate when the VCO frequency is in a ""lock"" state. When the ring is locked and selected to lock the detection mode, the tube foot has high output and low narrow pulse. In the RF1/RF2 lock detection mode, when RF2 and RF1 are locked, the indicator locks the state.

Note 11: Fastlock mode uses a folding output pin during FastLock to switch the second ring filter damping resistor to ground. Activate FastLock when the ICPO amplitude point of the RF ring is selected as high (and the#19 and#20 mode bits are set to FastLock).

Note 12: The counter reset mode bit RAt the time of 19 and R20, all counter is activated. After removing the reset position, the n counter continues to count the count with the R counter in the ""closed"" state. (The maximum error is a pre -scoring cycle). If the reset is activated, the R counter will also be forced to reset, allowing smooth communication and collection during power power.

Note: The data in parentheses indicates a programmable reference pressure divider data.

The data is moved into the register along the clock rising along. Data is first shifted in MSB.

Test conditions: Use the symmetrical waveform of the VCC/2 to test the serial data input timing of the serial data. The edge rate of the test waveform is 0.6V/ns2.2v@vccu003d2.7V and 2.6v@vccu003d5.5V.

Operation description:

1. The pressure -controlled oscillator assumes AC coupling.

2.RIN increases impedance, so that VCO output power is provided to the load instead of PLL. The typical value is 10 #8486; to 200 #8486; depending on the VCO power level. The scope of the finite frequency of the fin is 40 #8486; to 100 #8486;. If the impedance is large, it is fin.

3.50 #8486; Terminals are usually used on the test board to allow external reference oscillator. For most typical products A, the CMOS clock is used without the need to connect resistance. OSCIN can be communicated or DC coupling. It is recommended to use AC coupling because the input circuit provides its own bias. (See below).

4. It is recommended to add RC filters on the VCC line to reduce noise coupling from the ring to the ring.

Application Tips:

123] Correct use of grounding and bypass containers is the key to achieving high levels of performance. Be careful board can reduce the string layout between the pins. This is a static sensitive device. It can only be handled on a non -static workstation.

Application information

The frame diagram of the basic lock ring is shown in Figure 1.

Application information (continued)

The loop gain equation

Phase feedback linear control system model locking PLL as shown in Figure 2 Show. Open -loop gain is the pursuit VCO gain (KVCO/s) of the phase comparator gain (K board), and the loop filter gain Z (s) is divided by the feedback counter mold gain (N). The configuration of the passive cycle filter is shown in Figure 3, and the recurrence of the filter is shown in

From the equation (3), it can be seen that it can be seen , Phase item is not related to the single pole and zero, so the phase of the phase of the phase is based onProgram (5) OK. φ (ω) u003d TAN 1 (ωt2) Tan 1 (ωt1)+180 ; C

The size of G (s) h (s) of stability With the phase diagram loop, as shown in Figure 4, with a real tracking. The parameter φp indicates that the amount of phase habum in this point drops below zero (deeper frequency WP cycle). In the critical damping system, the edge of the phase amount is about 45 degrees. If we now redefine the deadlines wp #39; double the frequency of our original ring bandwidth WP, the response time of the ring circuit is about half. Due to the decrease in the attenuation at the frequency of comparative frequencies, the bruises will increase by about 6 decibels. In the proposed FastLock scheme, there will be higher bandal electricity and wider loop filter conditions. Only in the initial lock-as long as it takes a long time to get the benefits of locking faster. The goal is to open the loop bandwidth, but does not introduce any additional bandwidth to complicate or compromise standards related to our original design. Ideally, we hope to temporarily change the curve chart 4 to switch to different cut -off frequencies. From the dotted line, it does not affect the relative opening gain and phase relationship. Maintain the same gain/phase relationship gain and phase equation at twice the frequency of the original deadline (5), (6) to use the corresponding ""1/W"" or ""1/W2"" to compensate ""factor. Examination formula (3) (4), (5) indicate that the damaged resistance variable R2 can be selected to use the ""W"" item to compensate the phase of the phase. This means that another equal resistance is in the initial lock period. G (s) is equivalent to zero u003d work package 2. KVCO, K board, n or these terms can be a change factor 4 to offset the nominance of W2 items (3) and (4). K φ is selected to complete the conversion because it can be easily switched between 1x and 4X values. This is 1 ma to 4 mA in the standard mode by increasing the output current of the charge pump. ] Quick -locking circuit implementation

FIG. 5 shows the schematic diagram of the FastLock scheme implemented in the sodium semiconductor LMX2335/36/37 PLL. Then the charge pump circuit receives an input, so that the phase error per unit of each unit is 4 times the normal current in the second R2. It should be considered. The equipment configuration ensures that as long as the second same damping resistor is properly wirled, the ring is locked faster without considering any additional stability factors. The lock -up loop is restored to standard low noise settings with the RF1 ICPO bit. This conversion will not affect the charging on the loop filter capacitor and synchronize with the charge pump output.Seamless switch between lock and standard mode