General Instructions
The Z86129 / 130 /131 is a self-contained integrated circuit capable of processing Vertical Blanking Interval (VBI) data from two fields of a video frame in compliance with the transmission format defined in the Television Decoder Circuits Act of 1990 and the electronics industry Association Specification 608 (EIA-608).
The line 21 data stream may consist of data from multiple data channels multiplexed together. Field 1 has four data channels, two headers, and two texts. Field 2 has five additional data channels, two headers, two text and extended data services (xds). The xds data structure is defined in eia-608. The Z86129 can recover and display data transmitted on any of these nine data channels. The Z86130 and Z86131 are derivatives of the Z86129 that can recover XDS data and output the recovered data through the serial port. Z86130 Z86131 does not have OSD capability, but is ideal for 21 row data slicer applications.
The z86129/130/131 can recover and output any xds packet defined in eia-608 over the i2c serial bus. The on-chip XDS filter is fully programmable, allowing only user-selected XDS packets to be recovered, making the z86129/130 ideal for implementing NTSC brute force blocks. The Z86131 is designed to extract xds time information for automatic clock setting functions in TVs, VCRs and set-top boxes.
Also, the z86129/130 is great for monitoring line 21 of the video displayed in the pip window for brute force blocking purposes.

Pin Description Input Video (Pin 7). Composite ntsc video input, 1.0v pp (nom), band limited to 600khz. The circuit will work with signal changes between 0.7-1.4V pp. Polarity is negative for sync tip. This signal pin should be AC coupled through a 0.1µf capacitor and driven by a source impedance of 470 ohms or less.
hin (pin 5). Horizontal sync input for CMOS levels. This signal pulls the on-chip VCO into proper range when the device is used in video lock mode. The circuit uses the frequency of this signal, which must be within ±3%f, but can be of any polarity. When used in H-lock mode, the VCO phase locks to the rising edge of this signal. The hpol bit of the h position register can be set to work with either polarity of the input signal. This is usually the h flyback signal. The time difference between the rising edge of hin and the leading edge of the composite sync (video input) is one of the factors that affects the horizontal position of the monitor. Any shift caused by the timing of this signal can be compensated for by the horizontal timing value in the h-position register. Hour SMS (pin 6). Mode select pin for the serial control port. When this input is in a CMOS high state (1), the serial control port will operate in SPI mode. When the input is low (0), the serial control port will operate in I2C slave mode. In spi mode, the sen pin must be tied high. (See the Reset Actions section.)
sensor (pin 4). Enable signal for SPI mode operation of the serial control port. When this pin is low (0), the SPI port is disabled and the SDO pin is in a high impedance state. Transitions on the SCK and SDA pins are ignored. When short message is high (1), SPI mode operation is enabled.
SCK (pin 15). Input pin for the serial clock signal of the master device. In I2C mode, clock rates are expected to be within I2C limits. In SPI mode, the maximum clock frequency is 10 MHz.
reset operation. When both the SMS and sensor pins are in the low (0) state, the part will be in reset. So in i2c mode, the sen pin can be used as nreset input. When using spi mode, if three-wire operation is required, both sms and sen can be tied together and used as nreset input. In either mode, nreset must be held low (0) for at least 100 ns.
Input/Output VIN/Profile (pin 13). In the external (external) vertical lock mode of operation, the internal vertical sync circuit will lock to the VIN input signal applied on this pin. The part will latch to the rising or falling edge of the signal according to the setting of the V polarity command. The default value is "rising edge". The VIN pulse must be at least 2 lines wide.
In profile mode, when configured for internal vertical synchronization, this pin will be an output pin that provides an interrupt signal to the host control device according to the settings in the interrupt mask register.
SDA (pin 14). When the serial control port is set to operate in I2C mode, this pin acts as a bidirectional data line for sending and receiving serial data. In spi mode it works as serial data input. SPI mode output data is available on the SDO pin.
output
SDO (pin 16). Serial data output is provided when SPI mode communication is selected. This pin is not used for I2C mode operation.
Box (pin 17*). The black box keying output is an active high CMOS level signal used to input the black box in the subtitle/text display. When the background property is set to translucent (Z86129 only), this output will be in a high impedance state.
Red, Green, Blue (pins 2*, 3*, 18*). Positive-acting CMOS level signal (Z86129 only).
Color Mode: Red, green, and blue character video output for color receivers.
Mono Mode: All three outputs carry character brightness information.
NOTE: The selection of color/mono mode is controlled by the user in bit d (address = 00h) of the configuration register. (See the Internal Registers section.)
Pins with external components
C Sync (Pin 8). Sync slice level. A 0.1µF capacitor must be connected between this pin and analog ground vss(a). This capacitor stores the sync chip level voltage.
LPF (pin 9). loop filter. A series rc low pass filter must be connected between this pin and analog ground vss(a). There must also be a second capacitor from the pin to vss(a). The values for the three parts will be specified later.
RREF (Pin 10). Refer to setting resistors. Resistors must be 10k ohms, ±2%.
power supply
V (pin 12). Due diligence The voltage on this pin is nominally 5.0 volts, relative to the vehicle speed sensor pin, it could be between 4.75 and 5.25 volts.

Z86129/130/131 block diagram description
vss (pins 1, 11). These pins are the lowest potential power pins for analog and digital circuits. They are usually tied to system ground. NOTE: Recommended printed circuit diagrams for implementing power connections and critical components will be provided later.
The z86129 is designed to handle both fields of line 21 of TV vbi and provides the functional capabilities of line 21 closed caption decoder and extended data services decoder. It requires two input signals, composite video and a horizontal timing signal (hin), and several passive components to function properly. If the OSD display mode is required in the absence of a video signal, the vertical input signal is also required. The decoder performs several functions, namely extracting data from line 21, separating normal line 21 data from xds data, on-screen display of the selected data channel (z86129 only), and outputting the xds data over the serial communication channel.
Input Signal The composite video input should be a signal, nominally 1.0 volts pp, with a negative sync tip and a band limited to 600 kHz. The Z86129 will operate with a ±3dB change in input level.
A HIN input signal is required to bring the VCO close to the desired operating frequency. It must be a CMOS level signal. The hin signal can have positive and negative polarities and is only required to be within 3% of the standard h frequency. When configured for ext hlk operation, this signal should correspond to the h flyback signal.
The time difference between the rising edge of hin and the leading edge of the composite sync (video input) is one of the factors that affects the horizontal position of the monitor. Any shift caused by the timing of this signal can be compensated for by the horizontal timing value in the h-position register.
Video input signal processing
The comp video input is ac-coupled to the sync terminal via a double-clamped device internally clamped to a fixed reference voltage. Initially, a simple clamp is used to clamp the unlocked signal. Impulse noise performance is improved after the internal synchronization circuit locks to the input signal. Noise rejection is achieved by making the clamp work only on the sync tip. The clamped composite video signal is fed to the data slicer and sync slicer blocks.
The data slicer generates clean cmos-level data signals by slicing the midpoint of the signal. During Line 21, slice levels were established on an adaptive basis. The resulting value is stored to the next occurrence of row 21. A high level of noise immunity can be achieved with this process.
The sync slicer processes the clamped comp video signal to extract the comp sync. This signal is used to lock the internally generated genlock to incoming video when the video lock mode of operation is enabled. Synchronous slicing is performed in two steps. In unlocked mode, sync will slice at a fixed offset level from the sync hint. When correct locking operation is achieved, the chip level voltage is switched from a fixed reference level to an adaptive level. The chip level is stored on the synchronous chip capacitor csync.
The data clock recovery circuit works in conjunction with the digital h-lock circuit. They generate a 32h clock signal (dclk) that is locked in phase with the clock run burst portion of the sliced data obtained from the data slicer. When line 21 appears, dclk phase locking is achieved during burst clock operation and is used to relock slice data. Once phase lock is established, it will remain until the video signal changes.
The digital h-lock circuit generates video timing gates, pg, stg, etc., which are synchronously locked with the video timing signal hsync, no matter what h-lock mode is used in the display generation circuit. This self-contained phase-locked loop responds quickly to changes in video timing regardless of display stability requirements.

Z86129/130/131 Block Diagram Description (continued)
The VCO and one-time all internal timing and synchronization signals are derived from the onboard 12 MHz VCO. Its output is the dot CLK signal used to drive the horizontal and vertical counter chains and display timing. The single shot circuit generates a horizontal timing signal derived from the incoming video and defined by the copy protection logic circuit.
The VCO can be genlocked to two different sources. For TV operation, in the presence of a good level display timing signal, the VCO is locked to the HIN input by the action of the phase detector (PH2). When there is no suitable HIN signal, such as in VCR, VCO can lock to incoming video via a phase detector (PH1). In this case, the frequency detector (FR) circuit is activated as needed to keep VCO within the pull-in range of Ph1.
The timing and counting circuit first divides the point clk down to generate the character timing clock char clk. This signal is then further divided to generate horizontal timing signals h, 2h and hsqr. These timing signals are used in the data output (display) circuits.
The h signal is further divided in the line and fld cntr to generate the various decodings used to establish vertical lock and time the display and control functions required for proper operation. The h signal is also used to generate a smooth scroll timing signal for display.
The v-lock circuit produces noise-free vertical pulses derived from the horizontal timing signal. When the user selects video as the vertical lock source, the internal sync signal and the input video are progressively amplified by comparing the internally generated vertical pulse with the input vertical pulse derived from the comp sync signal provided by the sync slicer. In vertical lock set to VIN mode, the VIN signal is used in place of the signal obtained from the compressor synchronization. In both cases, when the proper phase is established, the circuit outputs a lock signal that is used to provide additional noise immunity to the slicing circuit.
The locked state is established only after several consecutive fields in which the two vertical pulses remain synchronized. Once locked, the internal timing will flywheel until the two vertical pulses lose alignment, one of the few consecutive fields. The decoder works pulse-to-pulse until a lock is established.
The command processor commands the processor circuit to control the operation of the data for storage and display. It handles control port input commands to determine the desired display state and the selected data channel. During display (lines 43-237), this information is used to control the loading, addressing, and clearing of display RAM and the operation of character ROMs and output logic.
During the data recovery time (TV lines 21-42), the command processor works with the data recovery circuit to recover the xds data and the data for the selected data channel. Data is sent to ram for storage and display, and/or to the serial port (as the case may be). When necessary, the command processor converts the input data to the appropriate format.
Output logic (Z86129 only)
The output logic circuits work together to produce the red, green and blue output color signals and the box signal. When monochrome mode is selected, all three color outputs will carry luminance information. These outputs are positive output logic signals.
The character rom contains the dot pattern of all characters. The output logic provides hardware underline, graphic character, and italic generation circuitry. Smooth scroll display is achieved by smooth scroll counter logic that controls addressing of character roms.
Decoder Control Circuit The decoder control circuit block is the user communication port. It converts the information provided to the control port into the internal control signals needed to establish the working mode of the decoder. This port can operate in one of two serial modes. The sms pin is used to establish the serial control mode to be used.
In two-wire (I2C) control mode, the Z86129/130/131 will respond to the slave address under read and write conditions. If the read bit is low (indicating a write sequence), the z86129/130/131 will respond with an acknowledge. The host should then send an address byte followed by a data byte. If the read bit is high (indicating a read sequence), the z86129/130/131 will respond with an acknowledge, followed by a status byte, then a data byte. The read data can only be obtained by indirect addressing. Write addressing will have both indirect and direct modes. The busy bit in the status byte will indicate whether the write operation has completed or the read data is available.
The spi mode is a three-wire bus with the z86129/130/131 acting as slaves. Communication is synchronized by the sck signal generated by the host. Typically, serial data output is sent on the falling edge of sck and received data is captured on the rising edge of sck. All data is exchanged in 8-bit bytes.
Voltage/Current Reference The voltage/current reference circuit uses externally connected resistors to establish the reference levels used in the z86129/130/131. Use external resistors to improve internal accuracy with minimal additional cost.
Z86129/130/131 function description
The Z86129 offers full-featured NTSC, 21-gauge performance. Include input commands to enable the decoder to process and display the eight subtitle/text data channels (cc1, cc2, cc3, cc4, t1, t2, t3, or t4) contained in line 21 of any field of the input video any of the . You can also select xds data for display. The decoder on/off command controls whether line 21 data in the selected channel is actually displayed. When switching to the decoder off (TV) state, incoming data in the selected channel will still be processed but not displayed.
The z86129/130/131 can also be configured to operate with pal or secam video signals. It will decode the information encoded into the vbi on line 22. The encoded data must conform to the waveform and command structure defined for the ntsc line 21 operation.
VCO Lock This design includes a stable gain characteristic and good power supply rejection of the VCO. Internal horizontal and vertical synchronization circuits provide a high degree of noise immunity. There are options for horizontal and vertical locking. The VCO can be phase locked to a horizontal signal derived from the video input signal (video) or an externally supplied hin signal, usually a horizontal flyback.
The hin lock is used to provide a display with minimal observable jitter. This requires a hin signal with the proper polarity obtained from the TV monitor. Such signals are readily available in television receivers. Video lock mode enables the VCO to lock in phase with the incoming video signal, providing good operation in applications where there is no display-related hin signal, such as in a VCR.
Video Timing Timing signals come from the VCO for line counting and display circuits. Line counting requires correct identification of the vertical pulses of the incoming signal. The default operation uses a vertical sync signal derived from the video input signal as the source for vertical lock. This method has good locking performance and anti-noise performance.
If OSD operation is required without input video, the Z86129 needs to be set to VIN lock. In this mode, the vertical timing will be determined by the vertical pulse signal supplied to the VIN pin.
The horizontal position of the subtitle display is determined by an internal timing circuit. A default condition has been established that will result in a centered display in a typical application. However, since the signal delay through the video processing circuitry can vary between designs, the z86129 provides the user with the ability to change the default timing. Regardless of the horizontal lock mode selected, the display horizontal position on the screen can be adjusted in quarter-character (330ns) steps via serial port commands.
Displayable character set (Z86129 only)
normal mode. Characters appear as white or colored dot matrix characters on an opaque background. The box is usually black, but the Z86129 can be set to a blue background box via serial commands. Characters are described by a 12x18 dot pattern within a character unit that is 16 dots wide by 26 dots high per frame. The position of character brightness in the character unit varies from character to character to allow lowercase and lowercase letters to be displayed. All characters have at least a 1-point black border around each character. Underscore is also provided.
The character rom consists of a 12×18 dot pattern for each character. . Read alternating rows and columns in each field to generate interleaving and rounding characters. The display line contains a maximum of 32 characters plus leading and trailing black boxes, and the width of each character unit makes the overall width of the display line 34×8=272 dots. Consecutive display lines are stitched together so that the total display height is 195 points.
The black box's 34-character cell is 195 dots wide and 195 scanlines high, and its size is 45.018 microseconds. The frame extends from scan line 43 to scan line 237 . In theory, when the box starts 13.2 μs after the leading edge of h, the display will be centered horizontally in the video display.
The Z86129's default settings set the center of the box to about 13.5 microseconds to allow for some delay in the normal video path. However, the horizontal position of the box can be adjusted by the user in 330ns increments. The display will be approximately within the safe header area of the NTSC receiver. The character width is 42.37 microseconds, also centered on the screen, resulting in a black border of 1.32 microseconds.
An optional title display mode drop shadow can be selected by the user via the serial port. This display mode eliminates the black box around the characters and places a 2-dot black shadow to the right and below the character's brightness point in 15-line scan mode. This display mode can be used for title, text and OSD displays.
extensions
eia-608 defines new extended features such as optional background and foreground display attributes and optional extended characters. The Z86129 will always respond to extended characters, but the extended background/foreground response can be controlled by the user. The background and foreground properties add code for the background color, black foreground, and transparent, opaque, and semi-transparent backgrounds. Whenever one of the translucent property codes is active, the box signal output pin will be set to tri-state. External keying circuits can then use this condition to achieve the desired video display.
Accented capital letters are achieved by placing an accent symbol above the character cell. When checked, this mode will cause accent marks to be written in the character cell space on the row above. In some modes of operation, the Z86129 will expand the size of the entire box height by adding two extra scanlines at the top and one at the bottom. This will make room for the accented character on the top line and add a black line below any descendants of lowercase characters on the last line.
This approach is desirable because shrinking capital letters to leave room for accents in character cells degrades character quality, and in some cases there is no distinction between upper and lower case letters. It also has the advantage of minimising the size of the rom and provides a good readable font that closely matches what is usually seen in print.
If an accented uppercase letter on a line collides with a lowercase descending character in the same character position on the previous line, the descending character takes precedence. This approach improves readability compared to contracted capital letters, which far outweighs this potential conflict, and brings a cost-effective compromise in providing a full, expanded feature implementation.
Extended characters share their address space with OSD graphic characters. The extended character set is in effect when displayed with a box. However, graphic characters are valid if displayed with shading. For title and text display modes, if drop shadow is set, the user must also command z86129 to switch back to extended characters.

Text mode display (Z86129 only)
When text mode is selected, a black box is displayed whenever a valid 21st line of code in the selected field is detected. The Z86129 offers the option to make the box blue instead of black. This option applies to titles and text.
The default text display mode uses a black box of 15 lines and 34 characters. Text characters are displayed when they are received from the first line. Consecutive carriage returns will continuously move the display lines down until all 15 lines are displayed. After this, the text will scroll up and new characters will be added to the next line.
If the data of the selected channel is interrupted by a command from another channel, data processing will stop, but the display will remain unchanged. When a resume text command is received, data processing will resume and new characters will be added starting from where the row/column pointer was displayed when data processing was interrupted. If a start text command is received, the display is cleared and new characters are displayed starting at row 1, column 1 (left).
The user can change the number of displayed lines and the position of the text box (base line). In this way, the user can determine the coverage of the screen when non-program related information is displayed.
When scrolling, the display will move one scanline per frame until a full line is scrolled. If a carriage return is received before scrolling is complete, the display will jump over the remaining scan lines, "scrolling" is completed immediately, and new text will begin to appear.
Subtitle mode display (Z86129 only)
According to the fcc specification, subtitle data can appear on any of the 15 display lines, but a subtitle can contain no more than 4 lines. The form in which the subtitles are displayed depends on the subtitle mode indicated by the transmitted subtitle command, pop, draw, or scroll. The Z86129 can display a single title with up to eight lines. When any subtitle display mode is selected, the screen will be transparent. (The display box only appears when the title is displayed.)
Pop-up subtitles have two subtitle memories. One of them is usually displayed and the other is used to accumulate new header data. Pop a new subtitle by swapping these two memories using the End Caption (EOC) command. When screen memory is erased, the screen is blank (transparent), and the memory will default to the row/column pointer, at row 1, column 1, and monochrome without underline.
When subtitle mode is selected, the decoder will process any data after the resume caption loading (rcl) command (or eoc). Typically, this command is followed by a preamble address code (pac) to indicate the row, column, and character attributes to be used with the following data. If no pac is received, the data will be added at the position last indicated by the row/column pointer before the rcl command was received.
The Draw Caption mode is essentially the same as the POPON mode, except that the data received after the Direct Caption (RDC) command is restored is written to the screen memory instead of the off-screen memory. All the rules for pacs, midcodes, etc. are the same.
Roll-up title mode displays a "text"-like display that is limited to 2, 3, or 4 lines depending on the recovery rollup (run) command used. The pac after the run command is used as the base line for the summary display. The base row will be the "bottom" row displayed on scroll up. In this case, the black box only appears when the characters are displayed, and the box is only wide enough to provide leading and trailing boxes on each line. The new data appears on the bottom row, and when each carriage return is received, the row scrolls up and the new data is added to the bottom. When the number of rows indicated by the resume command is reached, the data in the top row will scroll as new data is added to the bottom.
tab(indent)pac allows headings to be placed in any heading line starting from a 4-character boundary. The tab offset command provides a way to adjust the starting position of the header at any column position in the current row.
XDS display mode (Z86129 only)
Two pre-programmed xds display modes are available. One of them provides information on current projects that will be of interest to "River Grazing". The second display shows clear packets and additional xds packets that will inform the viewer program content. Information will be displayed as it is received. The display uses shadow mode with 15 scanlines per line.

Z86129/130/131 Feature Set The following briefly introduces the main features of Z86129/130/131. A more complete description can be found later in this document.
vbi data processing
z86129/130/131 extract data in line 21 of incoming video. All data channels in both video fields are supported. Specifically, the Z86129 can:
Process the data of both fields on line 21 at the same time.
XDS data is output through the serial port when the selected data is displayed.
Output xds data via raw or filtered serial port.
The xds filter can be selected from a list of pre-programmed values, including program nominal and time/local time.
Selectable NTSC or PAL operation.
The data extracted by the z86129 from line 21 of the input video can be displayed in different ways depending on user selection and data type. The Z86129 only provides the following display functions:
10 different 21-line data display modes; CC1-CC4, T1-T4, plus two standard templates for XDS display.
Pop, paint and roll up the subtitle display.
The text display defaults to a full-screen 15-line display.
The user can vertically shrink and reposition the text display as needed.
Color or monochrome display mode is optional.
xdsg display mode (channel clear): Automatically display network name, call letter, program name, program length and time in display packets.
XDSF display mode (full information): Automatically display XDSG display mode information plus: program type (basic type only) and program description.
Universal OSD mode (Z86129 only)
In addition to displaying data extracted from line 21 of the input video, the z86129 can also display information provided through its serial port. This is called the On Screen Display (OSD) display mode. This mode provides:
Programmable full screen OSD: 15 line display
32 Character Columns Graphical Characters Double Height Double Width Characters Fully programmable display positioning; information can be placed anywhere on the screen.
Accept externally provided or internally generated vsync to enable osd even without video.
character set
Z86129 has a new character set with extended features such as: new fonts, lowercase letters down an optional display mode that uses shaded fonts (in other words, stripes appear on each character instead of a solid "black box" background).
EIA-608 Extended Characters
EIA-608 Background and Foreground properties are used for special frames and graphic characters displayed by the OSD.
Double height double width character display for OSD.
Scans 15 lines of OSD and text per character line.
Note: Please contact your nearest Zilog sales office for additional information on how to define custom OSD character sets.
Serial communication interface
Communication and control of the Z86129/130/131 is achieved through the serial control interface. There are two serial control modes available when the Z86129/130/131 operates as a slave device. These modes are:
1. Two-wire I2C interface.
2. A three-wire serial peripheral interface (spi).
3. There are five device pins dedicated to the serial control port function. These pins are designated as:

Z86129/130/131 Feature Set (continued)
When sen is turned high, the parts will sync and wait for commands. If sen is bound high, the part can also be synchronized via the command string. During SPI mode operation, the VIN/Profile signal (pin 13) can be configured to generate an interrupt request to the master on selected events. (See note below.)
NOTE: The part will reset when the sen and sms pins go low at the same time.
Interrupt generation. The VIN/Profile signal (pin 13) can be configured to provide an interrupt output on selected events. The configuration of the VIN/Profile (pin 13) is user programmable and can be in one of two states:
1. Input pin to receive external synchronization timing signal
2. Output pins used to generate interrupts on selected events Note: Configuring the V in/intro as an interrupt-generated output is especially useful when implementing v-chip functionality in TVs and VCRs. In this configuration, pin 13 is used to interrupt the host processor when an xds program rated packet is found. Therefore, the host processor is not burdened with monitoring or filtering the line 21 data stream. The z86129/130/131 filters the line 21 data stream for the host processor and only generates an interrupt when the desired packet is found.
Setup and Operation Controls
The Z86129/130/131 is very flexible and fully programmable through its serial communication port. The following table provides a partial list of user-programmable features, user-selectable display modes, and default conditions upon reset.
Z86129/130/131 Programmable Features – Decoder On/Off – TV Scan Lines (13 or 15) per OSD Row
– EIA-608 Extended Properties On/Off – OSD On/Off Shadows – Color/Monochrome – OSD Horizontal Start Position – Text Box Size (Lines)
– Text box start line position – NTSC or PAL
– Vertical Lock Source: Video or External VIN – XDS Data Output, Raw or Filtered – H Lock Source: Video or External HIN
In addition to the programmable functions just listed, the Z86129 also provides 11 display modes for users to choose from.

Serial Communication Interface (continued)
All write commands to the I2C bus are one- or two-byte commands. The z86129/130/131 is enabled when a START condition is received followed by a slave address write byte. It will be disabled once it thinks the command has completed or a stop condition. A new START condition without a STOP condition will start a new sequence. Thus, consecutive commands can be executed by consecutive strings of "start-slave address command" sequences without sending any intervening stop conditions.
notes:
The number of bytes of data received by the z86129/130/131 is inherent in the command, and the z86129/130/131 will only respond with an acknowledgment for the expected number of bytes. If the master writes more bytes than expected, the extra bytes are not acknowledged.
A status read should always be performed to verify that the z86129/130/131 is not busy before writing to the z86129/130/131. The status register data is output immediately after the slave address read is received. If the rdy bit is set, the master can initiate its write sequence, always starting with a START condition. The first byte of a double-byte command is always written first.
An example of a host sequence to write a double-byte command (after checking RDY) is as follows:
Start slave address write/slave acknowledge command (master)/slave acknowledge data (master)/slave acknowledge stop.
Reading data using the I2C bus With the exception of the serial status (ss) register, which can be read at any time, each read operation must be set up before data can be read from the serial output registers of the z86129/130/131. Set data automatically or manually for read operations. By setting a valid xds filter register selection, xds data reads are automatically set on resume. All other data read operations must be set manually using the read select commands rds1 and rds2. These commands load the selected data byte or byte pair into the serial output register, set the ss register rd2 bit according to the number of data bytes requested, and set the ss register dav bit to indicate data availability.
The Z86129/130/131 I2C bus supports 1, 2 and 3 byte read sequences. All read sequences output the ss register as the first output byte. If the serial status dav bit is set, a two- or three-byte read sequence can be initiated from a new strt condition. If the dav bit is not set, the i2c master should not attempt to read any data bytes, otherwise the required data may be lost from the z86129/130/131 output registers.
The number of data bytes available is indicated by the state of the RD2 bit of the serial status. In a typical read operation, the status byte is read and the dav and rd2 bits are checked. If one or two data bytes are available, they are read sequentially, separated by acknowledgments.

Serial Communication Interface (continued)
SPI Bus Operation When the short message pin is high, the Z86129/130/131 will be in SPI serial control mode. The clock line should be tied to the SCK pin. The data input signal and data output signal from the master device should be connected to the SDA and SDO pins, respectively. The sen pin is used to select the z86129/130/131 when there are multiple peripherals on the bus.
As mentioned above, when both the sms and sen pins are low, the part is in reset. When the spi bus is used in a dedicated way between the host and the z86129/130/131, both the sen and sms pins will be tied high. The reset function requires binding both pins to the nreset signal. To ensure synchronization, the host should send a serial synchronization signal after reset is released.
When spi mode is used for multi-peripheral environment, sen pin is used as z86129/130/131 enable signal. Then you can use sms for the nreset signal as long as the reset is only applied when sen is low. In this case, the host does not need to send a serial sync string after reset if there is at least 100 ns between the end of reset and the start of port enable.
The command string can be interrupted at any time and the port can be resynchronized by sending a serial sync signal or by the rising edge of sen.
The spi bus is a three-wire bus when used in a dedicated manner between the z86129/130/131 and the master. If other peripherals are connected to the bus, this device must be placed on the bus using the sen pin at the appropriate time. When sen is low, the sdo pin will be tri-stated and transitions on the sck and sda pins will be ignored.
If you do not need to output data from the Z86129/130/131, you can only use the SCK and SDA pins to complete the control. Since this type of operation precludes the ability to check the rdy bit, it is important that commands are separated by at least two frames (133 microseconds) to ensure that one command is executed before another command is initiated.
The bus is controlled by the master, which generates the serial clock (SCK) and initiates all operations. Inputting clock data on sda will simultaneously output data on sdo. The host should always check for appropriate handshake signals before executing any command other than nop.
The write part needs to set the RDY bit, while the read part needs to check the SS register to see if the DAV bit is set. Both of these bits are contained in the Serial Status (SS) register. Writing to the z86129/130/131 will first concurrently output the contents of the ss register msb unless additional data is output due to one of the read commands. If the ss needs to be read without executing the command, the nop command can be written at any time, even if the serial status rdy bit is not set.
The RDY status bit is driven on the SDO pin between command transfers. The controlling MCU can test the state of this pin without timing to determine if subsequent serial transfers are possible. The DAV bit can only be checked by outputting the contents of the SS register.
All write commands to the spi bus are one or two byte commands. The number of bytes of data received by the z86129/130/131 is inherent to the command. If the master writes more bytes than expected, the command may be overwritten or corrupted by extraneous bytes.
A status read should always be performed to verify that the device is ready before writing to the z86129/130/131. Serial status is output by the device, while any command bytes are input. The master can write a new command if the rdy bit of the serial status register is set.
Command and data bytes are written to msb first. The first byte of the two-byte command is sent first. These bits are clocked into the z86129/130/131 by putting data on the sda input and turning sck high.
Reading data using the SPI bus With the exception of SS read, each read operation must be set up before actually reading data from the device's serial output registers. Set data automatically or manually for read operations. By setting a valid xds filter register selection, xds data is set to be read automatically on restore. The read selection commands rds1 and rds2 must be used. These commands load the selected data byte or byte pair into the serial output register, set the SS register RD2 bit based on the requested number of data bytes, and set the serial status dav bit to indicate data availability.
The Z86129/130/131 SPI bus supports two and three byte read sequences. In spi mode, the ss must be read before starting the read sequence so that the dav and rd2 bits can be checked. The number of data bytes available is indicated by the state of the RD2 bit. Then use the special commands read1 or read2 to read one or two available bytes of data. The serial state is clocked during a write to a READ1 or READ2 command. The data bytes are then clocked sequentially, msb first, and the nop command is written to the device. Data bits are clocked on the rising edge of SCK. All available data bytes must be read to clear the DAV bit and allow subsequent reads.