feature? ? Standard high-performance functions in ROM
- Dolby Digital AC-3, 5.1 channel and 2 channel decoding up to 640 kbits per second
- Dolby Pro Logic codec
- mpeg1 and mpeg2 dual channel mpeg2 decoding pes stream parsing, pts decoding and scr processing Downloadable SiliconSoftware functions
- Orel a3d, Dolby Virtual Surround, Harman vmax
-qsound qsurround, spatializer N-2-2 home THX
-srs trusurround, music mode
- Bass management and multi-channel mixing flexible input and output
- Serial and/or parallel data stream I/O
- Serial SPI, Serial Z2C or 8-bit parallel host interface
- 3 serial input data ports and 4 serial data output ports
- Formatted S/PDIF receiver with sample rates up to 96 kHz
- Sample rate: 32 kHz, 44.1 kHz, 48 kHz or 96 kHz
- Formatted s/pdif ac-3 and mpeg transmitter output system low cost
- No host operation, no glue chips
- Separate internal PLL for DSP core and audio input/output
-5.1 Dolby AC-3/MPEG2 without external RAM
- Wait state generation for low cost external memory
- 100 -pin plastic four-piece package (PQFP)
-3.3 V power supply, 5 V compatible I/O, low power software and hardware PC development environment
- assembler/linker/emulator
- On-chip ice holder with direct PC connection
- ZR38600DB demo board with 6 analog outputs, mic and line inputs, and optional PC connection instructions
ZORAN ZR38601 is a high-performance programmable digital device that can decode real-time single-chip audio signal processor Dolby Digital AC-3 5.1 channel and MPEG2 digital surround algorithm. This is the fourth generation of decoders built by Zoran, based on the proven ZR38000, ZR38500 and ZR38600 builds. Hardware block floating point optimized for Dolby AC-3 and complex digital audio signal processing applications.
Due to its programmable high performance and high level of integration, the ZR38 601 meets a wide range of flexibility.
Lowest possible system requirement scope cost. At the low end, it provides standard fixed decoding with just a DAC and an optical interface for s/pdif.
Inputs other than oscillator crystals. At the high end it can provide eight-channel outputs, analog inputs, long-latency memory, custom operating functions, and upgradeability using the downloaded SiliconSoftware 8482 ; product enhancements. Yet all this flexibility comes without design complexity. Highly configurable standard functions with simple command structure minimize software development, while a full suite of development tools are available for highly customized product developers.
ZR38601 is mainly suitable for audio applications such as home theater audio/video receivers, digital audio broadcasting (DAB), 3D audio, six-channel speaker systems and karaoke processors; mainly video applications such as SDTV and HDTV stereo TV receivers , digital cable and satellite set-top boxes; and multimedia applications, including audio and video like multimedia PCs and digital video disk (DVD) players.

General Instructions
Zoran ZR38601 is the latest digital audio processing
The ZR38000 high-performance programmable controller is a member of the digital signal processor product line. It is specially configured with peripherals, I/O functions and digital audio software.
Today, high-quality digital audio begins with primary decoding functions and adding appropriate streaming protocols and interfaces with I/O configurations to match the application. The ZR38601 has these main decoding and protocol software functions, but also leaves processing cycles for additional product features. The ZR38601 also has system I/O and hardware configuration flexibility.
The ZR38601 has the same pinout and instruction set as the earlier ZR38600, but with a higher 50-MIPS processing rate and larger internal program and data ram and rom.
New 96khz sample rate s/pdif decoding and memory for increased processing cycles and extra features. New hardware features are a programmable timer, a Z2C serial host interface and more support for 24-bit I/O data formats.
Function
ac-3 and mpeg and their variants are the main decoding functions currently in use. The ZR38601 has these and their associated functions required for setup, operation and system testing to make them available in end user products. In addition, an increasing number of electronic software functions can add special enhancements and differentiating functions to products.

The decoded audio output can be up to 8 bit serial channels from the S/PDIF DAC format or six encoded channels from the transmitter.
Memory usually does not require external storage, but can be programs and/or digital audio data. Additional program stores provide different or additional functionality when the mainframe is not in use and allow options for future upgradeability. May require external data storage with long acoustic delays, input buffering, or large data tables. The byte width of the program memory interface is to provide the lowest cost and part count. Functional Description The operation and configuration of the ZR38601 software and its hardware configuration are described more fully below.
software operation
A major advantage of the ZR38601 is its ease of use. System developers have a wide range of system requirements. Standard functions are easy to use, but custom functions can be added without having to go back to custom software development considerations with complex real-time operating systems or detailed I/O protocols. The following are all software functions that provide command and response sequences for host or api (application programming interface) for calling a program from within. Each provides custom functions in not only one, but a range of ways depending on the complexity.
Setup, main and silicon software functions as in the middle. Using system utilities to maintain communication with the host, the host can issue a series of commands in response to control the operation of the ZR38601. Utilities make api calls to functions. All software development is based on getting information back from the ZR38601's actions even in the type of changes in functional operation.
Alternatively, the control information in the command can be entered into a program running internally on the ZR38601 processor in a sequence of API calls issued from a custom item. Not anymore. The host is required.
For host command/response streams or api calls, custom functions in native ZR38001 code can be used without losing the benefits of ease of use in a common structure.
Standard main, operating and setting functions. Note that there are read and write commands to the ZR38601 and responses from the ZR38601 to the host. The response is caused by the command During normal operation in progress is followed by a specific command with a read command.

Software - Function Main decoding and testing function
The main working mode functions of the AC-3 Dolby Digital ac-3 decoder are summarized in Table 2. Choose linear pcm for input and output ports and their formats, including audio/video sync (AVS), constant, or request-driven PES operations to encapsulate input to DVD.
AC-3 input decoding rates up to 640 kbits per second. Fully selectable speaker configurations, dynamic range compression, downmixing, delay, filtering and error concealment strategies. Karaoke mixing is also supported.
Includes downloaded karaoke coefficients.
The pcm+pro logic utilizes a two-channel PCM input, and the choice of function is four-channel PRO logic decoding or two-channel stereo mixing. Speaker configuration, downmix, delay and surround filtering can be selected.
The MPEG standard mpeg1 decoder function accepts an mpeg1 or mpeg2 input stream and produces a stereo output in the form of a Pro logic or a two-channel DAC. Selectable speaker configuration, dynamic range compression, downmixing, delay and surround filtering.
Pink Noise This is a six-channel pink (equal energy per constant proportional bandwidth) pseudorandom noise generator test function. It is used by users to test speaker balance in the listening space. The six-person single speaker can be at a single adjustable level, with or without a band-limiting filter. SiliconSoftware features 3D audio with six third-party vendors using the ZR38601 number. This function provides a three-dimensional effect on the sound field of only two speakers. These certified features are Orel a3d, Dolby Virtual Surround, Harman vmax, qsoundQsurround, Spatializer N-2-2 and SRS Trusurround. They use 2 or 6 channel inputs and AC-3, MPEG speakers depending on the listening area and can want to change the distribution of bass frequencies among the speakers. The choice of speaker configuration is to provide the simplest Hertz with a low pass cutoff frequency of 80, 100 or 120. Full functionality allows low-pass as well as high-pass filter coefficients for individual speaker volume.
Bass management works with two or six channel inputs as well as AC-3, MPEG and Pro logic decoders. It does not work although some 3D audio features include some bass management functions.
DVD-Linear Dynamics Control Module In addition to audio/video synchronization (AVS) and driver pes packet input feature functions that request standard decoding, this DVD function has 3D audio capabilities and bass management. It works with dual, six or eight channel pcm inputs and AC-3, MPEG and Pro logic decoders.

Hall Effect/Music mode uses this feature to add short and long term delays and reverbs to the multi-channel pcm input. The delay factor is downloaded to simulate various acoustic environments (concert halls, churches, stadiums, etc.) Home THX5.1 This function is used to connect to the cascade, providing the sound of the Lucas Cinema home listening environment. The input chip runs all standard decoding functions and passes its pcm output to a second chip for THX5.1 processing, including full bass management, decorrelation, tone matching and re-equalization, and individually programmable channel delays.
Karaoke Processing In addition to the mixing features of the Karaoke input standard, the decoding functions are true Karaoke Voice Processing Cancellation, Pitch Shifting, Voice Echo and Reverb, and Bass Management. External data storage may be required for this feature.
custom functions, etc.
User functions allow developers to easily add custom functions using their own native ZR38001 code, while retaining control of the command and reaction structure
No. ZR38601.
Operation and Setup Functions Summary Operation functions are the real-time start and stop commands required for system control once the Master Decode function has been selected. Also included are commands to obtain input channel and decode status to monitor ongoing operations. PTC and STC clocks can also be monitored to ensure audio and video synchronization.
Setup functions configure hardware and software manufactured prior to the start of an operation or as a primary operation change. Hardware configuration and initialization includes phase-locked loops (plls), system clocks, and input/output (I/O). Software can be installed in place by the host processor from its I/O or memory system. May be in the form of a custom command and its arguments or directly executable native command code for the core dsp processor.

The rest of the system function standard zr38601 is used to have a system function monitor in each program rom which is a simple real time operating system small kernel with all ZR38601 functions functioning properly. The Utilities System utility maintains the various I/O interfaces shared among the operational functions. These include serial audio data ports, serial SPI or Z2C host interfaces, and parallel host interfaces for commands and responses. These utilities also include initialization and reset boot routines that determine the boot ROM and perform its initialization process.
ICE debugging uses ZR38000 series circuit simulation debugging simulator, monitor execution with single step and program breakpoints.
Software-System Configuration Due to the ZR38 601's capabilities, it can be configured from low-cost, fixed-function devices to very flexible, full-performance audio. Processor, there are many software options related to the configuration of the system hardware configuration. The important consideration is whether or not the host uses standard commands. The most common configurations and their relative advantages.
Software for different hardware configurations. From the on-chip program rom, it can be a standard version, or it can have a custom function as shown. Custom and electronic software functions can be downloaded to the on-chip program RAM arrows for the three sources indicated by dashed lines. Without a host, byte-wide program ROM must be loaded externally. For the host, it may come from the host's own non-volatile memory (usually rom or flash-eprom) or through its I/O peripherals such as online links or removable memory media like floppy disks.
Hardware - The system configures all hardware, composite system ZR38601. The host, data input and output, and external memory options are summarized in Table 5. Those that get standard functions with standard commands are recorded. Individual silicon software functions support additional configurations. For example, karaoke processing supports the required bit-serial ADC data input and external data ram for pitch correction and sound reverb.

oersted
The operation of the ZR38601 does not require a host microprocessor. A custom program that takes the standard internal rom in either the internal rom or the external rom is enough. Control then operates through GPIO (General Purpose Input/Output) ports. However, if you use a host, the greatest flexibility is available. The lowest cost of this external hardware is the serial host interface. This four-wire SPI (Small Peripheral Interface) or two-wire Z2C signal (see Table 6) connects directly to most low-cost microcontrollers. The host serial interface has no speed penalty and it enables the parallel interface to be used with external memory.
The parallel interface of ZR38601 can be used for byte-range connection with the microprocessor host, and byte-range I/O has standard command support. All 16 bits can be used for I/O connection to the developer's software if the parallel interface is called. Note that the parallel interface cannot be used simultaneously for external data or program memory while using the host and I/O.
Data Input/Output The main data input is a single wire digital audio interface receiver. This is fully compliant with S/PDIF, IEC-958, AES/EBU and EIAJ CP-340 consumer standards. All standard sample rates support raw or packed bit streams as well as data-driven master operations using the DREQ signal on the GPIO0 port. Serial Port A or a byte-wide parallel interface can alternately be used as a master or slave of the channel bit stream.
The parallel interface also provides data-driven master operations, but not with the system.
Up to 6-bit serial ADC data channels can be input as master data or slave silicon software functions in multiple industry formats when required.
Up to eight bit-serial DAC data channels can be output to master and slave in the same industry format, including i2s and eiaj, with word, frame, and frameless synchronization.
Ports B, C, and D are used by standard 6-channel functions. Port G additionally has 8-channel silicon software functions. Otherwise port G is used as the S/PDIF master transmitter.
The 20 address and 16 data lines of the external memory parallel port allow the choice of external memory for program and data storage requiring silicon software functionality or future flexibility.
Variable wait states are supported for slower, lower cost memories. Not for use with parallel hosts or I/O interfaces.
Hardware - digital audio processor ZR38601 consists of interface, memory and
The system clocks around the ZR38001 DSP core are summarized as shown in Table 6. The power connections are shown in Table 6.
This diagram illustrates how the serial output port g with the s/pdif transmitter and its parallel multifunction ports for external hosts, I/O and memory utilizes unused 16-bit memory data lines when the parallel byte wide interface is used for external hosts and I/O.
Using standard functionality, three of the six GPIO signals are dedicated to mute input, I/O data request output, DREQ, and one I/O error output, ERROR.

Internal memory is large: 20Kwords of 32-bit program/data ROM increases downloadable memory. The data-only memory is a 10 Kword RAM at 20-bit data word precision.
Two programmable phase-locked loops (PLLs), one for the DSP core (FDSP) and one audio serial port (FAUDIO) allow independent selection of these two key internal clock rates.
When the ZR38601 system oscillator is not determined by its own external crystal, but by the predetermined system clock frequency. There are two pllsDSP cores working simultaneously at a maximum of 50 MIPS.
Serial I/O processing rates (FDSP = 100 MHz) operate at standard sample rates of 32, 44.1, 48, or 96 kHz, regardless of whether the predetermined system clock frequency is a common submultiple.
The supply voltage is 3.3V to reduce power consumption, however all I/O signals are 5.0V tolerant in a 5.0V system.

Standard function description
The ZR38601 standard functions are determined by whether these send commands, parameters and responses received by the microprocessor through the serial host interface, or the parallel host interface when using a parallel host. This AC-3 has similar features like Application Programming Interface (API), Pro Logic, Pink Noise etc. These APIs are executed by the developer program on the core processor.
The transfer between the host and the ZR38601 with SPI is full duplex, the host is the host. One word is received from the ZR38601 for each command sent. With parallel host interface or serial Z2C interface for half duplex and master together. The host must then send a response after each command. Commands are sent only from the host and are displayed in general form.
There are two types of commands: to the decoder and those read back from the decoder. Writing code in addition to basic operations. There are three types of write commands: functions that select main decode and test, functions that control operations (such as stop or play) and those that set operations

Command Operations This section describes using the command structure and its configuration choices.
After the boot is reset by the system reset signal, the ZR38601 will check if the external program rom is to be loaded. Couldn't find this would start executing from the internal rom and wait for it to come from the master. Normal host operation will confirm the ROM version number and then configure the ZR38601 to match the system and desired operation. The command configuration sequence plltab, pllcfg, cfg is required and must be selected in any decoding function.
The pll is configured with two phase-locked loops (PLLs) that allow independent selection of the core processor clock rate (fdsp) and the clock rate (faudio) of the various system clock frequencies (fxti) of the serial digital audio and sources. Figure 6 shows the system oscillator, two plls, serial i/o splitter chain and interconnect selection. They are controlled by the plltab, pllcfg and cfg commands.
The dspm and dspd fields in the plltab command determine the core processor clock rate to allow a lower clock frequency to be selected between processing performance and lower power consumption. Table 10 shows some representative values for common system clock frequencies.
The audm and audd fields in the plltab command determine the serial digital audio master clock rate for the I/O splitter.
Some representative and recommended values for common sample rates and master clock multiples.

input/output configuration
The cfg configuration command (see page 17) and the setio command (see page 19) determine the digital input and output configuration.
With data stream input, output DACs and unit general registers via input/output ports. There are seven digital audio input and output ports (ports A, E, and F are inputs, and ports B, C, D, and G are outputs). There are six unit general purpose user-defined I/O ports: GPIO[5:0].
Serial Port Bit Serial ports serve various peripheral conventions. Their operation is entirely determined by the cfg configuration command. Input port group A (serial input A, E, F) and output port group B (serial output B, C, D, and G) have separate clock systems, which can be used individually by selecting the ZR38601 as a master or slave (port F Can be activated by the clock system of port group B). The system clock (FXTI), the audio PLL locked to the system clock or the s/pdif receiver can generate the main audio clock. This can be used to generate the bit rate clock for both internal inputs and outputs when they are masters.
If input port group A is the master port, the frequency of SCKA is fa=fpsa/(2·spas), where fpsa is the audio clock faudio. In the case where spas is equal to 1, fa is equal to fpsa. Separator spas is a field in the cfg command. Similarly, when output port group B is the master port, the rate of SCKB is fb=fpsb/(2·spbs), where fpsb is the internal audio clock faudio or the external clock fsckin received through the sckin pin. When spbs is equal to 1, fb is equal to fpsb.
The output is unique and can also derive a clock input (SCKIN) with a programmable division ratio SPB from an externally provided master device when operating as a master clock.
This selection is made using the cb field in the cfg command.

digital audio receiver
The digital audio receiver function of the ZR38601 is fully compliant with IEC-958, S/PDIF, AES/EBU and EIAJ CP-340 user mode interface standards. It locks on the incoming bit stream and extracts clock and data information. The data is provided to the processor for decoding and the clock is multiplied by the 256x or 384x sample rate DACS as required. This master clock signal is available as an output on the sckin pin.
For proper operation of the S/PDIF receiver, the following initialization steps are required:
• The audd variable in the plltab command should be set to approximately 128 x FXTI, where FXTI is the clock input frequency in MHz (ie, if FXTI = 12.288 MHz) audd equals the integer part of 12.288 x 128 = 1572. For sample rates of 256x or 384x, audm should be set to 4 or 6 audio clock outputs.
• The F1 field in the PLLCFG command should be set to 1.
• The sen field in the cfg command should be set to 1.
Other representative values for audm/audd, f3 and spbs, various sample rates and master clock rates when using s/pdif receivers. They are for the average person to choose a system clock frequency (FXTI) of 24.576MHz.

digital audio transmitter
The digital audio transmitter of ZR38601 is fully compatible with iec-958, s/pdif, aes/ebu and eaij cp-340 user mode standards. This feature allows the transfer of digital audio bitstreams to an external decoder for processing in all modes of operation, i.e. AC-3, MPEG or PCM. The transmitter is enabled by setting the spo bit in the cfg command. The channel state information required by this iec-958 shall be provided to the zr38601 through the spdifcs command, the S/PDIF channel state SPDIFCS part. It is important for the external decoder to set the channel status bits for proper operation. The fourth serial port SDG is disabled when the S/PDIF output is enabled. Note that when the output frame is output using S/PDIF, the size must be 32 bits (frb=1).
General Purpose Ports There are six units General purpose ports GPIO[5:0] are normally configured as inputs on reset. GPIO5 is usually used as mute input and GPIO0 as DREQ output. GPIO1 is usually the error output signal. via the setio command. Input pins, defined to sample from gpio[5:0] inputs and read from gpio are registered by the host with the setio command. At the same time it can set the state of pins configured as output pins.
Decoder Operation A typical decoder function selection command sequence is: AC3, unmute...mute...start, unmute...select AC-3 first, then switch to a later preamble. If the drq bit is set in the command cfg, the command sequence must include play: AC3, play, unmute...mute, stop...MPEG, play, unmute...

Processor General Description
The core processor of ZR38601 has multifunctional internal structure, general instruction set and high speed. Many other types of algorithms can be implemented in a wide variety of digital signal processor applications. These algorithms can add product-distinguishing features to basic audio decoding functions.
Along with the ZR38601's state-of-the-art performance, these additional features require very little processing time or program memory. 32-bit wide allows the device to perform large concurrent operations. For example, the following operations can be performed in one instruction cycle:
• Fetch two source operands from registers, perform arithmetic operations and store the results in registers.
• Update two data address pointers • Perform two parallel data move operations • Generate next program address • Fetch next program instruction.
Single-bit and immediate data instructions and the ZR38601's four-level zero-overhead loop and repeat instructions result in very compact code. Most instructions are in a loop.
The ZR38601 achieves 50 million instructions per second (50-MIPS) performance using an internal clock rate of up to 100 MHz. This allows cycles per instruction. An internal programmable Phase Locked Loop (PLL) multiplier/divider circuit allows for any external crystal or input clock to be used (in the 12-50 MHz range).
The ZR38601's optimized 20-bit (120 dB) data precision makes it ideal for disc-quality audio applications, including audio equalization, special effects, and audio mixing where the 16-bit data precision of traditional fixed-point DSPs is insufficient. In addition, extending dynamic range by providing high-performance support for block floating-point operations (including a period index detection and two ZR38601-based systems is inherently more cost-effective than a 24-bit precision fixed-point DSP implementation that extends dynamic range by extending only the extended data) Precision. High performance block floating point is due to the ZR38601's bidirectional barrel shifter, a feature not available on most traditional 16-bit and 24-bit fixed-point DSPs.
To simplify programming and increase speed, the ZR38601 architecture provides a general-purpose data register file that can provide up to four source registers and two destination registers as directed. A total of eight 20-bit data registers are provided, with two registers extended to 48 bits for use as accumulator registers with 8-bit overflow protection.
The ZR38601 also provides a dual address generator and register file capable of generating two independent addresses per instruction cycle. The address generator supports modulo and bit-reversed addressing, in addition to a complete set of pre- and post-modification addressing modes.
The ZR38601 has many built-in memory resources. A large 2K x programmable 20k x 32-bit ROM in addition to many encoding functions in the mask. The already large internal 10K x 20-bit data RAM can be extended via a 16-bit external data bus and a 20-bit off-chip memory address bus, allowing it to address up to 1M data words in a unified address space. Programmable wait states accommodate low-cost slow external memory and byte-range configurations are available for lower chip counts if desired.
Processor Functional Description Architecture Overview
Detailed functional unit processor of ZR38601. The data path consists of arithmetic units, memory sections for data and their associated address generators. A control path is an instruction unit, the memory portion of a program, and its associated program sequence unit. The rest are input/output ports and system interfaces.
Data flow between datapath units exceeds a single 20-bit data bus with a corresponding 20-bit data address bus. Control flow is on a single 32-bit program data bus on a 20-bit program address bus. These dual data and address buses are multiplexed to a smaller single external bus external data memory. This simple space-saving bus structure maintains high performance because each internal bus has two transfers per instruction cycle, and each unit is independent with its own local memory.
The high performance of the ZR38601 slaves the power of the data functional unit and its accompanying instructions, and matches the control power to the functional unit and its description. Both are described in turn.
Data and control paths can be guaranteed in wide word instruction sets due to fast interconnect bus structure and control both. This view operates by function and instruction confirms that the arithmetic unit arithmetic unit uses a full-featured ALU (bidirectional barrel shifter) to perform all datapath operations in the processor and a 20 x 20-bit multiplier, all out of multiport Job registration documents. These seven ports allow two incoming or outgoing cycles to register files from memory using three-operand multipliers and arithmetic operations in parallel, including store-result instruction cycles. In addition to basic two's complement arithmetic and logic operations, the 48-bit ALU can find minimum and maximum values, normalize, determine the exponent of block floating point, support multiple precision and perform division primitives. A further refinement is a butterfly primitive that computes the product and difference using an auxiliary adder. This one takes four operands, performs multiplication, addition, and subtraction, and stores the two results, helping to implement a very fast 4-cycle radix-2 fast Fourier transform butterfly. The ALU result sets the appropriate status register bit system interface, sticky bits with multiple precisions, and array calculations. A large class of immediate data logic and arithmetic instructions free up register space and reduce instruction counts in bit manipulations common in communication coding applications. The multiplier provides both signed and unsigned operation by the ms bit in the mode register. This fractional-aligned shift preserves the maximum 42-bit product of the shift. This 48-bit barrel shifter performs both logical and arithmetic shifts; the SD bit in the mode register allows positive shift operators to be interpreted as shifting left or right. The third data shifter provides arithmetic shifting, rounding, and limiting when transferring data from the register file onto the data bus. The range of this shift from 1-bit right to 2-bit left is determined by the ds bit in the mode register.
Two of the eight registers of the register file (d0 & d1) are 48 bits, the remaining 6 bits are 20 bits, and are aligned as shown in In general, all arithmetic unit operations are implicit data overflow, limited, Rounding or registers D2-D7 are truncated accordingly. But when d0 or d1 is the source or destination, the operation is as follows to retain the full 48-bit precision result in these registers. Likewise, transfers in and out of d0 and d1 using the data bus are based on the expansion or reduction of 48-bit operands. These two registers are often used as high precision accumulators and are at the heart of most signal processing algorithms.
If the implicit operand is not the desired operand. The address generation unit restores to the data register file from and reads the data manipulated by the arithmetic unit. The register file location is indicated by direct addressing of the register field in the operation field. For internal and external memory and registers, direct addressing can also be used, but indirect addressing of the address generation unit is generally faster and more program memory efficient. The address generator can perform two bus transfers per cycle, modifying two addresses in the same instruction cycle.
The generated indirect address can be linearly incremented or by any modulo m. This is the unit calculated by address alu (aalu) and address register file done in address generation The next address is the modulo register mx using the comparison of address register ax with index register ix in a modified operation. The five addressing modes in assembler symbols are: NOTE: The stack has no indexed or circular addressing. pointer sp. For m=hex fffff, the corresponding a register is incremented in a bit-reversed manner to perform a base 2 fft. For an n-point fft, the incrementing index register must be loaded with N/2.
The address register file can be accessed on the data bus and can be used for general purpose registers. Also, they can load instant data from the program data bus.

memory, which transfers on the data bus and only from the data address bus. It is always located in the lowest memory address space from hex 00000 to 027FF. The other RAM and ROM are 32 bits wide and can be used for both data and program memory. They can be accessed by program and data address buses and are sources, and ram destinations, for data and program data transfer buses. When the program RAM is written to the 12-bit simultaneously extended load (dbx) register from the data bus. When program ram is read as data, the dbx registers are loaded with the most significant 12-bit data. This dbx register can also be used as a general-purpose register to load or read data with the least significant 12 bits. The rom is always located in memory at locations hex e0000 to e4fff in two address spaces on the bus. The standard ZR38601 product has a digital audio decoder function and is used to accept external ROM from the host or to load operating programs from one byte wide into RAM. Note that the external ROM data is on D[11-4]. Program/Data RAM is always located at hex d0000 to d07ff of memory space on both address buses. It provides fast internal memory without the use of internally programmed mask ROM boot ROMs or host microcontrollers when the ZR38601 is used with external byte widths.
All internal memories have one port, but with the bus, each instruction can execute two complete cycles of operations. if the bus is available. Each internal address bus has its own address space, but since internal memory and external memory do not overlap memory sharing a common address bus, all memory can be considered in one address space The internal data bus is multiplexed to A smaller external memory bus. Therefore only one external data transfer can take place at a time. Also, only one transfer to the slower external memory can be done per instruction cycle. This memory cycle time can be extended by inserting wait states to allow the use of slower memory at a lower cost. The number of wait states is dictated by the cfg command, so that external memory operations execute one, three to seven instruction cycles. The address shown is an internal 20-bit.
The optional external boot rom is 8 bits wide, connected to d[11-4]. Different widths of memory can be used for external RAM if required. Options are 8-bit or 16-bit. Data must be left-aligned on the data bus.
Reset and Interrupt Memory Locations Reset and interrupt vectors occupy 64 (hex 40) locations in memory. Can be located in the lowest part of the 20K x 32-bit OM or 2K x 32-bit RAM on-chip. This is controlled by the mode register as follows: All processor operations of the program sequence unit are controlled by decoded instructions in the instruction register (ir). The control flow of the processor is the sequence of instructions presented to ir. This program sequence unit fetches the program address from program memory by generating the program address.
This unit in the ZR38601 is also a powerful address generator, usually producing a minimal sequence of long operations program memory transfers. Examples of this are repeat and loop instructions, which allow repeating single and multiple instructions without instruction overhead. In addition to these instructions, the main changes in control flow are subroutines that are responded to by reset operations, interrupts, branches, and program sequence units. Reset and interrupt operations The processor's operation asserts the reset PIN from the system. When a reset is asserted, the mode register is set to 00038 hex and the status register is set to 00000 hex. The serial port data register and shift register are both cleared for outgoing serial ports and the serial port shift register pointer is reset. The modulo register and loop end register are cleared. The program counter is set to e0000 in hex and resets and breaks before unconditionally jumping to reset start. The first three classes provide the functionality of the complete arithmetic unit and its fields of operation (opcodes and operands), but perform parallel operations at the same time. This parallel operation field (parallel opcode and parallel operand) specifies single and double, direct and indirect transfer source and destination, and address generation modification operations. Bit instructions are also parallel operations. The last five classes of instructions are used for large field direct data transfer and program control.
For classes IV and V, possible source or destination registers are general purpose registers. For parallel operation, the source and destination registers may include auxiliary registers.
and the general register.

I/O ports connect to external memory and peripheral devices through I/O ports. There is a 16-bit parallel data port, 8 serial data ports and 6 single general purpose I/O ports (GPIO). These last can be used as output or input by the user. parallel port
The ZR38601 parallel port operates in two different modes selected by pin P/M at reset. It can act as a data parallel port for loading data, instructions and programming the chip and reading status and other information from the chip, or it can work as an external memory interface. This external memory interface consists of a 20-bit address bus A[19:0], a 16-bit bidirectional data bus D[19:4] and control signals CS, RD and wr. The data parallel port interface includes 8-bit bidirectional data bus pp[7:0] and control signals cs, rd, wr, err, c/d, rdy. RDY, C/D and ER signals are d[14:12], and pp[7:0] is also d[11:4]. When controlling the external memory interface (P/M=0), CS is asserted low when accessing external memory. rd is asserted during an external read cycle and can be used as an output enable of the memory. wr is in external write cycle and can be used for memory.
The ZR38601 can generate wait states for external memory using the wait field of the cfg command slowly. Transitions of memory interface signals in access cycles with wait states are identical to those in zero wait cycles, but all are specified by a digital stretch that refers to instruction clock cycles (1, 3, or 7). Accessed in an instruction cycle with no external data, the rd and wr signals are not active. However, the address bus continues to be driven by internal instructions to fetch addresses.
When the parallel I/O interface is selected (P/M=1), the internal fifo is used to enable the host to write data in long bursts. This rdy output signal indicates when the fifo is ready to receive more data (rdy=1) or when the fifo is almost full and not ready to receive data (rdy=0). The error signal is if in data. The C/D input signal distinguishes between input data and instructions or states using the hregin/hregout registers. When C/D=1, the transfer is the master command or response state, so write the hregin register or the slave hregout register. When c/d=0, then all the internal fifo is written from the host. cs, rd and wr are always entered when /M=1. When reset is asserted, the address and data buses and control signals cs, rd, and wr are all set to a high impedance state.
Serial DAC and ADC ports Serial ports are used flexibly on the ZR38 601 for a wide range of services.
Various applications and peripherals. The three ADC inputs and four DAC outputs can be grouped differently to share two common control signals, one for each master or slave. Other options are word or frame synchronization, frame size and 16, 18, 20 or 24 bit word transfers. A master clock output that internally generates a group programmable rate clock. The i2s format, the frameless time division multiplexing (TDM) format and the LSB justified frame all support the EIAJ format.
Ports A, E, and F are always ADC data inputs, while B, C, and D are always DAC data outputs. Port G can be the DAC data output or the s/pdif transmitter output. They can be configured as two groups with a shared clock: all inputs and all outputs, or as two groups using one of the inputs in the "output" group. This selection is formed by the AB bits in the mode register. Group B is the only one whose clock output can also be derived from an externally supplied master clock input (sckin) when operating as a source for a DAC in this case.
Transfers are on the positive or negative going edge of the bit rate clock (scka and sckb), and the most significant bits are shifted in or out of the double-buffered shift register first. Word boundaries are represented by a unit duration frame signal (fsa and fsb) for each word or alternate word signals (wsa and wsb) to represent the left or right channel, even or odd. Signal type 16, 18, 20 or 24 bits word length and frame size are individually selected for each group from 16 to 256 bits per frame. The word select bits in the state register reflect each set when the left or right channel transmits. ws/fs signals may be spaced by one or more bits in non-i2s format. Completed frame transfers for each group are interrupted when individually enabled by the vector indicating to the processor. TDM exceptions where each word in a frame is interrupted.
Each group can be a source or a slave selected in the Auxiliary Serial Port Mode Register. When a signal source, the clock will be independently programmable circuit emulation interface
The in-circuit emulation (ICE) capability of the ZR38601 provides hardware and software calls to pins (tdi, tdo, tck, tms) using the standard jtag interface through four tests. This interface is serviced by routines and highest priority interrupts in the on-chip program/data rom. This provides hardware debugging of register and memory read and set commands. Three breakpoint address detection registers and in addition, two count registers with interrupts provide support for real-time program debugging in ICE. Reset and Initialize The processor can only reset external input pins by asserting the reset signal. At initial power-up, the operating condition must be asserted for at least 160 clock cycles at the proper supply voltage. Run 16 cycles after rising edge. After power-up, any reset must be asserted for at least 16 clock cycles, but less than 128 clock cycles to reset the PLL if not required. If the user wishes to reset the plls, the reset signal must be active for at least 160 clock cycles. Operation begins 16 cycles after the rising edge of the selected reset service at the regular position in memory. However, the processor will not, accept the serial host command and return until the 200 response command cycles have elapsed. For the decoder to operate correctly, the following command sequence should be provided: PLLTAB, PLLCFG, CFG, AC-3 (if AC-3 mode is required) unmute.
The state of the pin after reset is tri-stated or the external interrupt input signal INT is edge sensitive and must remain asserted for two clock cycles to set the internal INT flag. This flag is cleared when the interrupt service routine starts, so any new interrupt condition must allow the int to go high and then low again to generate another interrupt.
Oscillator and Clock Inputs The xti and xto signals together supply the oscillator clock fxti as an input from the ttl system clock or as a crystal connection to enable the internal oscillator. The maximum frequency fxti is 40mhz and the minimum is 4mhz. The internal phase-locked loop (pll) thus generates a dsp core clock FDSP. This internal DSP clock can be in the range of 4-100 MHz. (For low FDSP frequencies, care should be taken as the spi data rate is scaled down). After reset, but before PLL locks, fdsp=fxti.
An external clock should be applied to the XTI, and an external crystal connected parallel resonant fundamental mode crystal should be used with two 20pf capacitors.