feature

Three video anti-aliasing or reconstruction filters 2:1 mux input for YPBPR and RGB input supports D1, D2, D3 and D4 video D connectors (EIAJ CP-4120) selectable 8MHz/15MHz/30MHz sixth order filter plus Bypass works with SD (480i), Progressive (480p) and HD (1080i/720p) AC-coupled input includes DC restoration/bias circuit All outputs can drive AC or DC coupled 75Ω loads and provide 0dB or 6dB gain 0.40% differential Gain, 0.25° Differential Phase Lead-Free TSSOP-20 Package

application

Progressive Scan Cable STB Home Theater Satellite STB DVD Player HDTV Personal Video Recorder (PVR) Video on Demand (VOD)

illustrate

The FMS6403 provides comprehensive filtering of box or DVD applications for TVs, set-top boxes. This section consists of three sequential filter frequencies with 6 selectable 30MHz, 15MHz or 8MHz cutoffs. Filters can also be bypassed so that the bandwidth is limited only by the output amplifier. A 2-to-1 multiplexer is provided on each filter channel. Triple filter for ypbpr and rgb signals. The DC clamp level controls the input according to the rgb_sel setting. The YBPR sync tips were clamped to 250 mV, 1.125V and 1.125V, respectively, and the RGB sync tips were both clamped to 250 mV. Sync clamp timing can be input from Y/G or from an external sync pin. The 8MHz and 15MHz filter settings support bi-level synchronization, while the 30MHz filter setting and bypass mode support tri-level synchronization. All channels nominally accept AC coupled 1vpp signals. Selectable 0dB or 6dB gain allows the output to drive a 1VPP or 2vpp signal input with an AC-DC coupled termination load using a 1vpp input. The input signal cannot exceed 1.5vpp and the output cannot exceed 2.5vpp.

Functional Description: 1. Introduction Next Generation Filter Solution Fails Semiconductor Extended Filtering Required for TVs, Set-Top Boxes, and DVD Players Includes Progressive Scan Capability Products Offers Selectable Filtering with Cut Frequency 30MHz, 15MHz, and 8.0MHz for all three channels. Alternatively, the filter can be BYPASSED for Wider Bandwidth Applications. The FMS6403 allows consumer devices to support a range of resolutions on the same hardware standard. Channel inputs are controlled by a multiplexer on the input to set synchronization. TIP clamp voltages for YPBPR or RGB applications. The three channels are set to 250MV sync tips to reduce DC-coupled input power dissipation. Output bias voltages are not suitable for PBPR outputs. Inputs these signals are keyed to 1.125V while Y is still clamped to 250mv. The genlock voltage setting forces the desired DC offset level period during the current sync. For systems without Y/G sync, an external sync input is provided. If sync exists on one input Y/G signal but not on the other Y/G input signal, the IN2 salt and the external sync control input can be used together with the input source to switch the sync source. Standard definition and high definition sync support rely on FSEL[(1):(0)] inputs. See the Sync Processing Section for further details. The standard defines a sync pulse with a progressive signal pressing the signal key to the desired voltage during the sync pulse. For the sync signal, the sync tip is forced to the clamp voltage ("typically 250MV") Duration when high definition sync is present is too short to allow this approach. In order to precisely clamp the HD signal, the sync pulse starts for a period of time, and the actual clamping occurs in the following period. The sync pulse TIP will still be a typical location for 250MV. If its amplitude is 300mv all three outputs are driven by amplifier, with selectable gain Of 0DB or +6DB. Gain is set with 0.DB \ \ xE4 salt pine. These amplifiers can drive two terminal video loads ((+7584866P); input at 1VPP when set to 6DB gain.

The input range is Limited to 1.5vpp and the output range is limited to 2.5vpp. All control inputs must be driven high or low. Do not leave Them floating. External sync mode FMS6403 can recover sync time from video in advance. Signals including sync If the Y-Input Video signals doe not include sync, the FMS6403 can be used in external sync mode. When the FMS6403 is used in external sync mode (external sync pin high), the pulse input must be applied to the sync pin. If no video signal is present, and therefore no sync signal, there must still be an input applied to the sync-in pin. When there is no video signal on the video input sync_in can be a sync pulse every 60 microseconds to simulate the slowest sync video signal. The following two sections discuss synchronization requiring more detailed processing and timing. SD and progressive scan video synchronization processing FMS6403 must control the DC offset of the AC coupling due to the average DC level of the video with the image content. If the input offset is allowed to drift, it can distort the signal beyond the common-mode input range of the amplifier. Reference DC offset adjustment as clamping or, in some cases, bias, must be done at the correct time on each video line. The best time is during the sync pulse as it is the lowest input voltage. This method works well for 480i and 480p signals because the sync cue duration is long enough to allow the DC offset to be compensated for row by row errors. The DC offset is shown in Figure 12 by the current at the input during the forced sync pulse. The sync tip will be clamped to about 250MV. Signals like pb and pr with a symmetrical voltage range (±350mV) will be clamped Please note the diagram below illustrates the DC reduction function and indicates the output voltage levels for 0dB and 6dB gain (1VPP and 2VPP video) signals on the output pins of the FMS6403 ).

In some cases, the sync voltage may be compressed to a value greater than the nominal 300MV. The FMS6403 can successfully restore SD and progressive scan synchronization, the latter being greater than 100mV (compressed to 33% of nominal). The FMS6403 correctly restores sync timing from Luma to green including sync. If no video signal includes sync, the external sync control input can be set high. The external sync signal must be input on the sync input pin. See the External Synchronization section for details. The time required for this mode of operation is shown in the figure. The synchronization times T1 and T2 are defined in SD Electrical

HD and Bypass Mode Video Sync Processing When the input signal is a high-definition signal, the tri-level sync pulse is too short for proper clamping operation. Instead of clamping during the sync pulse, the sync pulse is positioned and clamped to the blanking level. The 250mV amplitude of the sync tip is still set to approximately 300mV with the sync tip. The external sync control input selects the stripper output or sync pin used by the sync clamp circuit. Note: The sync timing is different for the HD signal and not the timing for the sd or ps signal. For HD signals, the sync signal must be activated at the clamp. During this time after the sync pulse, the signal is at the blanking level. This operation is shown in the figure. Note the following points charts illustrate the DC reduction function and indicate the voltage levels for output 0db and 6db gain (1vpp and 2vpp video signals on the FMS6403 output pins). Synchronized timing, T1 and T2.

Note: Tri-level sync can only be compressed by 5%. If the HD sync compression exceeds 5% it may not be located correctly. Synchronization Timing Normally, the FMS6403 will respond to two-stage synchronization and clamp the synchronization tip during cycle "b" in Figure (a). Filter switching to high definition mode (30MHz) or bypass mode sync processing will respond to tri-level sync and clamp during blanking in the "C" diagram (b). NOTE: The figure indicates the output pins.

Figure Sync Time; the dual horizontal tertiary sync pulses are positioned so that such wide pulses do not trigger lock in the vertical gap. Sequentially improve the turns of the system setup and the broad pulse will be clamped to the ground. Once a wide pulse is on the ground, the normal bond process overtakes and clamps to a burst level in the process. Figure (b) The FMS6403 is designed to support video standards. And associated comp timings shown in Table 1, (+Additional) Standards such as 483p59.94 will also work correctly filter

Application Information: The DC recovery circuit in the input circuit FMS6403 requires a source impedance (Rsource = Rs Rt) less than or equal to 150Ω for proper operation. Driving the FMS6403 with a high impedance source (such as a DAC loaded with 330Ω) will not yield the best results. The output driver specifies that the FMS6403 operates at an output current typically less than 60mA, over dual (75Ω) video loading. The current limit of the internal amplifier is about 100mA and should withstand brief durations. short-circuit conditions, but this capability is not guaranteed. The maximum assignable input voltage is 15VPP. Continues for all inputs. When the input is clamped to 1.125V, this does not produce a meaningful output signal. When the gain is 6db, the output should be 1.125v ± 1.5v which is impossible because the output cannot drive ground below. This condition will not damage the part; however, the output will be truncated. This does not happen for a clamped signal of 250 mV. Signals at midscale during sync (PB and PR) must be clamped to 1.125V and signals at their lowest values during sync (Y, R, G, B) must be clamped to 250 mV for proper operation. Clamping the PR signal to 250 mV will result in the bottom of the clipped signal. A 220uF capacitor coupled with a 150Ω termination, as shown in the Typical Application Circuit in Figure 5, Table A, a high-pass filter, blocks DC frequencies and avoids tilt when transmitting video. Anything below 220 microF will cause issues such as video skew. Higher value, for example because 470µf-1000µf is the most ideal output coupling capacitor. With AC coupling, the average DC level is zero. Therefore, the output voltages of all channels will be centered around zero degrees. Sync recovery The FMS6403 will typically recover with amplitudes greater than 100mV (relative to the nominal 300mV amplitude). The FMS6403 looks for the lowest signal voltage and clamps it to an approximate output of 250mV. Tri-level sync cannot compress more than 5% (15MV) for proper operation. Two-level sync recovery is achieved by finding the edge of the three-level pulse and running a timer to operate a selection of 8MHz or 15MHz filters. Selection of 30MHz filter or bypass mode enables three-stage sync recovery. Bi-level and tri-level sync recovery are not interchangeable. See the Detailed Synchronization section for more information. Power consumption must be considered when calculating the total power consumption with the MS6403 output driver configuration. Care must be taken not to exceed the maximum die junction temperature. The following example can be used to calculate the power dissipation and internal temperature rise of the FMS6403.

Board layout also affects thermal characteristics. The FMS6403 is specified to operate at an output current typically less than 60mA, more than a single (150Ω) video load. The internal amplifier is current limited to 100mA maximum and should withstand short-duration short-circuit conditions, but this capability is not reassuring. Layout Considerations General layout and power supply bypass performance and thermal characteristics at high frequency. Fairchild provides a demo board, the FMS6403DEMO, which is used as a guide characterization for layout and auxiliary device testing. The FMS6403DEMO is a 4-layer board with full power. For best results, follow these steps as a basis for a high frequency layout: Include 10µF and 0.1µF ceramic bypass capacitors Place 10µF capacitors on power pins Place 0.1µF capacitors on power pins Connect all external ground pins as closely as possible , it is best to have a large ground layout channel connections under the package to reduce mutual trace inductance Minimize all trace lengths to reduce series inductance. If routing across boards, place the device with longer traces on the input side rather than the output side. If multiple low-impedance DC-coupled outputs are used, special layout techniques can be used to aid heat dissipation. For two-layer boards, place 0.5" to 1" (1.27 cm to 2.54 cm) directly below the device and on the bottom of the board. Use multiple vias to connect ground planes. For multi-layer boards, additional planes (connected with vias) can be used for additional thermal improvement. Worse, the additional die power may be estimated as (VCC per output channel 2/4rload) due to the DC load. This is the assumed constant DC output voltage of VCC 2. For 5V VCC with dual DC video loads, each channel adds 25/(4*75)=83mW.