feature

80 msps wideband input (14 linear bits plus 3 RSSI); handles two wcdma channels (UMTS or cdma2000 1) or four gsm/edge, is136 channels; four independent digital receivers in one package; dual 16-bit parallel output port; dual 8-bit link port; 96 dB programmable digital agc loop; digital resampling with non-integer decimation rate; programmable decimation fir filter; interpolating half-band filter; programmable attenuator control, via electrical Flat indicator prevents clamping and external gain range; flexible control of multi-carrier phased array antenna; 3.3VI/O, 2.5V CMOS core; user-configurable built-in self-test (BIST) function; JTAG boundary scan.

application

Multi-carrier multi-mode digital receiver; GSM, IS136, EDGE, PHS, IS95, UMTS, CDMA2000; micro and pico cellular systems, software radio; wireless local loop; smart antenna system.

General Instructions

The AD6634 is a multimode 4-channel digital receive signal processor (RSP) capable of processing up to two WCDMA channels. Each channel consists of four cascaded signal processing elements: a frequency converter, two fixed coefficient decimation filters, and a programmable coefficient decimation filter. Each input port has an input level threshold detection circuit and agc controller to accommodate a large dynamic range or when a gain ranging converter is used. Dual 16-bit parallel output ports accommodate high data rate WBCDMA applications. On-chip interpolation half-bands can also be used to further increase the output rate. Additionally, each parallel output port has a digital agc for output data scaling. Link port outputs are provided for glueless interfacing with ADI's Tigersharc DSP cores.

The AD6634 is part of the Analog Devices Softcell® Multi-Carrier Transceiver Chipset and is designed to be compatible with the Analog Devices family of high sampling rate IF sampling ADCs (AD9238/AD6645 12-bit and 14-bit). Soft cell receivers include digital receivers capable of digitizing the entire carrier spectrum and digitally selecting the carrier of interest for tuning and channel selection. This architecture eliminates redundant radios in wireless base station applications.

High dynamic range decimation filters provide a wide range of decimation rates. The RAM-based architecture can be easily reconfigured for multimodal applications.

Decimation filters remove unwanted signals and noise from the channel of interest. When the bandwidth occupied by the channel of interest is smaller than the input signal, this suppression of out-of-band noise is called processing gain. By using a large decimation factor, this processing gain can improve the ADC's signal-to-noise ratio by more than 30dB. In addition, programmable ram coefficient filters allow anti-aliasing, matched filtering and static equalization functions to be combined in one cost-effective filter. The wcdma application uses a half-band interpolation filter at the output, increasing the output rate from 2x to 4x the chip rate. The AD6634 is also equipped with two independent automatic gain control (AGC) loops for direct connection to a RAKE receiver.

The AD6634 is compatible with standard ADC converters such as the AD664X, AD923X, AD943X, and AD922X families of data converters. The AD6634 is also compatible with the AD6600 diversity ADC, providing a cost and size reduction path.

architecture

The AD6634 has four signal processing stages: frequency converter, second-order resampling cascaded integrator comb FIR filter (RCIC2), fifth-order cascaded integrator comb FIR filter (CIC5), and RAM coefficient FIR filter (RCF ). Supports multiple modes for timing on-chip and off-chip data and provides flexibility in interfacing with a variety of digitizers. Programming and control are accomplished through serial and/or microprocessor interfaces.

Frequency conversion is done by a 32-bit, complex, numerically controlled oscillator (NCO). The actual data entering this stage is divided into in-phase (i) and quadrature (q) components. This stage converts the input signal from digital intermediate frequency (if) to digital baseband. Phase and amplitude jitter can be implemented on-chip to improve the spurious performance of the NCO. The phase offset word can be used to create a known phase relationship between multiple AD6634s or between channels.

The following frequency conversion is a resampling, fixed coefficient, high speed, second order resampling cascaded integrator comb (rcic2) filter that reduces the sampling rate based on the ratio between the decimation register and the interpolation register.

The next stage is a five-stage cascaded integrator comb (cic5) filter whose response is defined by the decimation rate. The purpose of this filter is to reduce the data rate to the final filter stage so that more taps per output can be calculated.

The final stage is a sum of products of fir filters with programmable 20-bit coefficients, with a programmable decimation rate from 1 to 256 (actually 1 to 32). The ram coefficient fir filter (rcf in the functional block diagram) can handle up to 160 taps.

The next stage is a fixed coefficient half-band interpolation filter, where data from different channels are combined and interpolated by a factor of two. Next, the agc section with a gain range of 96.3db can be used. This agc section is fully programmable in terms of its response. As shown in the functional block diagram, there are two half-band filters and an AGC each in the AD6634. These half-band filters and AGC sections can be bypassed independently of each other.

The overall filter response of the AD6634 is the combination of all decimation and interpolation stages. Each successive filter stage narrows the transition bandwidth, but requires more clk cycles to compute the output. Doing more decimation in the first filtering stage will minimize the total power consumption. Data from the chip is connected to the dsp through a high speed parallel port or a tigershar compatible link port.

Figure 1a illustrates the basic function of the AD6634: selecting and filtering a single channel from a wide input spectrum. A frequency converter tunes the desired carrier to baseband. Figure 1b shows the combined filter responses of rcic2, cic5 and rcf.

input data port

The AD6634 has dual high-speed ADC input ports, input port A and input port B. Dual input ports allow single tuner chips maximum flexibility. These can be diversity inputs or truly independent inputs, such as separate antenna segments. The ADC port can be routed to one of four tuner channels. For added flexibility, each input port can be used to support multiple inputs, such as those found on the ad6600 or other ADCs with multiple outputs. This extra flexibility allows the four internal channels to process up to four different analog sources simultaneously.

In addition, the front end of the AD6634 contains circuitry that enables high-speed signal level detection and control. This is achieved through a unique high-speed level detection circuit that provides minimal delay and maximum flexibility to control up to four analog signal paths. The entire signal path delay from input to output on the AD6634 can be expressed in high-speed clock cycles. The following formula can be used to calculate the delay.

MRCIC2mcic5 are the decimation values of the rcic2 and cic5 filters, respectively. NTAPS is the number of revolving loan taps selected.

input data format

Each input port consists of a 14-bit mantissa and a 3-bit exponent. The exponent bit can be grounded if required to interface with a standard ADC. If connected to a floating point ADC such as the AD6600, the exponent bits of this product can be connected to the input exponent bits of the AD6634. The mantissa data format is 2's complement and the exponent is unsigned binary.

input timing

Data for each high-speed input port is latched on the rising edge of CLK. This clock signal is used to sample the input port and to clock subsequent synchronization signal processing stages in the selected channel.

The clock signal operates at frequencies up to 80 MHz with a 50% duty cycle. In applications using high speed ADCs, the ADC sample clock or data valid strobe is often used to clock the AD6634.

input enable control

Input port A and input port B have one IENA and one IENB pins, respectively. There are four modes of operation when using each IEN pin. Using these modes, it is possible to simulate the operation of other rsps, such as the ad6620, which provides the dual channel mode normally associated with diversity operation. These modes are: IEN transition low, IEN transition high, IEN high and blank on IEN low.

In IEN HIGH mode, input and normal operation will occur when INPUT ENABLE is HIGH. When IEN transitions to low mode, normal operation occurs on the first rising edge of the clock after IEN transitions to low mode. Likewise, in the transition of ien to high mode, the operation occurs on the rising edge of the clock after the transition of ien to high mode. (See the Numerically Controlled Oscillators section for more details on configuring input enable modes.) When empty in IEN low mode, input data is interpreted as zero when IEN is low.

A typical application of this function is to receive data from the AD6600 diversity ADC to one input of the AD6634. A/B\U taken out of the chip will be the same as

Ian. Then, set one channel in the AD6634 to enable IEN transitions low. Another channel will be configured so that IEN to HIGH conversion is enabled. This will allow two of the AD6634 channels to be configured to emulate that AD6620 in diversity mode. Of course, the NCO frequency and other channel characteristics need to be set similarly, but this feature allows the AD6634 to handle interleaved data streams such as those found on the AD6600.

The difference between IEN transitioning to HIGH and IEN HIGH is found when the supplied system clock is higher than the converter's data rate. It is often advantageous to provide a clock faster than the data rate so that additional filter taps can be calculated. This naturally provides better filtering. To ensure that the rest of the circuit correctly identifies the faster clock in the easiest way possible, IEN should be used to transition low or high. In this mode, only the first clock edge that meets the setup and hold times will be used to lock and process incoming data. All other clock pulses are ignored by front-end processing. However, each clock cycle will still generate a new pair of filter calculations.

Gain switch

The AD6634 includes circuitry useful in applications where a large dynamic range is present or where gain ranging converters are used. This circuit allows digital thresholds to be set so that the upper and lower thresholds can be programmed.

One use of this could be to detect when the ADC is about to reach full scale under certain input conditions. The result will be to provide a flag that can be used to quickly insert the attenuator to prevent the ADC from overdriving. If you turn on the attenuation (or gain) 18db (or any value), the signal dynamic range of the system will increase by 18db. The process begins when the input signal reaches the programmed upper limit. In typical applications this can be set to 1db below full scale (user definable). When this input condition is met, the appropriate li (lia-a, lia-b, lib-a, or lib-b) signal associated with the a or b input port is activated. This can be used to switch the gain or attenuation of external circuits. The LI line remains active until the input condition falls below the programmed lower limit. To provide hysteresis, dwell time registers (see memory map of input control registers) can be used to hold the switching of control lines for a predetermined number of clocks. Once the input condition falls below the lower threshold, the programmable counter starts counting the high-speed clock. As long as the input signal remains below the programmed lower threshold for the number of high-speed clock cycles, the attenuator will be removed at the terminal count. However, if the input condition is above the lower threshold while the counter is running, it will be reset and must fall below the lower threshold again to start the process. This will prevent unnecessary switching between states, as shown in Figure 27.

When the input signal exceeds the upper threshold, the corresponding li signal becomes active. Once the signal falls below the lower limit, the counter starts counting. If the input condition is above the lower threshold, the counter will reset and start again, as shown in Figure 27. Once the counter terminates at 0, the li line will become inactive.

The li line can be used for various functions. It can be used to set the attenuator, DVGA or integrated controller and works with analog VGA. To simplify the use of this feature, the AD6634 includes two separate gain settings, one when the line is inactive (RCIC2_quiet[4:0] is stored in bits 9:5 of the 0x92 register) and one when it is active ( RCIC2_loud[4:0] is stored in bits 4:0 of register 0x92). This allows the digital gain to be adjusted for external changes. Combined with gain settings, variable hold is included to compensate for the ADC's pipeline delay and gain control element switching time. Together these two features provide seamless gain switching.

Another use of this pin is to facilitate gain range hold within the gain range adc. For converters that use gain scaling to increase the overall signal dynamic range, it may be necessary to disable internal gain scaling in some cases. For this converter, the li(a or b) line can be used to stop this. For this application, a higher threshold will be set based on similar conditions. However, the lower threshold will be set to a level consistent with the gain range of the particular converter. The delay can then be set appropriately for any of a number of factors such as fading profile, signal peak-to-average ratio, or any other time-based characteristic that may cause unwanted gain variation.

Because the AD6634 has a total of four gain control circuits, these circuits can be used if both the A and B input ports have interleaved data. Each corresponding lip pin is independent and can be set to different set points. It should be noted that the gain control circuit is broadband and implemented before any filtering elements to minimize loop delay. Any of the four channels can be set to monitor any of the four possible input channels (two in normal mode and four when the inputs are time-multiplexed).

The chip also provides appropriate scaling of the internal data based on the attenuation associated with the li signal. In this way, the data to the DSP maintains the correct scale value throughout, making it completely independent. Since there is usually a finite delay associated with external gain switching components, the AD6634 includes variable piping delays that can be used to compensate for external piping delays or total settling time associated with gain/attenuator devices. This delay can be set to seven high-speed clocks. These features ensure smooth switching between gain settings.

input data scaling

The AD6634 has two data input ports, an A input port and a B input port. Each accepts a 14-bit mantissa (two's complement integer) in [13:0], a 3-bit exponent (unsigned integer) exp[2:0], and input enable (ien). Both inputs are clocked by CLK. These pins allow direct connection to standard fixed-point ADCs, such as the AD9238 and AD6645, and gain-changing ADCs, such as the AD6600. For normal operation with less than 14 bits of ADC, the active bits should be msb justified and the unused lsb should be low bound.

The 3-bit exponent exp[2:0] is interpreted as an unsigned integer. The index will then be modified to RCIC2_U Loud[4:0] or RCIC2_U Quiet[4:0], depending on whether the li line is active. These 5-bit scale values are stored in the rcic2 scale register (0x92) and the scale is applied before the data enters the rcic2 resampling filter. These 5-bit registers contain scale values to compensate for RCIC2 gain, external attenuator (if used), and exponential offset (expoff). If the external attenuator is not used, the RCIC2_MUTE register and the RCIC2_LOUD register will contain the same value. Detailed instructions and formulas for setting the attenuation scale registers are given in the floating point scaling or gain ranging ADCs section.

fixed point adc scaling

For fixed-point ADCs, the ad6634 exponent input exp[2:0] is generally not used and should be limited to the low order bits. The ADC output is connected directly to the AD6634 input and is aligned with the main power distribution board. The expoff bit in 0x92 should be programmed to 0. Likewise, the exponent reversal bit should be 0. So for fixed point ADCs the exponent is usually static and no input scaling is used in AD6634.

An example of scaling exponential control features using floating point or gain ranging ADCs combines the AD6600 and AD6634. The AD6600 is an 11-bit ADC with a three-bit gain range. In effect, the 11-bit ADC provides the mantissa and 3-bit relative signal strength indicator (rssi) for the exponent. The AD6600 uses only five of the eight available steps. See the AD6600 data sheet for more details.

For gain ranging adc, such as ad6600:

where in is the value of in[13:0], exp is the value of exp[2:0], and rcic2 is the rcic tick register value (0x92 bits 9–5 and 4–0).

The RSSi output of the AD6600 increases numerically as the analog input signal strength increases (RSSi=5 for large signals and RSSi=0 for small signals). When the exponent inversion bit (expinv) is set to zero, the AD6634 will consider the smallest signal at in[13:0] to be the largest, and as the exp word increases, it internally shifts the data down (exp=5 will Shift the 14-bit word right by 5 internal bits before passing the data to RCIC2). In this example with expinv=0, the ad6634 treats the largest signal possible on the ad6600 as the smallest signal. So we can use the exponent reversal bit to make the ad6634 exponent consistent with the ad6600 rssi. By setting expinv=1, this forces the AD6634 to shift the data up (left) to increase exp, rather than down. The exponent reversal bit should always be set high for use with the AD6600.

Exponential offsets are used to move data up. For example, Table I shows that without RCIC2 scaling, 12 dB of range is lost when the ADC input is at its maximum level. This is undesirable because it reduces the dynamic range and signal-to-noise ratio of the system, reducing the signal of interest associated with the quantization noise floor.

To avoid this automatic decay of the full-scale ADC signal, expoff is used to shift the maximum signal (rssi=5) up to the point where there is no downshift. In other words, once the exponent inversion bit is set, the exponent offset should be adjusted so that mod(7–5+expoff,32)=0. This is the case when the exponent offset is set to 30 because mod(32, 32) = 0. Table II illustrates the usage of expinv and expoff when used with the AD6600 ADC.

This flexibility in processing indices allows the AD6634 to interface with ADCs with gain ranges other than the AD6600. The exponent offset can be adjusted to allow use of up to seven rssi(exp) ranges instead of the ad6600's five. It also allows the AD6634 to be customized in systems that use the AD6600 but do not take advantage of its full signal range. For example, if only the first four rssi ranges are expected, expoff can be adjusted to 29, which will make rssi=4 correspond to the 0db point of the ad6634.

CNC oscillator

frequency conversion

The processing stage includes a digital tuner consisting of two multipliers and a 32-bit complex nco. Each channel of the AD6634 has an independent NCO. The nco acts as a quadrature local oscillator capable of generating nco frequencies between -clk/2 and +clk/2 in complex mode with a resolution of clk/232. Worst-case spurious from nco is better than -100dbc for all output frequencies.

The nco frequency values in registers 0x85 and 0x86 are interpreted as 32-bit unsigned integers. The nco frequency is calculated by:

where nco_freq is a 32-bit integer (registers 0x85 and 0x86), fchannel is the desired channel frequency, and clk is the AD6634 master clock rate or input data rate, depending on the input enable mode used. See the Input Enable Control section.

NCO frequency holding register

When the nco frequency register is written, the data is actually passed to a shadow register. Data can be moved to the main register in one of two ways: when the channel comes out of sleep mode or when a sync hop occurs. In either case, the counter can be loaded with the nco frequency holding register value. The 16-bit unsigned integer counter (0x84) starts counting down from the master clock, and when it reaches zero, the new frequency value in the shadow register is written to the nco frequency register. The nco can also be set to synchronize immediately, in which case the frequency hold counter is bypassed and the new frequency value is updated immediately.

Phase offset

The phase offset register (0x87) adds an offset to the nco's phase accumulator. This is a 16-bit register, interpreted as a 16-bit unsigned integer. 0x0000 in this register corresponds to an offset of 0 radians, and 0xffff corresponds to an offset of 2 (1-1/(216)) radians. This register allows multiple NCOs to be synchronized to generate a sine wave with a known and stable phase difference.

NCO Control Register

The nco control register at 0x88 is used to configure the function of the nco. These are controlled on a per-channel basis, as described below.

bypass

The NCO on the front end of the AD6634 can be bypassed.

Bypass mode is enabled by setting Bit 0 high at 0x88. When it is bypassed, no down-conversion is performed and the ad6634 channel only works as an actual filter on complex data. This is useful for baseband sampling applications where the a input is connected to the i signal path within the filter and the b input is connected to the q signal path. This may be required if the digitized signal has been converted to baseband in a previous analog stage, or by other digital preprocessing.

Phase jitter

The AD6634 provides a phase jitter option for improving the spurious performance of the NCO. Phase jitter is enabled by setting bit 1. When phase dithering is enabled by setting this bit high, the pulses in the nco due to phase truncation are random. The energy from these spurs is diffused into the noise floor, and the spur-free dynamic range is increased, at the expense of a small reduction in signal-to-noise ratio. Whether or not phase jitter is used in the system ultimately depends on the system goals. This approach should be used if you want to reduce spurs at the expense of a slightly raised noise floor. Phase jitter is not required if a low noise floor is required and higher spurs can be tolerated or filtered by subsequent stages.

Amplitude jitter

Amplitude jitter can also be used to improve the spurious performance of the nco. Amplitude dithering is enabled by setting bit 2.

Amplitude dithering improves performance by randomizing the amplitude quantization error within the angular-to-Cartesian conversion range of nco. This option may reduce harshness at the expense of a slightly raised noise floor. Amplitude jitter and phase jitter can be used together, alone, or not at all.

Jump clear phase battery

When bit 3 is set, the nco phase accumulator is cleared before frequency hopping. This ensures that the phase of the nco at each hop is consistent. The NCO phase offset is not affected by this setting and is still in effect. If successive phase transitions are required, this bit should be cleared and the last phase in the nco phase register will be the starting point for the new frequency.

input enable control

There are four different modes of operation for input enable. Each high-speed input port contains an IEN line. Any of the four filter channels can be programmed to take data from the two A or B input ports. (See the WB Input Selection section.) Along with the data is the IEN(A,B) signal. Each filter channel can be configured to process the ien signal in one of four modes. When processing data based on a time division multiplexed data stream, three of these modes are associated. The fourth mode is used for applications that employ time division duplexing, such as radar, sonar, ultrasonic, and communications involving tdd.

Mode 00: IEN LOW is blank

In this mode, the data is hidden when the IEN line is low. There is new data on every rising edge of the input clock during the period when the IEN line is high. When lowering the IEN line, the input data is replaced with zero values. During this time, nco continues to run so that when the ien row is raised again, the nco value will be what it would have been if the ien row had never been lowered. This mode has the effect of making the digital input disappear when the IEN line is lowered. Backend processing (rcic2, cic5, and rcf) continues while the IEN line is high. This mode is useful for time division multiplexing applications.

Mode 01: IEN high clock

In this mode, data is clocked into the chip when the IEN line is high. There is new data on every rising edge of the input clock during the period when the IEN line is high. When the IEN line is lowered, incoming data is no longer locked into the channel. In addition, the progress of NCO was stopped. However, backend processing (rcic2, cic5, and rcf) continues during this time. The main use of this mode is to allow a clock faster than the input sample data rate to allow more filter taps to be computed than otherwise possible. In Figure 30, although CLK continues to run 4 times faster than data, incoming data is only toggled during the period when IEN is high.

Mode 10: IEN clock transitions high

In this mode, data only enters the chip on the first clock edge after the rising transition of the IEN line. Although data is only latched on the first valid clock edge, backend processing (rcic2, cic5, and rcf) continues on every available clock that may exist, similar to mode 01. The nco phase accumulator is incremented only once for each new input data sample and not once for each input clock.

Mode 11: IEN clock transitions low

In this mode, data is clocked into the chip on the first clock edge only after a falling transition on the IEN line. Although data is only locked on the first valid clock edge, backend processing (rcic2, cic5, and rcf) continues one for each available clock that may exist, similar to mode 01. The nco phase accumulator is incremented only once for each new input data sample and not once for each input clock.

WB input selection

Bit 6 in this register controls which input port is selected for signal processing. If this bit is set high, input port B (INB, EXPB and IENB) will be connected to the selected filter channel. If this bit is cleared, input port A (INA, EXPA, and IENA) will be connected to the selected filter channel.

Sync selection

Bits 7 and 8 of this register determine which external synchronization pin is associated with the selected channel. The AD6634 has four synchronization pins named synca, syncb, syncc, and syncd. Any of these sync pins can be associated with any of the four receiver channels within the AD6634. Additionally, if the system requires only one sync signal, all four receiver channels can reference the same sync pulse. Bit value 00 is channel A, 01 is channel B, 10 is channel C, and 11 is channel D.

second-order rcic filter

The RCIC2 filter is a second cascade resampling integrator comb filter. The resampler is implemented using a unique technique that does not require the use of a high-speed clock, simplifying the design and saving power. The resampler allows for a non-integer relationship between the master clock and the output data rate, which makes it easier to implement multimode or systems that require the use of a master clock that is not a multiple of the data rate.

RCIC2 allows up to 512 interpolations and up to 4096 decimations. The resampling factor for rcic2(l) is a 9-bit integer. When combined with the decimation factor m (a 12-bit number), the total rate change can be any fraction of the form:

The only restriction is that the L/M ratio must be less than or equal to 1. This means that RCIC2 has a lethality of 1 or more.

Resampling is accomplished by significantly increasing the input sampling rate by a factor l, using zero-padding for new data samples. Following the resampling is a second cascaded integrator comb filter. The filter characteristics are determined only by the fractional rate change (L/M).

The filter can process the signal at the full rate of the 80mhz input port. The output rate of this stage is given by the following equation:

Both lrccic2 and mrcic2 are unsigned integers. The interpolation rate (lrcci2) can be 1 to 512, and the decimation rate (mrcic2) can be 1 to 4096. This stage can be bypassed by setting the decimation to 1/1. The frequency response of the RCIC2 filter is given by the following equation:

The gain and passband attenuation of RCIC2 should be calculated from the above equation and the filter transfer equation that follows. At the rcf level, excessive passband attenuation can be compensated for by peaking the passband by the inverse of the roll-off.

The scale factor srcic2 is a programmable unsigned 5-bit between 0 and 31. This is an attenuator that reduces the gain of the RCIC2 in 6dB increments. For optimal dynamic range, srcic2 should be set to the smallest possible value (i.e. lowest attenuation) without creating an overflow condition. This can be done safely using the formula below, where

INPUT_LEVEL is the largest portion of the AD6634's (usually 1) input full scale. Always use the RCIC2 scale factor, whether bypassing RCIC2 or not.

In addition, two scale registers (RCIC2_loud[4:0] bits 4–0 in x92) and (RCIC2_quiet[4:0] bits 9–5 in x92) are used with the calculated SRCIC2, which determines the RCIC2’s Overall scale. The srcic2 value must be added to the value in each corresponding tick register and expoff to determine the tick value that must be placed into the rcic2 tick register. This number must be less than 32, or the interpolation and decimation rates must be adjusted to validate the formula. The ceil function represents the next integer, and the floor function represents the previous integer. For example, ceil(4.5) is 5 and floor(4.5) is 4.

where in is the value of in[13:0], exp is the value of exp[2:0], and rcic2 is the value of the tick register at 0x92 (rcic2_quiet[4:0] and rcic2_loud[4:0]).

RCIC2 rejected

Table 3 illustrates the amount of bandwidth (expressed as a percentage of the data rate) entering the rcic2 level. The data in this table can be scaled to any other allowed sampling rate, up to 80MHz in single channel mode and 40MHz in diversity channel mode. Table III can be used as a tool to decide how to allocate decimation between RCIC2, CIC5 and RCF.

Example calculation

Goal: Implement a filter with an input sample rate of 10mhz that requires 100db of aliasing rejection within a ±7khz passband. Solution: First determine the percentage of sample rate represented by the frequency band.

Find the –100dB column and look down for the value in that column that is greater than or equal to the passband percentage of the clock rate. Then look at the leftmost column to find the corresponding rate change factor (mrcic2/lrccic2). Referring to the table, note that for mrcic2/lrccic2 of 4, the frequency with -100db alias suppression is 0.071%, slightly more than the calculated 0.07%. Therefore, in this example, the maximum bound on the rate change of rcic2 is 4. Choosing a higher mrcic2/lrccic2 means less alias rejections than the required 100 db.

mrcic2/lrccic2 of less than 4 will still produce the desired rejection; however, power consumption can be minimized by decimation as much as possible in this rcic2 stage. Decimation in RCIC2 reduces the data rate, thereby reducing power consumption in subsequent stages. It should also be noted that there is more than one way to get a draw before 4. Decimating 4 equals an L/M ratio of 0.25. Therefore, any integer combination that yields an L/M of 0.25 is valid (1/4, 2/8, or 4/16). However, for optimal dynamic range, the simplest ratio should be used. For example, 1/4 has better performance than 4/16.

Decimation and Interpolation Register RCIC2 The decimation value is stored in Register 0x90. This is a 12-bit register that contains the decimation part minus 1. The interpolation part is stored in register 0x91. This 9-bit value keeps the interpolation less than 1.

proportional scale

Register 0x92 contains scaling information for this part of the circuit. The main function is to store the scale values calculated in the above sections.

Bits 4–0 (rcic2_loud[4:0]) of this register are used to contain the scale factor for rcic2 under strong signal conditions. These five bits represent the rcic2 scalar calculated above plus any external signal scale for the attenuator.

Bits 9–5 (rcic2_quiet[4:0]) of this register are used to contain the scale factor for rcic2 in weak signal conditions. In this register, external attenuators are not used and are not included. Only the value calculated above is stored in these bits.

Bit 10 of this register is used to indicate the value of the external exponent. If this bit is set low, each external exponent represents 6 dB per step in the AD6600. If this bit is set high, each index represents a 12-dB step.

Bit 11 of this register is used to invert the external exponent before the internal calculation. This bit should be set high for gain ranging ADCs that use an increasing exponent to represent increasing signal levels. This bit should be set low for gain ranging ADCs that use a decrementing exponent to represent increasing signal levels.

In applications that do not require the RCIC2 feature, the L/M ratio can be set to 1/1. This effectively bypasses all of RCIC2's circuitry except for scaling which is still valid.

5th order cic filter

The third signal processing stage cic5 implements a sharper fixed coefficient decimation filter than rcic2. The input rate for this filter is fsamp2. The maximum input rate is given by the following equation. For diversity channel actual input mode, NCH is equal to 2; otherwise NCH is equal to 1. To satisfy this equation, mrcic2 can be increased, nch decreased, or fclk increased (reference fractional rate input timing is described in the Input Timing section).

The decimation rate mcic5 is programmable from 2 to 32 (all integer values). The frequency response of the filter is given by the following equation. The gain and passband attenuation of cic5 should be calculated using these equations. Both of these parameters can be compensated during the revolving loan phase.

The scale factor scic5 is between 0 and 20. It is used to control data decay to cic5 level in 6db increments. For best dynamic range, SCIC5 should be set to the smallest possible value (lowest attenuation) without creating an overflow condition. This can be safely achieved using the following equation, where olrcic2 is the largest part of the input full scale of this filter stage. This value is output from the RCIC2 stage, which is then piped to CIC5.

The output rate at this stage is given by:

CIC5 Rejection

Table IV shows the amount of bandwidth, expressed as a percentage of the clock rate, that can be protected with various decimation rates and alias rejection specifications. When RCIC2 is decremented by 1, the maximum rate input to CIC5 is 80 MHz. As shown in Table 3, these are half bandwidth characteristics of cic5. Note that the cic5 stage protects a wider band from any given rejection.

ram coefficient filter

The final signal processing stage is the sum of products of decimation filters with programmable coefficients. A simplified block diagram is shown in Figure 31. The data memories i-ram and q-ram store the 160 latest complex samples from the previous filtering stage at 20-bit resolution. The coefficient memory cmem stores up to 256 coefficients with 20-bit resolution. In each clk cycle, one tap for i and one tap for q are computed using the same coefficients. The RCF output consists of 24 data bits.

Revolving Loan Extraction Register

Each RCF channel can be used to reduce the data rate. The decimation register is an 8-bit register that can decimate from 1 to 256. The revolving loan draw is stored in 0xa0 as MRCF-1. The input rate for the revolving loan is fsamp5.

Revolving Loan Extraction Phase

The RCF decimation stage can be used to synchronize multiple filters within the chip. This is useful when implementing a polyphase filter using multiple channels in the AD6634, allowing resource parallelism for multiple filters. In this application, two revolving loan filters will process the same data from cic5. However, each filter will be delayed by half the decimation rate, resulting in a 180 degree phase difference between the two halves. The AD6634 filter channel uses the value stored in this register to preload the RCF counter. So instead of starting at 0, the counter is loaded with this value, creating an offset in processing that should be equal to the desired processing delay. This data is stored in 0xA1 as an 8-bit number.

RCF filter length

The maximum number of taps nTaps that can be calculated by this filter is given by the following equation. The value ntaps – 1 is written to the channel register at Address 0xA2 in the AD6634.

The rcf coefficients are located at addresses 0x00 to 0x7f and are interpreted as 20-bit 2's complement. When writing to coefficient ram, the lower address will be multiplied by the relatively old data from cic5 and the higher coefficient address will be multiplied by the relatively newer data from cic5. The coefficients do not have to be symmetric, and the coefficient length ntaps can be even or odd. If the coefficients are symmetric, both sides of the impulse response must be written into the coefficients ram.

Although the base memory for coefficients is only 128 words long, the actual length is 256 words long. There are two pages of 128 words each. The page is selected by bit 8 of 0xA4. Although this data must be written in pages, the internal core handles filters over 128 taps in length. Therefore, the full length of the data ram can be used as the filter length (160 taps).

The revolving loan stores data from cic5 into a 160x40 ram.

160 x 20 is assigned to i data and 160 x 20 is assigned to q data. rcf uses ram as a circular buffer, so it's hard to know at which address a particular data element is stored.

When the rcf is triggered to compute the filter output, it first multiplies the oldest value in the data ram by the first coefficient, which is indicated by the rcf coefficient offset register (0xa3). The product of this value and the newer data word multiplied by subsequent locations in coefficient ram is accumulated until the coefficient address rcfoff+ntaps–1 is reached.

The revolving loan factor offset register can be used for two purposes. The main purpose of this register is to allow multiple filters to be loaded into memory and selected by changing the offset as a pointer to quick filter changes. Another use of this register is to form part of symbol timing adjustments. If the desired filter length is padded with zeros at the end, the starting point can be adjusted to create a slight delay in computing the filter with reference to the high-speed clock. This allows the cursor to adjust symbol timing. Course adjustments can be made during the revolving loan draw phase.

The output rate of this filter is determined by the output rate of the cic5 stage and mrcf:

Revolving Loan Output Scale Factor and Control Register Register 0xA4 is a composite register that configures several aspects of the RCF register. Bits 3–0 are used to set the scale for fixed-point output mode. The scale value can also be used in conjunction with bit 6 of this register to set the floating point output.

Bits 4 and 5 determine the output mode. Mode 00 sets the chip to fixed-point mode. The number of bits is determined by the parallel or link port configuration.

Mode 01 selects floating point mode 8+4. In this mode, an 8-bit mantissa is followed by a 4-bit exponent. In mode 1x (x doesn't matter), the mode is 12+4, or 12 bits of mantissa and 4 bits of exponent.

Typically, the AD6634 will determine the exponent value that optimizes numerical precision. However, if bit 6 is set, the output is scaled using the value stored in bits 3–0. This ensures consistent scaling and accuracy where a predictable output range is possible. If bits 3–0 are represented by the rcf scale, the scale factor (unit: db) is given by:

For a level 0 revolving loan, the scaling factor is equal to -18.06 decibels; for a level 15 revolving loan, the scaling factor is equal to 72.25 decibels.

If bit 7 is set, the real and imaginary outputs (i and q) will use the same exponent. The exponent used will be one that prevents numeric overflow at the expense of small-signal precision. However, this is rarely a problem since small numbers represent 0 regardless of the exponent used.

Bit 8 is the revolving loan bank select bit for register programming. When this bit is 0, the lowest block of 128 is selected (tap 0 to 127). When high, select the tallest block (tap 128 to 255). Note that while the chip is a computational filter, TAP 127 is adjacent to 128 and has no paging issues.

Bit 9 selects the input source for each revolving loan. If bit 9 is clear, the revolving loan input is from CIC5 normally associated with revolving loans. However, if the bit is set, the input is from cic5 channel 1. The only exception is channel 1, which uses the output of cic5 channel 0 as its alternate channel. Using this feature, each RCF can operate on its own channel data or pair with the channel 1 RCF. The rcf of channel 1 can also be paired with channel 0. This control bit is used for polyphase distributed filtering.

If Bit 10 is cleared, the AD6634 channel operates in normal mode.

However, if bit 10 is set, the RCF is bypassed to channel BIST. See the BIST (Built-In Self-Test) section for more details.

Interpolating half-band filter

The AD6634 has two interpolating half-band finite impulse response filters immediately preceding the two digital AGCs and following the four RCF channel outputs. Each interpolated half-band receives 16-bit i and 16-bit q data from the preceding rcf and outputs 16-bit i and 16-bit q to the agc. The half-band and the agc work independently, so the agc can be bypassed, in which case the output of the half-band is sent directly to the output data port. The half-bands also work independently and can be enabled or disabled. The control register for half-band A is at address 0x08, and the control register for half-band B is at address 0x09.

The half-band filter also performs the function of outputting interleaved data from the various rcf channels before the actual function.

interpolation. This data interleaving is allowed even if the actual function of the half-band filter is bypassed. This feature allows the use of multiple channels (implementing a polyphase filter) on the AD6634 to process a single carrier. Appropriate phase adjustments are made to the channel using RCF phase extraction or the channel's start hold counter. For example, if two channels of an ad6634 are used to process a cdma2000 carrier, the rcf filters for the two channels should be 180° out of phase. This can be achieved by using rcf phase decimation or an appropriate starting delay counter followed by an appropriate nco phase offset.

Half-band A can listen to all four channels: 0, 1, 2, and 3; channels 0 and 1; or just channel 0. Half-band B can listen to channels 2 and 3, or only channel 2. Each half-band interleaves the channels specified in its control register and interpolates the combined data from those channels 2 times. For one channel operating at twice the chip rate, half the frequency band can be used to output channel data at 43 chip rate.

Regarding the slice rate, the frequency response of the interpolated half-band fir is shown in Figure 32.

automatic gain control

The AD6634 is equipped with two independent automatic gain control (AGC) loops for direct interface with RAKE receivers. Each agc circuit has a range of 96db. Importantly, the decimation filter of the AD6634 before the AGC rejects unwanted signals so that each AGC loop operates only on the carrier of interest, and carriers of other frequencies do not affect the ranging of the loop.

The AGC compresses the 23-bit complex output of the interpolated half-band filter into a programmable word size of 4–8, 10, 12 or 16 bits. Since the small signal from the lower bits is pushed into the higher bits by increasing the gain, clipping of the lower bits does not impair the signal-to-noise ratio of the signal of interest. The AGC maintains a constant average power at the output regardless of the signal level of interest, allowing operation in environments where the dynamic range of the signal exceeds that of the output resolution.

The agc and interpolation filters are not tied together, either (or both) can be chosen without the other. If desired, the agc part can be bypassed by setting bit 0 of the agc control word. When bypassed, the i/q data is still clipped to the required number of bits and constant gain can be provided by the AGC gain multiplier.

There are three sources of errors introduced by the agc function: underflow, overflow, and modulation. Underflow is caused by bit truncation below the output range. Overflow is caused by a clipping error when the output signal exceeds the output range. Modulation errors occur when the output gain changes during reception of data.

The desired signal level should be set according to the probability density function of the signal to balance errors due to underflow and overflow. The gain and damping values of the loop filter should be set so that the agc is fast enough to track long-term amplitude variations of the signal that can cause excessive underflow or overflow, but slow enough to avoid excessive amplitude information due to signal modulation lost.

Automatic gain control loop

The agc loop adopts a log-linear structure. It contains four basic operations: power calculation, error calculation, loop filtering and gain multiplication.

The agc can be configured to operate in one of two modes: the desired signal level mode or the desired slice level mode set by Bit 4 of the agc control word (0x0a, 0x12). The agc adjusts the gain of the incoming data according to the distance from a given desired signal level or desired clipping level, depending on the selected operating mode. Two data paths are provided to the agc loop: one before the clipping circuit and one after the clipping circuit, as shown in Figure 33. For the desired signal level pattern, just use the I/Q path before the clip. For the desired clipping level pattern, use the difference of the i/q signal before and after the clipping circuit.

Desired Signal Level Mode

In this mode of operation, the AGC strives to maintain the output signal at a programmable level. This mode of operation is selected by entering a value of 0 in Bit 4 of the AGC Control Word (0x0A, 0x12). First, the loop determines the square (or power) of the incoming complex data signal by squaring i and q and adding them together. This operation is implemented using 2x (powers of 2) in the exponent domain.

The AGC loop has an average blocking and a fatal blocking. This averaging and decimation operation occurs on power samples, and before the square root operation. This block can be programmed to average 1-16384 power samples, while the Decimate section can be programmed to update the AGC every 1-4096 samples. A limitation of the averaging operation is that the number of samples of the average power should be a multiple (1, 2, 3 or 4) of the decimation value.

Averaging and decimation effectively means that the AGC can operate at an average power of 1-16384 output samples. Choosing to update the AGC every 1-4096 samples and running at average power helps to achieve a loop filter with a slow time constant, where the AGC error converges slowly, and infrequent gain adjustments are made. It is also useful in cases where the user wants to keep the gain scaling constant over the data frame (or symbol stream).

Since the limit on the average number of samples is a multiple of the drawn value, only multiples of 1, 2, 3, or 4 are programmed. This number is programmed in bits 1, 0 of the 0x10 and 0x18 registers. These average samples are then decimated with a decimation rate programmable from 1 to 4096. This decimation rate is defined in 12-bit registers 0x11 and 0x19.

The averaging and decimation operations are bundled together and implemented using a first-order cic filter and some fifo registers. The gain and bit growth associated with the cic filter depends on the decimation rate. To compensate for the gain associated with these operations, attenuation scaling is provided before the cic filter.

This scaling operation explains the division associated with the averaging operation and the traditional bit growth in the cic filter. Since this scaling is implemented as a bit-shift operation, only coarse scaling is possible. In the request level explained later, the fine scale is implemented as an offset. The attenuation scale scic is programmable from 0 to 14 using four bits of the 0x10 and 0x18 registers and is given by:

where mcic is the decimation rate (1–4096) and navg is the average number of samples programmed as a decimation rate multiple (1, 2, 3, or 4).

For example, if the decimation ratio mcic is 1000, and the navg is chosen to be 3 (1000 samples are drawn, 3000 samples are averaged), the actual gain produced by the averaging and decimation is 3000 or 69.54 db (=log2(3000)). Since the attenuation is implemented as a displacement operation, only multiples of the 6.02db attenuation are possible. In this case, the scic is 12, which is equivalent to 72.24db. This way, the SCIC scale is always attenuated enough to compensate for gain changes in the averaging and subtracting parts, preventing overflow in the AGC loop. It is also evident that cic scaling can cause up to 6.02dB of gain error (the difference between the gain caused by the cic and the attenuation provided). This error should be compensated in the request signal level as described below.

The logarithm to base 2 is applied to the output of the "Average" and "Decimation" sections. These decimated power samples (in the logarithmic domain) are converted to rms signal samples by applying the square root. This square root is implemented with a simple shift operation. The rms samples thus obtained are subtracted from the request signal level r specified in registers (0x0b, 0x14), leaving an error term processed by the loop filter g(z).

The user sets the programmable request signal level r according to the desired output signal level. The request signal level r is programmed from -0db to -23.99db in 0.094db steps. As mentioned, the request signal level should also compensate for errors (if any) due to cic scaling. Therefore, the request signal level is offset by the amount of error induced in cic, by:

where the offset is in db. Continuing the previous example, this offset is given by, offset=72.24–69.54=2.7 dB. The request signal level is given by:

where r is the request signal level and dsl (desired signal level) is the user desired output signal level. In the previous example, if the desired signal level was -13.8db, the request level r was programmed to be -16.54db.

agc provides programmable second order loop filter. The programmable parameters gain k and pole p fully define the characteristics of the loop filter. The error term after subtracting the request signal level is processed by the loop filter g(z). The open-loop poles of the second-order loop filter are 1 and p, respectively. The loop filter parameters pole p and gain k allow adjustment of the filter time constant that determines the window for calculating the peak-to-average ratio.

The open-loop transfer function of the filter (including the gain parameter) is as follows:

If the agc is configured correctly (according to the offset in the requested level), there is no gain other than the filter gain k. In this case, the closed-loop expression of the agc loop is possible and is given by:

The gain parameter k and pole p are programmable from 0 to 0.996 using an 8-bit representation in steps of 0.0039 via registers (agc channels a and b are 0x0e and 0x0f respectively). Although the user defines the open loop pole p and gain k, they will directly affect the closed loop pole location and filter characteristics. These closed-loop poles p1, p2 are the roots of the denominator of the closed-loop transfer function above, given by:

Typically, the performance of an AGC loop is defined in terms of its time constant or settling time. In this case, the closed loop poles should be set to satisfy the time constant required by the AGC loop. The following relationship between the time constant and the closed loop poles can be used for this purpose.

where τ1,2 is the time constant corresponding to the pole p1,2. The time constant can also be derived from the settling time given below:

mcic (cic decimation from 1 to 4096), user should select settling time or time constant. The sample rate is the combined sample rate of all interleaved channels entering the AGC/Half-Band Interpolation Filter. If two channels are used to process a umts carrier at a 2-chip rate, each channel operates at 3.84mhz and the combined sampling rate into the half-band interpolation filter is 7.68msps. If the half-band interpolation filter is bypassed, this rate should be used when calculating the poles in the above equation.

The loop filter output corresponds to the signal gain updated by the AGC. Since all computations of the loop filter are done in the logarithmic domain (base 2) of the samples, the signal gain is generated using the exponent (power of 2) of the loop filter output.

The gain multiplier gives the product of the signal gains of the i and q data input to the AGC section. This signal gain is used as a coarse 4-bit scaling followed by a fine 8-bit multiplier. Therefore, in 0.024db steps, the applied signal gain is between 0db and 96.296db. The initial value of the signal gain is programmable using registers 0x0d and 0x15 of agc a and agc b, respectively.

The product of the gain multipliers, the agc scale output, has a 19-bit representation. They are used in turn as i and q for calculating power and AGC error, and loop filtering to produce the signal gain for the next set of samples. These AGC scale outputs can be programmed to have a width of 4, 5, 6, 7, 8, 10, 12 or 16 bits using the AGC Control Word (0x0a, 0x12). As shown in the block diagram, a clipping circuit is used to truncate the AGC scaled output to the desired bit width.

Open loop gain setting

If the filter gain k occupies only one lsb or 0.0039 during multiplication with the error term, up to 6.02db of error can be truncated. This truncation is due to the lower bit width available -

Able to work in AGC loop. If the filter gain k is the maximum value, the truncation error is less than 0.094db (equivalent to 1lsb expressed by the error term). Typically, a small filter gain is used to implement a large time constant loop (or slow loop), but in this case it causes large errors to go undetected. Because of this feature, designers recommend that if users want a slow agc loop, they use a fairly high value of filter gain k, and then use cic decimation to implement the slow loop. In this way, the agc loop will produce large infrequent gain changes compared to the small and frequent gain changes of conventional small gain loop filters. However, despite the large infrequent gain changes of the AGC loop, a slow time constant is still obtained with a small truncation of the error.

Average sample setting

While it's difficult to accurately represent the effect of the average number of samples, it is intuitive to think that it has a smoothing effect on the way the AGC loop attacks abrupt increases or spikes in signal level. If the average of the four samples is used, the AGC will attack sudden increases in signal level more slowly than if the average is not used. The same applies to the way the agc attacks a sudden drop in signal level.

desired clip level mode

As previously mentioned, each AGC can be configured so that the loop locks to a desired clipping level or a desired signal level. The desired clipping level mode can be selected by setting Bit 4 of a single AGC control word (0x0A, 0x12). For signals that tend to exceed the peak-to-average ratio bounds, the desired clip level option allows a way to avoid clipping these signals and still provide agc that quickly attacks and settles to the desired output level. The signal paths for this mode of operation are indicated by broken arrows in the functional block diagram, and the operation is similar to the desired signal level mode.

First, the data from the gain multiplier is truncated to the lower resolution (4, 5, 6, 7, 8, 10, 12 or 16 bits) set by the AGC control word. An error term (i and q) is produced, which is the difference between the signal before and after truncation. This term is passed to the complex squared magnitude block to average and decimate the update samples and take the square root of it to find the rms samples in the desired signal level mode. Instead of requesting the desired signal level, the desired clipping level is subtracted, leaving an error term processed by the second order loop filter. The rest of the loop works in the same way as the desired signal level pattern. The truncation error is calculated in this way, and the agc loop maintains a constant level of truncation error.

Aside from bit 4 of the agc control word, the only register setting change compared to the desired signal level mode is that the desired clip level is stored in the agc desired level registers (0x0c, 0x15) instead of Request signal level (as in required signal level mode).

Synchronize

With the AGC output connected to a rake receiver, the rake receiver can synchronize the averaging and update sections to update the average power for the AGC error calculation and loop filtering. This external synchronization signal synchronizes the AGC changes to the rake receiver and ensures that the AGC gain word does not change over a symbol period, resulting in a more accurate estimate. This synchronization can be achieved by setting the appropriate bits in the agc control register.

When the channel comes out of sleep, it loads the AGC hold counter value and starts counting down, clocked by the master clock. When this counter is zero, the cic filter of the agc starts decimation and the agc loop filter is updated based on the set of cic decimation values.

Additionally, the appropriate hold value can be set in the agc hold counter (0x0b, 0x13) and the sync now bit (bit 3) in the agc control word is set whenever the user wants to synchronize the start of the decimation of a new update sample. When this bit is set, the hold counter value is counted down and the cic decimated value is updated when the count is zero.

While updating the new value, the CIC filter accumulator can be reset if the init on sync bit (bit 2) of the AGC control word is set. Each sync will initiate a new sync signal unless the first sync-only bit (bit 1) of the AGC control word is set. If the bit is not set, wait for the counter to reload with the value in the wait register to count down and repeat the same process. These additional features make agc synchronization more flexible and suitable for a variety of situations.

Addresses 0x0a–0x11 are reserved for configuring AGC

A and addresses 0x12–0x19 are reserved for configuring AGC B. The register specifications are detailed in the "Memory Map of Output Port Control Registers" section.