Pin Description Package Overview Pin Table Schematic Introduction
The Spartan-3E family of Field Programmable Gate Arrays (FPGAs) is specifically designed to meet high-volume, cost-sensitive consumer electronics applications. , five-person households offer system door densities ranging from 100,000 to 1.6 million.
The spartan-3e series is based on the earlier spartan-3 series, which significantly reduces the cost per logic unit by increasing the amount of logic per I/O. New features improve system performance and reduce configuration costs. Combined with advanced 90nm process technology, these SPARTAN-3E enhancements deliver more features and bandwidth per dollar than ever before, setting a new standard for the programmable logic industry.
Due to its extremely low cost, Spartan-3E FPGAs are ideal for a wide range of consumer electronics applications including broadband access, home networking, display/projection and digital TV equipment.
The Spartan 3e series is an alternative to mask programming asic. FPGAs avoid the high initial costs, lengthy development cycles and inherent flexibility of traditional ASICs. In addition, the programmability of FPGAs allows for field design upgrades without the need for hardware replacement, which is not possible in ASICs.
Features

Very low-cost, high-performance logic solution for high-density, consumer-facing applications, proven advanced 90nm process technology, multi-voltage, multi-standard SelectIO interface pins - up to 376 I/O pins Or 156 differential signal pairs - LVCMOS, LVTTL, HSTL and SSTL single-ended signal standards - True LVDS, RSD, Mini LVDS differential input and output 3.3V, 2.5V, 1.8V, 1.5V and 1.2V signals - Enhanced Dual Data Rate (DDR) Support - Rich, Flexible Logic Resources - Density Up to 33192 Logic Cells, Including Optional Shift Register or Distributed RAM Support - High Efficiency Broad Multiplexer, Wide Logic - Fast Look-Ahead Carry Logic - Enhanced 18 x 18 multiplier with optional pipelining - IEEE 1149.1/1532 jtag programming/debug ports, hierarchical selectram memory structure - Fast block ram up to 648 kbits - Efficient distributed ram up to 231 kbits, up to 8 Digital Clock Manager (dcms) - Clock Skew Cancellation (Delay Locked Loop) - Frequency Synthesis, Multiplication, Division - High Resolution Phase Shifting - Wide Frequency Range (5 MHz to over 300 MHz), 8 global clocks per half device and 8 clocks, plus rich low skew routing, configuration interface to industry standard PROMs - low cost, space saving SPI serial flash PROM - X8 or X8/X16 parallel NOR flash PROM - low cost Xilinx platform flash with JTAG , Full Xilinx ISE, Webpack Development System Support, Microblaze, PicoBlaze Embedded Processor Cores, Fully Compatible 32/64-bit 33/66 MHz PCI Support, Low Cost QFP and BGA Package Options - Universal Package Enables Easy Density Migration - Lead-free packaging options

ARCHITECTURAL OVERVIEW The Spartan 3e family structure consists of five basic programmable functional elements:
Configurable logic blocks (CLBs) contain flexible look-up tables (LUTS) that implement logic plus storage elements that act as flip-flops or latches. clb performs various logical functions and stores data. The Input/Output Block (IOB) controls the flow of data between the I/O pins and the logic inside the device. Each iob supports bidirectional data flow and tri-state operation. Multiple signaling standards are supported, including four high-performance differential standards. Includes double data rate (DDR) registers. Block RAM provides data storage in the form of 18kbit dual port blocks. The multiplier block accepts two 18-bit binary numbers as input and computes the product.
The Digital Clock Manager (DCM) module provides a self-calibrating all-digital solution for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.
The organization of these elements is shown in Figure 1. An iob ring surrounds a regular array of clbs. Each device has two columns of block ram, except the xc3s100e has one column. Each ram column consists of several 18kbit ram blocks. Each block of ram is associated with a dedicated multiplier. The DCMs are in the center of the device, two are on the top of the device, and two are on the bottom of the device. The xc3s100e has only one dcm at the top and bottom, while the xc3s1200e and xc3s160e add two dcms in the middle of the left and right sides.
The Spartan 3e family possesses a rich network of traces connecting all five functional elements, transmitting signals between them. Each functional element has an associated switch matrix, allowing multiple connections to be routed.
number

Configuration Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable static CMOS configuration latches (CCLS), which collectively control all functional elements and routing resources. The configuration data of the fpga is stored in an external prom or other non-volatile medium, either on or off the board. After power up, use any of seven different modes to write configuration data to the FPGA:
, Master serial port from Xilinx platform flash PROM, Serial Peripheral Interface (SPI) from industry standard SPI serial flash, Byte Peripheral Interface (BPI) from industry standard X8 or X8/X16 parallel or non-flash From the serial port, usually from the processor, from the parallel, usually from the processor, and from Boundary Scan (JTAG), usually from the processor or system tester.
I/O capability The spartan-3e fpga selectio interface supports many popular single-ended and differential standards.
Spartan-3E FPGAs support the following single-ended standards:
3.3V, Low Voltage TTL, LVTTL, Low Voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V or 1.2V 3.3V PCI at 33 MHz and 66 MHz, HSTL I and III at 1.8V, typically SSTL I at 1.8V and 2.5V for memory applications, typically used for memory applications Spartan 3E GT supports the following different standards:
LVD, bus LVD, mini LVD, RSD

Packaging logo
Top marking for Spartan-3E FPGAs in BGA packages except 132 ball chip scale packages (CP132 and CPG132). The markings for the bga package are almost identical to those for the quad flat package, except that the markings are rotated relative to the ball a1 indicator.
Top markings for Spartan-3E FPGAs in CP132 and CPG132 packages.

As described in the Architecture Overview, the Spartan-3E FPGA architecture consists of five basic functional elements:
Input/Output Block (IOB), Configurable Logic Block (CLB) and Slice Resources, Block RAM, Dedicated Multiplier, Digital Clock Manager (DCM)
The following sections provide details on these features. In addition, this section describes the following features:
Clock Infrastructure, Interconnect, Configure, Power Spartan-3e FPGAs Input/Output Block (IOB)
IOB Overview Input/Output Blocks (IOBs) provide a programmable, unidirectional or bidirectional interface between package pins and the FPGA's internal logic. The IOB is similar to the Spartan-3 family with the following differences:
Add input-only block 8226 ; programmable input delay added to all blocks • DDR flip-flops can be shared between adjacent IOBs unidirectional input-only blocks have a subset of full IOB functionality. Therefore, the output path has no connections or logic. The following paragraphs assume that any references to output functions do not apply to input-only blocks. The number of input-only blocks varies with device size, but does not exceed 25% of the total IOB count.
There are three main signal paths in the IOB: the output path, the input path, and the tristate path. Each path has its own pair of storage elements, which can act as registers or latches. For more information, see Stored Element Functions. The three main signal paths are as follows: The input path carries data directly from the pad (the pad is connected to the package pin) to the I line through an optional programmable delay element. After the delay element, there is alternate routing to the iq1 and iq2 lines through a pair of storage elements. The iob outputs i, iq1 and iq2 point to the internal logic of the FPGA. The delay element can be set to ensure zero hold time (see Input Delay Function). The output path, starting from the O1 and O2 lines, transfers data from the FPGA internal logic through the multiplexer and then to the IOB board through a tri-state driver. In addition to this direct path, the multiplexer offers the option of inserting a pair of storage elements. The three-state path determines when the output driver is high impedance. The T1 and T2 lines pass data from the FPGA's internal logic to the output drivers through a multiplexer. In addition to this direct path, the multiplexer offers the option of inserting a pair of storage elements. All signal paths into the IOB, including those associated with storage elements, have an inverter option. Any inverters placed on these paths are automatically absorbed into the IOB.

Input Delay Function Each IOB has a programmable delay block that can delay the input signal from 0 to a nominal 4000 ps. In Figure 2, the signal is first delayed by 0 or 2000 ps (nominal) and then applied to an 8-tap delay line. The delay line is nominally 250 ps per tap. All 8 taps can be used directly as asynchronous inputs into the FPGA fabric via the multiplexer. In this way, a delay from 0 to 4000 ps can be programmed in 250 ps steps. 4 of the 8 taps can also be connected to the d input of the synchronous storage element through a multiplexer. The delay inserted in the path to the storage element can vary from 0 to 4000 ps in 500 ps steps. First, the coarse delay element is common to both asynchronous and synchronous paths and must be used or not used for both paths.
Delay values are set once in silicon at configuration time, they are not modifiable during device operation.
The main purpose of the input delay element is to act as a sufficient delay to ensure that no hold time is required when using the input flip-flop with the global clock. The necessary value for this function is chosen by the xilinx software tool and depends on the device size. If the design is to use dcm in the clock path, then the delay element can be safely set to zero in the user's design and still have no hold time requirements.
Both asynchronous and synchronous values can be modified by the user, which is useful in situations where additional latency is required for clock or data input, for example, in interfaces to various types of RAM.

Storage Element Function There are three pairs of storage elements per iob, one pair for each of the three paths. Each of these storage elements can be configured as an edge-triggered d-type flip-flop (fd) or a level-sensitive latch (ld).
Pairs of storage elements on the output path or tri-state path can be used with dedicated multiplexers to produce double data rate (DDR) transfers.
This is accomplished by converting data synchronized to the rising edge of the clock signal into bits that are synchronized on the rising and falling edges. The combination of two registers and a multiplexer is called a double data rate d-type flip-flop (oddr2).

ck input to the lower register on the state path. The upper and lower registers on the input path have separate clock lines: ICLK1 and ICLK2.
The oce enable line controls the ce input of the upper and lower registers on the output path. Likewise, tce con
trols the ce input of the register pair on the tristate path, ice does the same for the register pair on the input path.
The set/reset(sr) line into the iob controls all six registers, as does the reverse(rev) line.

Double Data Rate Transfer Double Data Rate (DDR) transfer describes a technique for synchronizing a signal to the rising and falling edges of a clock signal. SPARTAN-3E devices use register pairs in all three IOB paths to perform DDR operations.
A pair of storage elements (off1 and off2) on the IOB output path acts as a register, combined with a special multiplexer to form an DDR D-type flip-flop (oddr2). This primitive allows DDR transfers where the output data bits are synchronized with the rising and falling edges of the clock. DDR operation requires two clock signals (usually 50% duty cycle), one is the inverse of the other. These signals alternately trigger two registers, and the digital clock manager (DCM) generates two clock signals by mirroring one input signal and then shifting it 180 degrees. This method ensures minimal deviation between the two signals. Alternatively, an inverter inside the iob can be used to invert the clock signal, so just use one clock line and the rising and falling edges of that clock line as two clocks for the ddr flip-flop.
Pairs of storage elements on tri-state paths (tff1 and tff2) can also be combined with local multiplexers to form DDR primitives. This allows the output to be synchronized to the rising and falling edges of the clock. This ddr operation is implemented in the same way as the output path.
The pair of storage elements on the input paths (iff1 and iff2) allow the i/o to receive the ddr signal. An incoming DDR clock signal triggers one register, and an inverted clock signal triggers the other register. The registers take turns capturing the bits of the incoming ddr data signal. The primitive that allows this functionality is called iddr2.
In addition to high bandwidth data transfer, the ddr output can be used to reproduce or mirror the clock signal at the output. This method is used to transmit clock and data signals simultaneously (sync source). A similar approach is used to reproduce the clock signal at multiple outputs.

Register Cascading Feature In the spartan-3e family, one IOB in a differential pair can cascade its input or output storage elements with storage elements in the other IOB in the differential pair. This is to make high-speed ddr operations easier to implement. New DDR connections available (dotted line), only for routing between IOBs, not for the FPGA fabric. Note that this feature is only available when using differential I/O.
The IDDR2 number is used as a DDR input pair, and the main IOB registers the input data on the rising edge of iclk1 (=d1) and the rising edge of iclk2 (=d2), which is usually the same as the falling edge of iclk1. These data are then transferred into the fpga structure. At some point, both signals must be brought into the same clock domain, usually iclk1. This can be difficult at high frequencies because, assuming a 50% duty cycle, the available time is only half the clock period.
In spartan-3e devices, the signal d2 can be cascaded into the memory cells of adjacent slave IOBs. There it is re-registered to IClk1 before being fed into the FPGA fabric, at which point it is already in the same time domain as D1. Here, the fpga structure only uses the clock iclk1 to process the received data.
oder 2
As a DDR output pair, the master IOB registers data from the FPGA fabric on the rising edge of oclk1 (=d1) and the rising edge of oclk2 (=d2), which is usually the same as the falling edge of oclk1. These two bits of data are multiplexed by the ddr mux and forwarded to the output pins. At some point in the fpga structure, the signal d2 must be brought into the clock domain oclk2 from the oclk1 domain. This can be difficult at high frequencies as only half a clock cycle is available.
In the spartan-3e device, the signal d2 can be cascaded through the memory cells of the adjacent slave iob. Here, it is registered by oclk1, then forwarded to the main IOB, where it is re-registered to oclk2, selected by the ddr multiplexer as usual, and then forwarded to the output pin. In this way, just use the clock oclk1 in the fpga structure to process the data for transmission

Select Signal Standard
The Spartan-3E I/O inputs and outputs support a wide range of I/O signal standards (Tables 3 and 4). Most I/Os can also be used to form differential pairs to support any differential signaling standard (Table 4).
SPARTAN-3E FPGAs provide additional input flexibility by allowing I/O standards to be mixed in different banks. Special care must be taken to ensure that the input voltage does not exceed VCCO (. For a specific VCCO voltage, Table 3 and Table 4 list all IOS standards that can be combined, and whether the IOS standard is supported as input only, or available for both input and output.

The hstl and sstl inputs use a reference voltage (vref) to bias the input switching thresholds. Once a configuration data file is loaded into an FPGA that requires a given bank's i/o to use hstl/sstl, some specific reserved i/o pins of the same bank are automatically converted to vref inputs. For groups that do not contain hstl or sstl, the vref pins can still be used for user i/o or input pins.
Differential standards use a pair of signals with opposite polarities. The noise cancellation features of these standards (eg, common mode rejection) allow exceptionally high data transfer rates. This subsection describes the differential signaling capabilities of SPARTAN-3E devices.
Each device package combination specifies a specific I/O pair, specifically optimized to support differential criteria. Differential pairs can be displayed in the Pin and Area Constraint Editor (PACE) via the "Show Differential Pairs" option. A unique L number (as part of the pin name) identifies the wire pair associated with each tube group. For each pair, the letters p and n represent solid and inverted lines, respectively. For example, the pin names io_l43p_3 and io_l43n_3 indicate the true and inverted lines consisting of the line pair l43 on column 3. VCCO provides current to the output and additional power for the on-chip differential termination. When using on-chip differential termination, VCCO must be 2.5V. Differential operation does not require a VREF line.
On-Chip Differential Termination The SPARTAN-3E device provides on-chip 100Ω differential termination at the input differential receiver terminals (see Module 3 for specific ranges). On-chip input differential termination in spartan-3e devices eliminates the external 100Ω termination resistors commonly found in differential receiver circuits. Use differential termination for LVDs, mini-LVDs, and BLVDS when the application allows.
On-chip differential termination is available in groups with VCCO=2.5V, not supported by dedicated input pins. Set the diff_term property to true to enable differential termination on differential I/O pin pairs.
The diff_term attribute uses the following syntax in ucf files: inst diff_term=" "; Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors within each IOB can optionally force floating I/O pins into defined states.

Pull-down resistors are typically used for unused I/Os, inputs, and tri-state outputs, but can be used for any I/O. A pull-down resistor connects the I/O to VCCO through a resistor. Resistor value depends on VCCO voltage (see Module 3 for specifications). Pull-down resistors similarly tie the I/O to the resistor ground. The pullup and pulldown properties and library primitives turn on these optional resistors.
By default, pull-down resistors terminate all unused I/Os. Unused I/O can also be set to pullup or float. To change unused I/O pad settings, set the Bitstream Generator (BitGen) option unusedPin to pullup, pulldown, or float. The unusedpin option is accessible through the properties of the generated programming file in ISE.
During configuration, a low logic level on HSWAP activates the pull-up resistors for all I/Os that are not directly used in the selected configuration mode.
Holdover Circuit Each I/O has an optional holdover circuit that keeps the bus from floating when the bus is not actively being driven. The keeper circuit holds the last logic level on the line after all drivers are turned off. Apply the keeper property or use the keeper library primitives to use the keeper circuit. Pull-up and pull-down resistors override the keeper settings.
Slew Rate Control and Drive Strength Each IOB has a slew rate control that sets the output switching edge rate for the lvcmos and lvttl outputs. The Rotation property controls the rotation rate and can be set to Slow (default) or Fast.
Each LVCMOS and LVTTL output additionally supports up to 6 different drive current strengths To adjust the drive strength for each output, set the Drive property to the desired drive strength: 2, 4, 6, 8, 12 and 16.
High output current drive strength and fast output slew rates typically result in the fastest I/O performance. However, these same setups often also have transmission line effects on printed circuit boards (PCBs), except for the shortest ones. Each IOB has independent slew rate and drive strength controls. Use the lowest slew rate and lowest output drive current that meets the performance requirements of the end application.
Also, a given package supports a limited number of simultaneous switching outputs (SSOs) when using fast, high drive outputs due to lead inductance. Use fast, high drive outputs only when your application requires it.
IOUs organized into banks
The Spartan-3E architecture organizes the IOBs into four I/O groups, each with independent VCCO and VREF supplies. Separate power supplies allow each bank to set the VCCO independently. Similarly, vref feeds can be set for each bank. See Table 3 and Table 4 for VCCO and VREF requirements. When using Spartan-3E devices, most differential I/O standards are compatible and can be combined within any given group. Each bank can support any two of the following variance standards: lvds_25 output, mini_lvds_25 output, and rsds_25 output. For example, lvds_25 output, rsds_25 output, and any other differential input are valid combinations when using on-chip differential termination. A disallowed combination is a single rank with lvds-25 output, rsds-25 output, and mini-lvds-25 output.

I/O Bank Rules These VCCO rules must be followed when allocating I/O to banks: 1. All vcco pins on the fpga must be connected even if the bank is not used. 2. All relevant VCCO lines within a group must be set to the same voltage level. three. The VCCO level used by all standards assigned to any given bank's I/O must be consistent. The xilinx development software checks for this. Tables 3 and 4 describe how different standards use VCCO provisioning. Four. If the bank doesn't have any VCCO requirements, connect the VCCO to an available voltage like 2.5V or 3.3V. Certain configuration modes may place additional requirements on VCCO.
If any standard assigned to a bank input uses VREF, the following additional rules must be followed: 1. All VREF pins must be connected within a group. 2. All VREF lines associated with the cylinder bank must be set to the same voltage level. three. The VREF level used by all criteria assigned to the bank input must be consistent. The xilinx development software checks for this. Table 3 describes how the different standards use the VREF supply. If vrefs are not required to bias input switching thresholds, all relevant vref pins within the group can be used as user i/o or input pins.
Package Form Factor Compatibility Occasionally, applications will exceed the logic capacity of a particular SPARTAN-3E FPGA. Fortunately, the Spartan-3e family is designed so that multiple part types are available in pin-compatible package outlines, as described in Module 4. In some cases, there are subtle differences between devices available in the same memory. These differences are outlined for each package, such as pins not connected to one device but connected to another in the same package, or pins that are dedicated inputs on one package but full I/O on another foot. When designing printed circuit boards (PCBs), plan for possible future upgrades and package migrations.
The Spartan 3e series is not compatible with any previous Xilinx FPGA series.
Dedicated Inputs Dedicated inputs are iobs that are used only as inputs. If the name starts with IP (eg IP or IP_Lxxx_X), the pin name specifies a dedicated input. The dedicated inputs retain the full functionality of the IOB for the input function, except for the difference inputs (IP_Lxxx_X). For differential dedicated inputs, on-chip differential termination is not available. To replace the differential termination on the chip, choose a differential pair that supports the outputs (IO_lxxx_x), or use an external 100Ω termination resistor on the board.
ESD protection clamp diodes protect all device pads from electrostatic discharge (ESD) and excessive voltage transients. Each i/o has two clamping diodes: one diode extends p-to-n from pad to vcco and the other diode extends n-to-p from pad to gnd. During operation, these diodes are usually biased in the off state. These clamp diodes are always connected to the pads, regardless of the signal standard chosen. The presence of diodes limits the Spartan 3e i/o's ability to withstand high signal voltages. The VIN absolute maximum ratings in Table 1 for Module 3 specify the voltage range that the I/OS can tolerate.
IOB supply voltage
The IOB is powered by three power sources: 1. The vcco provides a power supply for each FPGA's I/O library to power the output drivers. The voltage on the VCCO pin determines the voltage swing of the output signal. 2. Vccint is the main power supply for the internal logic of fpga. three. VCUAX is an auxiliary power supply, mainly to optimize the performance of various FPGA functions such as I/O conversion.
I/Os During Power-Up, Configuration, and User Mode All I/Os have ESD clamping diodes connected to their respective VCCO supplies and GND, VCCINT (1.2V), VCCAUX (2.5V), and VCCO supplies can be used in any order . Before the FPGA begins its configuration process, vccint, vcco bank 2, and vccaux must have reached their respective recommended minimum operating requirements Levels (see table 2 of module 3). At this point, all I/O drivers are in a high impedance state. VCCO Bank 2, VCCINT, and VCCAU Serve as Inputs to the Internal Power-on Reset C A low level applied to the USER I/OS on the HSWAP input through the configured PUL resistor. A high level removable zip resistor on HSWAP that allows i/bone to float. HSWAP contains a soft sweater, high defect if left floating. When power is applied, the FPGA begins to initialize its configuration memory. At the same time, FPGA Internally asserts the global set-reset ("GSR"), which asynchronously resets all IOB storage elements to a default low state.
After initialization is complete and configuration is initialized, start going high, sampling the M0, M1, and M2 inputs to determine the configuration mode. At this point, the configuration data is loaded into the FPGA. The I/O driver goes through the configuration in a high impedance state (with or without a pulse resistor, as determined by the HSWAP input).
At the end of the configuration, the GSR Net is released, placing the IOB register in a low state, unless the load is designed to reverse its respective input polarity. Global Three-State (GTS) Net (GTS) Net (GTS) Net) is in Released at startup, marking the end of configuration and the beginning of design operation in user mode. After GTS Net was released, all users/OS were active, and all unused I//OS were vulnerable downloads ("Pulldown"). Designers can control I/O that is not used after GTS
One clock cycle delay ("Default"), Global Word Enable (GWE) Net is released, RAM and RAs can change state. Once in use mode, any pull-up resistors that HSWAP repeatedly generates can be used as a common setup and HSWAP, I//O. For more information on Pull-up and Pull-down, see Pull-up and Pull-down Resistors device.

Configurable Logic Blocks (CLBs) and slice resources
CLB Overview A Configurable Logic Block (clb) is the primary logic resource for implementing synchronous and combinational circuits. Each CLB contains four slices, each slice containing two look-up tables (LUTs) used to implement logic and two dedicated storage elements that can be used as flip-flops or latches. luts can be used as 16x1 memory (ram16) or as a 16-bit shift register (srl16).
Additional multiplexers and carry logic simplify extensive logic and arithmetic functions. Most of the common logic in the design is automatically mapped to sliced resources in the CLB. Each CLB is identical, and the CLB structure of the Spartan-3E family is identical to that of the Spartan-3 family.
CLB array
The CLBs are arranged in regular arrays of rows and columns. Each density varies with the number of rows and columns of the CLB. Each CLB contains four interconnected slices. These slices are grouped in pairs. Each pair is organized into a column with an independent carry chain. The left pair supports both logical and memory functions, and its slices are called slices. The pair on the right only supports logic, and its slices are called slices. therefore
lut supports both logic and memory (including ram16 and srl16 shift registers), while half supports logic only, the two types alternate in array columns. slicel reduces the size of the clb, reduces the cost of the device, and can also provide higher performance benefits than slicem.

Slice position specification
The xilinx development software specifies the position of the slice based on its x and y coordinates, starting from the lower left corner, as shown in Figure 11. The letter "x" followed by a number indicates the column of slices that increment from the left side of the die to the right side. The letter "Y" followed by a number indicates the position of each slice in a pair and indicates the CLB row, increasing from the bottom of the die. The CLB in the lower left corner of the mold. slicem always has an even 'x' number, slicel always has an odd 'x' number.
Slicing overview A slice consists of two lut function generators and two storage elements, plus additional logic
Both slicem and slicel have the following elements in common to provide logical, arithmetic and rom functionality:
• Two 4-input lut function generators, f and g • Two storage elements • Two wide function multiplexers, f5mux and fimux • Carry and arithmetic logic

Slice pairs support two additional features:
• Two 16x1 distributed RAM blocks, RAM16 • Two 16-bit shift registers, SRL16
The following sections describe each of these elements in more detail.
logical unit
The combination of lut and storage unit is called "logical unit". Additional functions in the slice, such as wide multiplexers, carry logic, and arithmetic gates, increase the capacity of the slice and implement logic that would otherwise require additional LUts. Benchmarks show that the entire slice is equivalent to 2.25 simple logic cells.
Slice Details It represents the superset of elements and connections to be found in all slices. The dashed and gray lines (blue when viewed in color) represent assets that are only found in slices, not slices.
Each slice has two parts which are differentiated as top and bottom to keep them distinct from the upper and lower slices in CLB. Control input for clock (CLK)
ENABLE (CE), SLICE WRITE ENABLE (SLICEWE1) and RESET/SET (RS) are shared between the two parts.
The luts at the top and bottom of the slice are called "g" and "f", or "g-lut" and "f-lut," respectively. The storage elements at the top and bottom of the slice are called ffy and ffx, respectively.
Each slice has two muxes, f5mux on the bottom of the slice and fimux on the top. Depending on the slice, fimux takes the name f6mux, f7mux, or f8mux depending on its position in the multiplexer chain. There is an F6Mux for both the lower slice and the slice. The slice above has an f7mux and the slice above has an f8mux.
The carry chain goes into the bottom of the slice as CIN and exits as CUT at the top. Five multiplexer control chains: cyinit, cy0f, and cymuxf at the bottom, and cy0g and cymuxg at the top. Dedicated arithmetic logic includes XOR gates xorf and xorg (bottom and top of the slice, respectively) and AND gates fand and gand (bottom and top, respectively).

Main Logical Path At the center of each slice operation are two nearly identical data paths at the top and bottom of the slice. The description below uses the name associated with the bottom path. (The top path name appears in parentheses.) The base path originates from the interconnect switch fabric outside the CLB.
Four lines, f1 to f4 (or g1 to g4 on the path above), go into the slice and connect directly to the lut. Once in the slice, the lower 4 bits path through the lut "f" (or "g") which performs a logical operation. The lut data output "d" provides five possible paths:
one. Exit the slice and return to the interconnect via line "X" (or "Y").
2. Inside the slice, "x" (or "y") is used as an input to dxmux (or dymux), which provides data for the data input "d" of the ffy (or ffx) storage element. The "Q" output of the memory cell drives the line XQ (or YQ) that exits the strip.
three. Controls the cymuxf (or cymuxg) multiplexer on the carry chain.
Four. For carry chains, used as input to an xorf (or xorg) XOR gate that performs an arithmetic operation, producing a result on "x" (or "y").
5. Drives the multiplexer f5mux to implement logic functions with more than 4 bits. Both the "d" outputs of the f-lut and g-lut are used as the data input for this multiplexer.
In addition to the main logic paths described above, there are two bypass paths into the slice as bx and by. Once in the fpga, the bx can accept any of several possible branches in the lower half of the slice (or (in the upper half):
one. Bypass the LUT and storage element, then exit the BXOUT (or BYOUT), and return to the interconnect.
2. Bypass the LUT, then pass the storage element through the D input before exiting with XQ (or YQ).
three. Controls the wide function multiplexer F5MUX (or FIMUX).
Four. Through the multiplexer, as the input to the carry chain.
5. The di input that drives the lut.
6.by can control the rev input of ffy and ffx storage units. See Store Element Functions.
Number 7. Finally, the DigiMUX multiplexer can switch to the mining line, exiting the slice.
Control inputs CLK, CE, SR, BX and BY have programmable polarities. Programmable polarity is not required for the lut inputs, as their function can be reversed within the lut.
The following sections provide more details on the individual functions of slicing.
Lookup Tables Lookup tables or LUTs are RAM-based function generators and are the primary resource for implementing logic functions. Additionally, as described later, the LUTs in each slice pair can be configured as distributed RAM or 16-bit shift registers.
Both luts (f and g) in the slice have four logic inputs (a1-a4) and one output (d). Any four-variable Boolean logic operation can be implemented in a lut. Functions with more inputs can be implemented by cascad
CLK SLICEL/M common input FFX/Y clock or RAM clock (SLICEM)
Input data to G-LUT RAM shift slice top input shifter slicer bottom output shift data output from f-lut ram
CIN Slice L/M Bottom Input Carry Chain Input
cout slice l/m top output carry chain output
X slice L/M bottom output combined output
Y slice L/M top output combined output
XB slice L/M bottom output carry or F-LUT SRL16 combined output (slice)
YB slice L/M carry or top output combined output of G-LUT SRL16 (slice M)
xq slice l/m bottom output ffx output
YQ slice L/M top output FFY output Table 7: Slice input and output (continued)
Name Location Direction Description Function Description Right Use lut or use the wide function multiplexer described later.
The output of the lut can be connected to wide multiplexer logic, carry and arithmetic logic, or directly to the clb output or the clb memory cell.
Wide Multiplexers Wide function multiplexers effectively combine LUTs to allow more complex logic operations. Each slice has two of these multiplexers, f5mux on the bottom of the slice and fimux on the top. f5mux multiplexes two luts in one slice. fimux multiplexes two clb inputs which are connected directly to f5mux, fimux result comes from the same slice or another slice.

Depending on the slice, fimux is named f6mux, f7mux, or f8mux. The name indicates the number of possible inputs without limiting functionality. For example, f7mux can generate any function with seven inputs.
Each mux can create logic functions with more inputs than its name indicates.
ATE any function of the five inputs, four inputs are copied to two LUTs, and the fifth input controls the MUX. Because each lut can implement an independent 2:1 mux, f5mux can combine them to create a 4:1 mux, which is a 6-input function. Some functionality of all nine inputs can be achieved if the two luts have completely independent sets of inputs. Table 8 shows the connections for each multiplexer and the number of possible inputs for different types of functions.

Dedicated Multipliers SPARTAN-3E devices provide from 4 to 36 dedicated multiplier blocks per device. The multipliers are in one or two columns along with the block ram, depending on the device density. See Arrangement of RAM Blocks on the Die for details on the location of these blocks and their connectivity.
The multiplier block mainly performs 2's complement digital multiplication, but can also perform some less obvious applications like simple data storage and bucket shifting. The logic slice also implements efficient small multipliers that complement the dedicated multipliers. The SPARTAN-3E dedicated multiplier block has additional functionality provided by SPARTAN-3 FPGAs.
Each multiplier performs the main operation p=a×b, where "a" and "b" are 18-bit words in two's complement form, and "p" is the full exact 36-bit product, also in two's complement form . The 18-bit input represents values from -13107210 to +13107110 and the resulting product ranges from -1717973811210 to +1717986918410.
Multipliers with inputs smaller than 18 bits are implemented by sign extending the input (that is, copying the most significant bit). Wider multiplication operations are performed by combining dedicated multipliers and slice-based logic into any feasible combination, or by time-sharing a single multiplier. Unsigned multiplication is performed by limiting the input to the positive range. Bind the most significant bit low and represent the unsigned value in the remaining 17 less significant bits.
As shown in Figure 33, each multiplier block has optional registers on each multiplier input and output. The registers are named areg, breg, and preg and can be used in any combination. The clock input is common to all registers in a block, but each register has independent clock enable and synchronous reset controls, making them ideal for storing data samples and coefficients. When used in pipelines, the registers increase the clock rate of the multiplier, which is beneficial for higher performance applications.
Use the mult18x18sio primitives shown in Figure 34 to instantiate the multiplier in the design. Although high-level logic synthesis software usually infers a multiplier automatically, adding pipeline registers usually requires mult18x18sio primitives. Connect the appropriate signal to the mult18x18sio multiplier port and set the individual areg, breg, and preg properties to '1' to insert the relevant register, or 0 to remove it and combine the signal paths.

Digital Clock Manager (DCMS)
Differences from Spartan-3 Architecture • Spartan-3E FPGAs have two, four or eight DCMs, depending on device size. The maximum phase shift range of the SSPANT-3E DCM is ±180°. The DCM range of the Spartan-3 is ±360°. • The SPARTAN-3E dynamic link library supports lower input frequencies, down to 5 MHz. The Spartan-3 DLL supports down to 24 MHz.
Overview
The SPARTAN-3E Digital Clock Manager (DCMS) provides flexible, complete control over clock frequency, phase shift and skew. To achieve this, DCM employs a Delay Locked Loop (DLL), an all-digital control system that uses feedback to maintain the high-precision characteristics of the clock signal despite normal variations in operating temperature and voltage. This section provides a basic description of DCM. For more information, see xapp462: "Using Digital Clock Managers (DCMs) in Spartan-3 Family FPGAs".
The FPGA of the xc3s100e has two dcms, one on the top of the device and one on the bottom of the device. The xc3s250e and xc3s500e FPGAs each include four dcms, two on the top and two on the bottom. The xc3s1200e and xc3s160e FPGAs contain eight dcms, two per edge (see also Figure 42). DCMs in spartan-3e FPGAs are surrounded by clbs in the logic array and are no longer at the top and bottom of the block ram column as in the spartan-3 architecture. The digital clock manager is instantiated as a design as a "dcm" primitive.
DCM supports three main functions:
• Clock Skew Elimination: Clock skew describes the extent to which a clock signal deviates from zero phase alignment under normal conditions. This happens when small differences in path delay cause the clock signal to arrive at different points on the die at different times. This clock skew increases setup and hold time requirements and clock-to-output time, which may not be needed in applications operating at high frequencies where timing is critical. The DCM removes clock skew by aligning the output clock signal it produces with another version of the clock signal that is fed back. As a result, the two clock signals establish a zero-phase relationship. This effectively eliminates output clock distribution delays that may be in the signal path from the dcm's clock output to its feedback input. • Frequency Synthesis: The DCM has an input signal that can generate many different output clock frequencies. This can be accomplished by multiplying and/or dividing the frequency of the input clock signal by any of several different factors. • Phase Shift: A DCM provides the ability to shift the phase of all its output clock signals relative to its input clock signal. dcm has four functional parts: delay locked loop (dll), digital frequency synthesizer (dfs), phase shifter (ps) and state logic dll clock input connects external clock source uses global clock input buffer (ibufg) into fpga, This buffer accesses the global clock network directly or through an input buffer (ibuf). The clock signals in the fpga use a global clock multiplexer buffer (bufgmux) to drive the global clock net. The global clock network is connected directly to the clkin input. Internal and external connections are shown in Figure 39a and Figure 39c, respectively. Differential clocks (eg lvds) can be used as inputs to clkin.
dll clock outputs and feedback connections Up to four of the nine DCM clock outputs can simultaneously drive four BUFGMUX buffers on the same die edge. All DCM clock outputs can simultaneously drive common routing resources, including interconnects to OBUF buffers.
The feedback loop, which is critical to dynamic link library operation, is established by driving the clkfb input with the clk0 or clk2x signal in order to include any undesired clock distribution delays in the loop. The seven DLL outputs can be synchronized using either of these two signals: clk0, clk90, clk180, clk270, clkdv, clk2x, or clk2x180. The value assigned to the clk_feedback property must match the physical feedback connection: 1x for clk0 and 2x for clk2x. If the dcm is used in an application that doesn't require the dll (i.e. only the dfs is used), the feedback loop is not needed, so clk_feedback is set to none.
There are two basic cases for deciding how to connect the dll clock output and feedback connections: on-chip synchronization and off-chip synchronization

The bufgmux pair is connected to four of the eight global clock inputs, which allows differential input to the global clock inputs without wasting bufgmux elements.
The connection of the lower edge bufgmux element is similar to the connection of the upper edge.
On the left and right edges, only two clock inputs power each pair of bufgmux elements.

Quadrant Clock Routing
Clock routing within the FPGA is quadrant-based, with each clock quadrant supporting 8 total clock signals, labeled "A" through "H" in Table 36 and Figure 44. A single clock line is clocked either from the global bufgmux element along the upper and lower edges or from the bufgmux element along the associated edge, and the clock line powers the synchronous resource elements (CLB, IOB, block RAM, multiplier, and DCM) within the quadrant.
The four quadrants of the device are: • Top Right (TR) • Bottom Right (BR) • Bottom Left (BL) • Top Left (TL) Note that the quadrant clock notation (tr, br, bl, tl) is the same as the one used for iob-like placement constraints Symbols are separated.

Configuration Differences from Spartan-3 Gas Turbines In general, the SPARTAN-3E FPGA configuration modes are a superset of the configuration modes available in SPARTAN-3 FPGAs. Two new modes have been added to SPARTAN-3E FPGAs that provide glueless configuration interfaces for industry-standard parallel NOR flash and SPI serial flash. Unlike Spartan-3FPGas, almost all Spartan-3E configuration pins can be used as user I/O after configuration.
configuration process
The functionality of the Spartan-3E FPGA is defined by loading application-specific configuration data into the FPGA's internal reprogrammable CMOS configuration latches (ccls), similar to the functionality of a microprocessor defined by its application Way. For FPGAs, this configuration process uses a subset of device pins, some of which are dedicated to configuration; others are only used to borrow and return to the application as general-purpose user I/O after configuration is complete.
Spartan-3E FPGAs offer a variety of configuration options to minimize the impact of configuration on the overall system design. In some configuration modes, the FPGA generates the clock and loads itself from an external memory source (serial or via a byte-wide datapath). Alternatively, an external host (such as a microprocessor) downloads the FPGA's configuration data using a simple synchronous serial interface or via a byte-wide peripheral-style interface. Additionally, multiple FPGA designs share a configuration memory source, creating a structure known as a daisy chain.
Three fpga pins m2, m1 and m0 select the desired configuration mode. The mode pin settings are shown in Table 38. The mode pin value is sampled at the start of configuration when the FPGA's init_b output goes high. After the FPGA is configured, the mode pins can be used as user I/O.

Master Serial Mode In master serial mode (M[2:0]=<0:0:0>), the Spartan-3E FPGA configures itself from the attached Xilinx platform flash PROM, the FPGA clocks the cclk output from its The internal oscillator is provided to the additional flash prom platform. In response, the platform flash prom provides bit-serial data to the FPGA's DIN input, and the FPGA receives this data on each rising cclk edge.

If the application requires multiple FPGAs with different configurations, use a daisy-chain configuration of the FPGAs, using master serial mode (M[2:0]=<0:0:0>) for the FPGA connected to the platform flash PROM, Will be used from serial mode (M[2:0]=<1:1:1>) to all other FPGAs in the daisy chain. After the master FPGA on the left in the figure finishes loading its configuration data from the platform flash, the master device uses its DOUT output pins to provide data to the next device in the daisy chain on the falling cclk edge.
JTAG interface
Both the spartan-3e fpga and the platform flash prom have a four-wire IEEE 1149.1/1532jtag port. Both devices share the tck clock input and the tms mode select input. These devices can be connected in any order on the jtag chain, with the TDO output of one device feeding the TDI input of the following devices in the chain. The TDO output of the last device in the JTAG chain drives the JTAG connector.
The jtag interface on the spartan-3e fpgas is powered by a 2.5vccaux supply. Therefore, the vccj power input of the prom must also be 2.5v. To create a 3.3v jtag interface, see application note xapp453: "3.3v configuration for spartan-3 fpgas" for more information.
In-system programming support
Both the fpga and the platform flash prom are programmed in the system through the jtag chain. Download support is provided by the xilinx impact programming software and the associated xilinx parallel cable iv, multipro or platform cable usb programming cable.
After additional user data configuration is stored in the platform flash, the FPGA application can continue to communicate with the platform flash prom using the main serial interface pins. If needed, use a larger platform flash prom to hold additional non-volatile application data such as microblaze processor code, or other user data such as serial numbers and ethernet mac ids. The fpga is first configured from the platform flash prom. Then use the configured fpga logic to copy the micro-block code in the platform flash to the external ddr sdram for code execution.
"Reading user data from configuration proms" and xapp482: "Microblaze platform flash/prom bootloader and user data storage" for specifics on how to implement such an interface.
Serial Flash Mode In SPI serial flash mode (M[2:0]=<0:0:0>), the Spartan-3E field programmable gate array configures itself according to the attached industry standard SPI serial flash PROM. The fpga supplies the cclk output clock from its internal oscillator to the clock input of the attached spi flash prom.

The spi flash prom density requires the smallest available SPI flash PROM to program a single SPARTAN-3E field programmable gate array. Commercial SPI Flash Prom densities range from 1 Mbit to 128 Mbit. Multiple FPGA daisy chain applications require a SPI flash prom large enough to contain the sum of the FPGA file sizes. Applications can also use the higher density spi flash prom to hold data other than FPGA configuration data. For example, the spi flash prom can also store application code for the microblaze™ risc processor core integrated in the spartan-3e FPGA. See Using the SPI Flash Interface After Configuration.
CCLK frequency In spi flash mode, the FPGA's internal oscillator generates the configuration clock frequency. The fpga provides this clock on its cclk output pin, which drives the prom's clock input pin. If specified in the configuration bitstream, the FPGA starts configuration at its lowest frequency and increases its frequency for the rest of the configuration process. Specify the maximum frequency using the configure bitstream generator option. The maximum frequency supported by the FPGA configuration logic depends on tim.
For SPI flash devices. Without checking the timing of a particular SPI flash PROM, use config rate=12, which is approximately 12 MHz. The spi flash prom that supports fast read commands supports higher data rates. Some of these proms support up to configrate=25 or higher, but require careful datasheet analysis.
Using the spi flash interface after configuration After the FPGA has successfully completed configuration, all pins connected to the spi flash prom are available as user I/O pins.
If the SPI flash PROM is not used after configuration, turn the CSO UB drive high to disable the PROM. Then the mosi, din and cclk pins are available for FPGA applications.
Since all interface pins are user I/O after configuration, the FPGA application can continue to use the SPI flash interface pins to communicate with the SPI flash PROM, the spiflashprom provides random access, byte addressing, read/write for FPGA applications , non-volatile storage.
Available densities for spi flash prom vary from 1 mbit to 128 mbit. However, a spartan-3e FPGA needs to be less than 6mbits. If desired, a larger spi flash prom can be used to contain additional non-volatile application data such as microblaze processor code, or other user data such as serial numbers and ethernet mac ids. The fpga is configured from the spi flash prom. Then use the configured fpga logic to copy the micro-block code in the spi flash memory to the external ddr sdram for code execution. Similarly, FPGA applications can store non-volatile application data in the SPI flash prom.
FPGA configuration data is stored starting at position 0. Stores any additional data starting from the next available SPI Flash PROM sector or page. Do not mix configuration data and user data in the same sector or page.

In-system programming support In production applications, spi flash proms are usually pre-programmed before being mounted on a printed circuit board. Some third-party prom programmers provide in-system programming support using socket adapters with connecting wires. To gain access to the SPI flash signals, drive the FPGA's prog_b input low using an open-drain driver. This action places all FPGA I/O pins (including those connected to the SPI flash) into high impedance (Hi-Z). If the hswap input is high, the i/o has a pull-up resistor to the vcco input on its respective i/o bank. Then, external programming hardware can directly access the spi flash pins. In byte-wide peripheral interface (BPI) mode (M[2:0]=<0:1:0> or <0:1:1>), Spartan- The 3E FPGA configures itself from an industry standard parallel or flash PROM, as shown in Figure 55. Field Programmable Gate Arrays generate parallel flash memory connected to 24-bit address rows to access the connected. Only 20 address lines are generated in the TQ144 package for Spartan-3E FPGAs. BPI mode is not available for Spartan-3E FPGAs in VQ100 assemblies.
The interface is designed for standard parallel or flash proms, supporting byte-wide (x8) and byte-wide/halfword (x8/x16) proms. The interface does not support halfword (x16) proms. This interface works equally well with other memories that use a similar interface (such as sram, nvram, eeprom, eprom, or shield rom), but is primarily designed for flash.
There is another type of flash memory called nand flash, which is commonly used in memory cards such as digital cameras. spartan-3e fpgas is not configured directly from nand flash memory.
The internal oscillator of the fpga controls the interface timing, and the fpga provides the clock on the cclk output pin. However, the cclk signal is not used in a single fpga application. Similarly, during configuration, the fpga drives the control input of the prom by three pins low (ldc[2:0]) and one pin high (hdc).

In-system programming support In production applications, parallel flash proms are often pre-programmed before being mounted on a printed circuit board. In-system programming support is available from 3rd party boundary scan tool vendors and some 3rd party PROM programmers using socket adapters with connecting wires. To gain access to parallel flash signals, drive the FPGA's prog_b input low with an open-drain driver. This action places all FPGA I/O pins (including those connected to parallel flash) into high impedance (Hi-Z). If the hswap input is high, the i/o has a pull-up resistor to the vcco input on its respective i/o bank. External programming hardware can then directly access the parallel flash pins.
The fpga itself can also be used as a parallel flash prom programmer during development and testing. Initially, a programmer based on fpga downloaded to fpga through jtag. Then, the fpga executes the flash prom programming algorithm, and receives programming data from the host through the fpga's jtag interface.
Using the multiboot option to dynamically load multiple configuration images After the fpga has configured itself using bpi mode from one side of the parallel flash prom, the fpga can trigger a multiboot event and reconfigure itself from the other side of the parallel flash prom. multiboot is only available when using bpi mode and only for applications using a single spartan-3e fpga.
By default, multiboot mode is disabled. To trigger a multiboot event, assert a low pulse for at least 300 ns on the MultiBoot Trigger (MBT) input to the STARTUPSP-SARTAN3E library primitive. On power up, the fpga loads itself from the connected parallel flash prom. In this example, the M0 mode pin is low, so the FPGA starts at address 0 and increments through the flash prom memory location. After the FPGA is configured, the application loaded into the FPGA uses the FPGA logic to perform board-level or system testing. If the test is successful, the FPGA triggers a multiboot event that causes the FPGA to reconfigure from the other side of the flash prom memory. The second configuration contains the fpga application for normal operation.

The external download host starts the configuration process by pulsing prog_b and monitoring if the init_b pin goes high, which indicates that the fpga is ready to receive its first data. The host asserts the active low chip select signal (csi_b) and the active low write signal (rdwr_b). Then, the host continues to provide data and clock signals until the done pin of the fpga goes high, indicating a successful configuration, or until the init_b pin of the fpga goes low, indicating a configuration error.
The fpga captures data on the rising cclk edge. If the cclk frequency exceeds 50mhz, then the host must also monitor the busy output of the fpga. If the fpga asserts busy high, the host must hold the data for an additional clock cycle until busy returns low. If the cclk frequency is 50 MHz or less, busy pins may be ignored but actively driven during configuration.
The configuration process requires more clock cycles than the configuration file size indicates. Additional clocks are required in the boot sequence of the FPGA, especially when the FPGA is programmed to wait for the selected digital clock manager (DCM) to lock to their respective clock inputs.
If the slave parallel interface is only used to configure the fpga and not to read back data, the rdwr_b signal can also be eliminated from the interface. However, rdwr_b must be kept low during configuration.

Slave Serial Mode In slave serial mode (m[2:0]=<1:1:1>), an external host (such as a microprocessor or microcontroller) synchronously serial interface writes serial configuration data fpga. Serial configuration data is displayed on the FPGA's DIN input pins with sufficient setup time before each rising edge of the externally generated CClk clock input.
The smart host starts the configuration process by pulsing prog_b and monitoring the init_b pin to go high,
Indicates that the fpga is ready to receive its first data. The host then continues to provide data and clock signals until the done pin goes high to indicate a successful configuration, or until the init_b pin goes low to indicate a configuration error. The configuration process requires more clock cycles than the configuration file size indicates. Additional clocks are required in the boot sequence of the FPGA, especially when the FPGA is programmed to wait for the selected digital clock manager (dcm) to lock to their respective clock inputs

The mode select pins m[2:0] are sampled when the FPGA's init_b output goes high and must be at a defined logic level during this time. Once configured, the mode pins can be used as full-featured user I/O pins when the FPGA's done output goes high.
Similarly, the FPGA's Hswap pin must be low to enable pull-up resistors on all user I/O pins, or high to disable pull-up resistors. The hswap control must maintain a constant logic level throughout the FPGA configuration process. Once configured, when the FPGA's done output goes high, the hswap pin can be used as a full-featured user i/o pin and is powered by the vcco_0 supply.

JTAG mode
The Spartan-3e FPGA has a dedicated 4-wire IEEE 1149.1/1532JTAG port, which is always available as long as the FPGA is powered, regardless of the mode pin settings. However, when the fpga mode pins are set to jtag mode (m[2:0]=<1:0:1>), the fpga waits for configuration through the jtag port after a power-on event or when prog_b is asserted. Selecting jtag mode simply disables other configuration modes. No other pins are required for the configuration interface.
The jtag interface is easily cascaded to any number of FPGAs by connecting the TDO output of one device to the TDI input of the next device in the chain. The tdo output of the last device in the chain loops back to the port connector.

Voltage Compatibility
The 2.5V VCCAUX supply powers the JTAG interface. All user I/Os are individually powered by their own VCCO power supplies.
When connecting the SPARTAN-3E JTAG port to a 3.3V interface, the JTAG input pins must use series resistors to limit current to 10mA or less. Similarly, the TDO pin is a CMOS output with +2.5v power. The tdo output can drive the 3.3v input directly, but with reduced noise immunity. For more information, see application note xapp453: "3.3v Configuration for Spartan-3 FPGAs".
Maximum bitstream size for daisy chains
The maximum bit stream length supported by the SASTAN-3E FPGA in a serial daisy chain is 4294967264 bits (4 bits), which is roughly equivalent to a daisy chain with 720×C3S1600 E FPGAs. This is just a limitation of serial daisy chaining, where configuration data is passed through the dout pins of the fpga. The JTAG chain has no such restriction.
configuration sequence
The spartan-3e configuration process is a three-phase process (por event) that begins after the FPGA is powered up
Or after program input has been asserted. A power-on reset (POR) occurs after the VCCINT, VCCAUX, and VCCO Bank 2 supplies reach their respective input threshold levels. After a por or prog_b event,
The three-phase configuration process begins.
one. The fpga clears (initializes) the internal configuration memory.
2. The configuration data is loaded into memory.
three. User applications are activated by the startup process.
Generic block diagram of spartan-3e configuration logic, showing the interaction of different device inputs and bitstream generator (bitgen) options.
Initialization Configuration starts automatically after power-up or assertion of the FPGA prog-b pin unless delayed using the FPGA's init-b pin. The FPGA keeps the open-drain init_b signal low when the internal configuration memory is cleared. Holding the init_b pin low externally will force the configuration sequencer to wait until init_b goes high again.

DC Characteristics In this section, specifications can be specified as pre, preliminary, or production. These terms are defined as follows:
Progress: Preliminary estimates are based on simulations, early characterization, and/or extrapolation from features from other families. Values may change at any time. For estimation, not for production.
Preliminary: Based on features. No further changes are expected.
Production: These specifications are approved once the silicon has been characterized on multiple production batches. Parameter values are considered stable and have no future changes.
All parameter limits represent worst-case supply voltage and junction temperature conditions. The following applies unless otherwise stated: The parameter values published in this module apply to all Spartan-3e devices. For commercial and industrial grades, AC and DC characteristics are specified using the same numbers.
If a particular Spartan-3e FPGA differs in functional or electrical characteristics from this datasheet, those differences will be described in a separate errata file.

Switching Characteristics All Spartan-3e FPGA boats have two speed grades: –4 and higher performance –5. As shown in Table 11, the switching characteristics in this document can be specified as advance, preliminary, or production. Each category is defined as follows:
Ahead: These specs are based on simulation only and are usually available soon after the FPGA specs are established. While the speed ratings under this designation are considered relatively stable and conservative, some underreporting is still possible.
Preliminary: These specifications are based on early complete silicon characterization. Devices and speed grades with this designation are intended to better indicate the expected performance of production silicon. Pre-reported delays are significantly less likely than pre-reported data.
Production: These specifications are approved once sufficient silicon is produced for a particular device family member to provide full correlation between speed files and devices across multiple production batches. There is no under-reporting of delays and the client receives formal notification of any subsequent changes. Usually, the slowest speed grade transitions to production before the faster speed grade.
A production quality system must use an FPGA design compiled with a speed file specified as production status. FPGA designs using less established speed file names should only be used during system prototyping or pre-production qualification. In production quality systems, FPGA designs with speed files designated as preview, advanced or preliminary should not be used.
Whenever the speed file name changes, Xilinx recommends re-running the Xilinx ISE software on the FPGA design as the device matures towards production state. This ensures that the FPGA design includes the latest timing information and software updates.
All specified limits represent worst-case supply voltage and junction temperature conditions. Unless otherwise stated, the following applies: Parameter values apply to all Spartan-3e devices. All parameters representing voltage are measured with respect to GND.
The following timing parameters and their representative values were chosen because they are important as general design requirements or because they represent basic device performance characteristics. The spartan-3e velocity file (v1.10) is part of the xilinx development software and is the original source code for many (but not all) values. The speed class names for these files are shown in Table 11. For more complete, accurate and worst-case data, use the values reported by the xilinx static timing analyzer (trace in the xilinx development software) and return annotations to the list of simulated nets.
Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: a delay-locked loop (DLL), a digital frequency synthesizer (DFS), and a phase shifter (PS).
Various aspects of dll operation come into play in all dcm applications. All of these applications inevitably use clkin and clkfb inputs connected to clk0 or clk2x feedback, respectively. The specifications in apply to any application that uses only dll components. When dfs and/or ps components are used with dlls, the specifications listed in the dfs and ps tables supersede the corresponding specifications in the dll table.
All DCM clock output signals exhibit a duty cycle of approximately 50%.
Period jitter and period jitter are two different ways of characterizing clock jitter. Both specifications describe the statistical variation of the mean.
Period jitter is the worst-case deviation of the average clock period of all clock periods in the sampled set of clock periods (typically from 100,000 to over 1 million samples for specification purposes). In a period jitter histogram, the average is the clock period.
Period jitter is the worst-case difference in clock periods between adjacent clock periods in a sampled set of clock periods. In the period jitter histogram, the mean is zero.

VQ100 Footprint

Note the pin 1 indicator and logo orientation in the upper left corner. Engineering samples have slightly different footprints