Features

High bandwidth:

280MHz (g u003d+1)

120MHz (g u003d+2)

#8226; Insufficient supply current: 3.9mA/CH (vs u003d+5V)

Flexible supply range:

± 1.4V to ± 5.5V dual power supply

+2.8V to+11V single power supply

input range includes single power grounding

4.91V output swing+5V power supply

] High conversion rate: 560V/μs

Low input voltage noise: 9.2nv/√Hz

tssop-14 packaging

[[

123] Application

Single power modulus number converter (ADC) input buffer

single power video line drive

CCD imaging channel

active filter

PLL points

Portable consumer electronics

Explanation

OPA4830 is a four -way, low power consumption, single power supply, broadband, voltage feedback amplifier, designed for single+3V or+5V power supply. It also supports running on ± 5V or+10V power supply. The input range is extended below the negative electrode power supply and within the 1.8V range of the positive power supply. When driving 150 complementary public emission pole output, so that the output swing is within 220 millivol to any power supply. The high output drive current (± 80mA) and the low difference gain and phase error also make the amplifier a great choice for single -power consumer video products.

The high -gain bandwidth (110MHz) and the conversion rate ensure low distortion operations (560V/μs), making OPA4830 an ideal input buffer level of 3V and 5V CMOS modulus converters (ADC). Unlike other low -power single power amplifiers, distortion performance increases with the decrease in signal swing. Low 9.2NV/√Hz Input voltage noise supports wide dynamic range operation.

OPA4830 uses industrial standards TSSOP-14 packaging.

Related Products

Typical features: vs u003d ± 5V Unless otherwise said that there are other sayingsMing (see Figure 74), otherwise TA u003d+25 ° C, G u003d+2V/V, RF u003d 750 , RL u003d 150

Typical features: vs u003d ± 5V, differential configuration

ta u003d+25 ° C, RF u003d 604 (as shown in Figure 18), RL u003d 500 unless there is another explanation.

Typical features: vs u003d+5V

Unless otherwise explained, it is in TA u003d+25 ° C, g u003d+2V/// V, RF u003d 750 to vs/2, enter VCM u003d 2.5V (see Figure 72).

Typical features: vs u003d+5V, differential configuration

[[] 123] TA u003d+25 ° C, RF u003d 604 , RL u003d 500 Differential (as shown in Figure 47), unless otherwise explained.

Typical features: vs u003d+3v

ta u003d+25 ° C, g u003d+2v/v, RL u003d 150 #8486 ; To vs/3, unless there is another explanation (see Figure 73).

Typical features: vs u003d+3V, differential configuration

ta u003d+25 ° C, RF u003d 604 , RL u003d 500 Differential (as shown in Figure 66), unless there is another explanation.

Broadband voltage feedback operation

OPA4830 , Design for single power operation (+3V to+10V). The input level supports the input voltage below the ground and within the 1.7V range of the positive power supply. The complementary agglomeration pole output level provides a ground and positive power supply within 25 millivolves. OPA4830 is compensated and can run stably under various resistance loads.

FIG. 72 shows AC coupling+2V/V gain configuration for+5V electrical characteristics and typical features. For the purpose of testing, the input impedance setting is 50 and the resistor is grounded. The voltage fluctuations in the electrical characteristics are directly collected at the input and output pins. For the circuit in Figure 72, the total effective load on the high -frequency output is 150 | | 1500 . 1.5K #8486 at the non -conversion input terminal provides a co -mode bias voltage. This parallel combination is equal to the DC resistance at the inverter input (RF), which reduces the DC output bias caused by the input bias current.

FIG. 73 shows AC coupling of+3V electrical characteristics and typical features+2V/V gain configuration. For the purpose of testing, the input impedance setting is 50 and the resistor is grounded. The voltage fluctuations in the electrical characteristics are directly collected at the input and output pins. For the circuit in FIG. 73, the total effective load on the high -frequency output is 150 | | 1500 . Non -switching to the input point 1.13k and 2.26k the resistance provides a common mode bias voltage. The parallel combination is equal to the DC resistance at the inverter input (RF), which reduces the DC output offset caused by the input bias current.

FIG. 74 shows DC coupling+2V/V gain dual -power circuit configuration as ± 5V electrical characteristics and typical characteristics. For the purpose of testing, the input impedance is used to set the input impedance to 50 , and the output impedance is set up to 150 The voltage fluctuation reported in the specification is directly measured at the input and output pin. For the circuit in FIG. 74, the total effective load is 150 1.5k Figure 74 includes two optional components. The additional resistor (348 ) is connected in series with non -swap input. Coupled with 25 DC power supply resistance back to the signal generator. And offset control part). In addition to the usual power supply container, a 0.01 μF capacitor also includes a 0.01 μF capacitor. In the actual printing circuit board layout, this optional electric container can usually increase the two harmonic distortion performance by 3 to 6 decibels.

DC level transformation

FIG Output voltage range. Given the required signal gain (G), and VOUT (ΔVout) that needs to be moved up in the center of VIN, Formula 1 and Formula 2 give the resistance value to generate the required performance. Suppose R4 is between 200 and 1.5k .

Among them

ensure that VIN and VOUT remain in the specified input and output powerWithin the range.

The circuit on the homepage is a good example of this application. When the+3V power supply is used, it is designed to obtain VIN between 0V and 0.5V and generates VOUT between 1V and 2V. The output means g u003d 2.00, ΔVout u003d 1.50V × 0.25V u003d 1.00V. Inserting these values u200bu200binto equations 1 and equation 2 (R4 u003d 750 ) are obtained: ng u003d 2.33, R1 u003d 375 , R2 u003d 2.25K , R3 u003d 563 The resistor is changed to the closest standard value of the homepage circuit.

AC coupling output video cable driver

Low -power and low -cost video cable drives usually gain a digital mode converter with a 2V/V ( DAC) output burst into the dual -end line. These interfaces usually need DC blocking capacitors. For a simple solution, the interface usually uses a very large value to block the capacitor (220 μF) to limit the tilt or depression between the frames. Figure 76 shows a method of using much lower capacitance to create a very low Qualcomm polar position. The circuit provides a voltage gain at the output pin, and Qualcomm is located at 8Hz. Considering the 150 load, a simple blocking capacitor method requires 133 μF. Using this simple curved correction circuit in FIG. 76, the two capacitors with much lower value give the same low pass pole.

The positive voltage in FIG. 76 slightly shifted from the positive input end. This configuration provides about 200mV input DC offset. When the DAC output is at the zero current at the synchronous tip part of the video signal, it is displayed at 400mv DC offset at the output pin. This offset is used to keep the output in its linear work area. Then, the circuit transmits any power noise to the output terminal, and the gain is about -20dB. Therefore, it is recommended to perform a good power supply on the power pins. FIG. 77 shows the frequency response of the circuit in Figure 76. This figure shows the 8Hz low -frequency high -pass magnetic pole and a high -end cutter of about 100MHz.

Non -mute amplifier reduced peaks

Figure 78 shows a non -conversion amplifier that can reduce the peak value at low gain. The resistor RC compensates OPA4830 to obtain higher noise gain (NG), so as to reduce the peak of AC response without changing the DC gain (usually 5dB at G u003d+1V/V, no RC). VIN must be a low -impedance source, such as operational amplifier. The resistance value is low to reduce noise. The use of RT and RF can help minimize parasitic impedance.

The noise gain can be calculated by formula 3, type 4 and type 5 calculation:

The unit gain buffer can be designed by selecting RT u003d RF u003d 20.0 and RC u003d 40.2 (Do not use RG). The noise gain of this circuit is 2V/V, so the response is similar to the characteristic diagram of G u003d+2V/V. Reduce RC to 20.0 noise gain to 3V/V, which usually gives a flat frequency response, but the bandwidth is small.

The circuit in FIG. 72 can be redesigned to reduce the peak by increasing the noise gain to 3. This increase is achieved by adding RC u003d 2.55K to achieve this increase.

Single power supply source filter

OPA4830, although working on a+3V or+5V power supply, it is very suitable for the design of high -frequency active filters. Similarly, the key additional requirement is to establish a DC working point near the point of the power supply in the highest dynamic range. Figure 79 shows the example of the 1MHz low-pass Bartvos filter using the Sallen-Key topology.

The input signal and the gain setting resistor use 0.1 μF blocking capacitors for AC coupling (the actual band response given is to set the low -frequency pole to 32kHz to display the component value). As described in Figure 72, the configuration allows two 1.87k the midpoint partial pressure formed by the resistor to appear on the input and output pin. In this case, the mid -frequency signal gain is set to +4 (12DB). In order to control the parasitic items of the input terminal, the capacitors are interested in setting up the ground. When the gain is +4, the OPA4830 on a single power supply shows a small signal and large signal bandwidth of 30MHz. In the amplifier level, the resistance value has been adjusted slightly to consider this limited bandwidth. The test of this circuit shows a precise 1MHz, -3DB point, and the maximum flat band (above the 32kHz AC coupling angle). The maximum attenuation of the amplifier is 36DB -3DB bandwidth to 30MHz.