feature

256 positions; AD5260: 1 channel; AD5262: 2 channels (independently programmable); potentiometer replacement; 20kΩ, 50kΩ, 200kΩ; low temperature coefficient: 35ppm/°C; 4-wire, SPI compatible serial Data input; 5 V to 15 V single supply; ±5.5 V dual supply operation; open midscale preset.

application

Mechanical potentiometer replacement; instrumentation: gain, offset adjustment; stereo channel audio level control; programmable voltage current conversion; programmable filter, delay, time constant; line impedance matching low resolution DAC replacement.

General Instructions

The AD5260/AD5262 provide a single- or dual-channel, 256-bit digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as potentiometers or variable resistors. Each channel of the AD5260/AD5262 contains a fixed resistor with a wiper contact that modulates the fixed resistor value at a point determined by a digital code loaded into an SPI-compatible serial input register tap. The resistance across the wiper and the fixed resistor changes linearly with the digital code and is transferred to the VR latch. The variable resistor provides a fully programmable resistance value between the A terminal and the wiper or the B terminal and the wiper. The nominal temperature coefficient of the 20Ω, 50Ω or 200Ω fixed A to B terminal resistance is 35 ppm/°C. Unlike most digital potentiometers on the market, these units can operate up to 15 V or ±5 V as long as the proper supply voltage is provided.

Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register loaded from a standard 3-wire serial-in digital interface. The AD5260 contains 8-bit serial registers, while the AD5262 contains 9-bit serial registers. Each bit is recorded to the edge of the CLK pin in the positive register. The AD5262 address bits determine the last 8 bits of the corresponding VR latch cs to load the data word during the positive side of the strobe. A serial data output pin on the other side of the serial register enables simple daisy-chaining in multiple VR applications without the need for additional external decoding logic. An optional reset pin (PR) forces the wipers to the mid-scale position by loading 0x80 into the VR latch.

The AD5260/AD5262 are available in thin surface mount 14-lead TSSOP and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended industrial temperature range (from -40°C to +85°C).

theory of operation

The AD5260/AD5262 provide a single- or dual-channel, 256-bit digitally controlled variable resistor (VR) device that operates up to 15V. Changing the programmed VR settings is done by clocking an 8/9 bit serial data word to the SDI (serial data input) pin. For the AD5262, the format of this data word is an address bit. a0 represents the first bit b8, followed by eight data bits b7 to b0, msb first. Table 2 and Table 3 provide the serial register data word format. The AD5262 address assignments are shown in Table 7 and are used to decode the location of the virtual reality latches (bits B7 to B0) that receive serial register data. VR outputs can be randomly changed one at a time. The AD5260/AD5262 are preset to mid-scale, simplifying fault state recovery at power-up. Mesoscale tanks can also be achieved at any time by maintaining the pr pins. Both sections have a built-in power-up preset that puts the wipers at a mid-scale preset when powered up. The operation of the power-on preset function depends only on the state of the V pin.

The AD5260/AD5262 include a power-down SHDN pin that puts the RDAC in a near-zero power state with terminal Ax open and wiper W connected to B, thereby consuming only leakage current in a virtual reality configuration. In shutdown mode, the VR latch settings are maintained so that when the mode resumes from shutdown, the VR settings return to their previous resistance values.

digital interface

The AD5260/AD5262 contain a 4-wire SPI compatible digital interface (sdi, sdo, cs, and clk). For the AD5260, the 8-bit serial word must be loaded with msb first. The format of the words is shown in Table 2. For the AD5262, the 9-bit serial word must be loaded with address bit a0 followed by the msb of data.

The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work fine. If a mechanical switch is used for product evaluation, it should be de-noised using a trigger or other suitable method. Figure 47 shows more details of the inter-NAL digital circuit. When CS is low, the clock loads data into the serial input register on each positive clock edge.

Data setup and data retention time determine the data validity time requirements. The AD5260 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. For the AD5262, when CS returns high, the last 9 bits of the input data word in the serial register remain unchanged. Any extra bits will be ignored. At the same time, CS goes high, which goes to the address decoder, enabling one of the two positive edge-triggered AD5262 RDAC latches (see Figure 48).

The target RDAC latch is loaded with the last 8 bits of the serial data word, completing an RDAC update. For the AD5262, two separate 9-bit data words must be entered to change the two VR settings.

During shutdown (SHDN), the SDO output pin is forced to the off (logic high) state to disable power dissipation in the pull-up resistor. A schematic diagram of the equivalent SDO output circuit is shown in Figure 49.

All digital inputs are protected with series input resistors and parallel Zener ESD structures, as shown in Figure 50. This works for:

Daisy Chain Operation

The Serial Data Out (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor to transfer data to the SDI pin of the next package. This allows multiple RDACs to be daisy-chained from a single-processor serial data line. The pull-up resistor termination voltage can be greater than the V supply voltage. It is recommended to increase the clock period when connecting pull-up resistors in series to the sdi pins of the following devices, as capacitive loads at the daisy-chain nodes connecting sdo and sdi between devices may cause time delays for subsequent devices. Users should be aware of this potential problem in order to successfully implement data transfers (see Figure 52). If two AD5260s are daisy-chained, a total of 16 bits of data are required. The first 8 bits in the format shown in Table 2 enter U2, and the second 8 bits in the same format enter U2 and enter U1. The CS pin should be held low until all 16 bits are in their respective serial registers, then the CS pin should be pulled high to complete the operation.

RDAC structure

The RDAC consists of a set of equal resistive segments with a set of analog switches acting as wiper connections. The number of positions is the resolution of the device. The AD5260/AD5262 have 256 connection points and can provide better than 0.4% settable resolution. Figure 53 shows the equivalent structure of the connections between the three terminals that make up one channel of the RDAC. sw and sw are always on, while one switch from sw(0) to sw(2–1) is on one at a time, depending on the resistor positions decoded from the data bits. Since the switch is not ideal, there is a 60Ω wiper resistance, r. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage, the higher the wiper resistance. Likewise, the higher the temperature, the higher the wiper resistance. When an accurate prediction of output resistance is required, the user should understand the contribution of the wiper resistance.

Variable Resistor Programming

Rheostat operation

The nominal resistance values of the RDAC between Terminal A and Terminal B are 20 kΩ, 50 kΩ, and 200 kΩ, respectively. The last three digits of the part number determine the nominal resistance value, eg 20 kΩ=20, 50 kΩ=50, 200 kΩ=200. The nominal resistance (r) of the vr has 256 contact points through the wiper terminal and the b terminal. The 8 bits of data in the rdac latches are decoded to select one of 256 possible settings. Assuming a 20 kΩ part is used, the first connection to the wiper starts at the B terminal of data 0x00. Because of the wiper contact resistance of 60Ω, such a connection creates a minimum resistance of 60Ω between terminal W and terminal B. The second connection is the first tap point of 138Ω (R=R/256 R=78Ω+60Ω) corresponding to data 0x01. The third connection is the next tap point, representing 216Ω (78×2+60) of data 0x02, and so on. For each additional LSB data value, the wipers move up the resistor ladder until the last tap point reaches 19982Ω (R−1 LSB+R). The wiper cannot be connected directly to the B terminal. A simplified diagram of the equivalent RDAC circuit is shown in Figure 53.

The general formula for determining the digitally programmed output resistance between w and b is:

where D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register and R is the nominal end-to-end resistance.

For example, when r=20kΩ, v=0v, and the a terminal is open, the rdac latch code sets the output resistance value of the following r. The result is the same if terminal A is connected to W.

Note that there is a finite wiper resistance of 60Ω under zero-scale conditions. Care should be taken to limit the current between W and B to no more than 20 mA in this state to avoid degradation or possible damage to the internal switches.

Like the mechanical potentiometers that the RDAC replaced, the AD5260/AD5262 are fully symmetrical. The resistance between wiper W and terminal A also produces a digitally controlled complementary resistance, R. Figure 54 shows the symmetric programmability of various terminal connections. When R is used, the B terminal can be left floating or fixed to the wiper. The resistance value that sets r starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general equation for this is:

For example, when r=20kΩ, v=0v, and the b terminal is open, set the following output resistance value of r for the rdac latch code shown in Table 10. The result is the same if terminal B is connected to terminal W.

The typical distribution of the nominal resistance r between channels is within ±1%. Equipment-to-equipment matching depends on the process batch, with a worst-case variation of ±30%. However, since the resistive element is fabricated with thin film technology, r has a low temperature coefficient of 35ppm/°C as a function of temperature.

Program the Potentiometer Divider

Voltage output operation

Digital potentiometers easily produce output voltages at wiper-to-B and wiper-to-A proportional to the input voltage at A to B. Ignore the effect of wiper resistance. For example, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage of W to B, starting at 0 V and ending at 1 LSB less than 5 V. The voltage of each LSB is equal to the voltage applied to Terminal A and Terminal B divided by the 256 positions of the potentiometer divider. Since the AD5260/AD5262 are powered by dual supplies, for any given input voltage applied to Terminal A and Terminal B, the general equation for defining the output voltage relative to ground at V is:

Operation of Digital Potentiometers in Voltage Divider Mode

The result is more precise operation at over temperature. Unlike the varistor mode, the output voltage depends on the ratio of the internal resistances r and r, not the absolute value; therefore, the drift is reduced to 5ppm/°C.

Layout and Power Bypass

A compact, minimal lead length layout design is best. Wires to the input should be as direct as possible with minimal wire length. The ground path should have low resistance and low inductance.

Also, for best stability, it is a good practice to bypass the power supply with a high quality capacitor. A 0.01µf to 0.1µf chip or chip ceramic capacitor should be used to bypass the device's power supply lines. A low ESR 1µF to 10µF tantalum or electrolytic capacitor should also be used at the power supply to minimize any transient disturbances (see Figure 55). Note that the digital ground should also be remotely connected to the analog ground to minimize ground bounce.

Terminal voltage operating range

The AD5260/AD5262 positive V and negative V supplies define the boundary conditions for proper operation of the 3-terminal digital potentiometer. Supply signals that appear on the A, B, and W terminals in excess of V or V are clamped by internal forward-biased diodes (see Figure 56).

The ground pins of the AD5260/AD5262 devices are primarily used as digital ground references and need to be connected to the common ground of the PCB. The digital input control signals of the AD5260/AD5262 must be referenced to the device ground pin (GND) and must meet the logic levels defined in Table 1. Internal level shifting circuitry ensures that the common-mode voltage range of the three terminals extends from V to V, regardless of the digital input level.

power-on sequence

Because diodes limit voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 56), V/V must be powered before any voltage is applied to the A, B, and W terminals. Otherwise, the diodes become forward biased, causing the v/v to inadvertently energize and potentially affect the rest of the user's circuit. The ideal power-up sequence is as follows: GND, V, V, V, digital input, and V/V/V. The order in which V/V/V and the digital inputs are powered up does not matter as long as they are powered up after V/V.

RDAC circuit simulation model

Internal parasitic capacitance and external capacitive loading control the AC characteristics of the RDAC. The −3 dB bandwidth of the AD5260 (20 kΩ resistor) is configured as a potentiometric divider and measures 310 kHz at half scale. Figure 28 provides the large-signal Bode plot characteristics for the three available resistor versions, 20 kΩ, 50 kΩ, and 200 kΩ. The parasitic simulation model is shown in Figure 57. The following section provides a list of macromodel nets for 20 kΩ RDACs.

application information

Dual Power Bipolar DC or AC Operation

The AD5260/AD5262 can be operated with dual power supplies, allowing control of ground-referenced AC signals or bipolar operation. AC signals up to V/V can be applied directly to Terminal A and Terminal B, and the output is taken from Terminal W. A typical circuit connection is shown in Figure 58.

Gain Control Compensation

Digital potentiometers are often used for gain control, such as the non-rotating gain amplifier shown in Figure 59.

Note that when the RDAC B terminal parasitic capacitance is connected to the op amp non-converting node, it introduces a zero for the 1/β term, which is +20 dB/Dec, while a typical op amp gain bandwidth product (GBP) has -20 dB/Dec characteristic. A large r2 and limited c1 can make the frequency of this zero much lower than the crossover frequency. Therefore, at the crossover frequency, the closure rate of the system is 40db/dec and the phase margin is 0. If the input is a rectangular pulse or step function, the output may ring or oscillate. Also, it can be loud when switching between two gain values, as this is equivalent to a step change at the input.

Depending on the op amp gbp, reducing the feedback resistor can extend the frequency of the zero enough to overcome the problem. However, a better approach is to include a compensation capacitor c2 to remove the effect caused by c1. The best compensation occurs when r1×c1=r2×c2. This is not an option because of the R2 change. Therefore, the relationship r1×c1=r2×c2 can be used and c2 is scaled to the maximum value of r2. Doing so may overcompensate and affect performance slightly when r2 is set to a low value. However, in the worst case, it avoids ringing or oscillation. For critical applications, C2 should be found empirically to meet the needs. In general, a c2 in the range of a few picofarads (pf) to no more than a few tenths of a pf is usually sufficient to compensate.

Similarly, there is w and a termination capacitor connected to the output (not shown). Fortunately, their effect is less pronounced at this node, and compensation can be avoided in most cases.

Programmable Voltage Reference

For voltage divider mode operation, as shown in Figure 60, the output of the digital potentiometer is typically buffered unless the load is much larger than R. Buffering is not only used for impedance conversion, but also allows heavier loads to be driven.

8-bit bipolar DAC

Figure 61 shows a low-cost 8-bit bipolar DAC. It provides the same number of adjustable steps, but not the same precision as traditional DACs. Linearity and temperature coefficients, especially at low value codes, can be skewed by the wiper resistance of the digital potentiometer. The output of this circuit is:

Bipolar Programmable Gain Amplifier

For applications requiring bipolar gain, Figure 62 shows an implementation. Digital potentiometer U1 sets the adjustment range. Therefore, with a given U2 setting, the wiper voltage at W2 can be programmed between V and -KV. Configuring A2 in non-vertical mode allows linear gain and attenuation. The transfer function is:

where k is the ratio of r/r set by u1.

Similar to the previous example, in the simpler and more common case where k=1, using a single digital potentiometer ad5260, u1 is replaced by a matched pair of resistors to apply v and -v at the ends of the digital potentiometer . The relationship becomes:

If r2 is large, several picofarad compensation capacitors may be needed to avoid any gain peaking.

As a result of adjusting d, a2 is configured for unity gain, gain 2, and gain 10. The result is a bipolar amplifier with linear programmable gain and 256 steps of resolution.

Programmable Voltage Source with Boost Output

For applications that require high current regulation, such as laser diode drivers or tunable lasers, a boost power supply can be considered (see Figure 63).

In this circuit, the inverting input of the op amp forces v to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the power supply via the p-channel fet, p1. The n-channel fet, n, simplifies the drive requirements of the op amp. A1 must be a rail-to-rail input type. Resistor r1 is needed to prevent p1 from turning on and off. The choice of r1 is a balance between the power loss of this resistor and the output off time. n1 can be any general-purpose signal FET. However, p1 is driven in saturation, so its power handling must be sufficient to dissipate (vv)×i power. This circuit can supply a maximum of 100mA from a 5V supply. Higher currents can be obtained by using p1 in a larger package. Note that a single n-channel FET can completely replace p1, n1, and r1. However, unless a separate power supply is used, the output swing is limited. For precision applications, a voltage reference such as adr423, adr292, or ad1584 can be applied to the input of a digital potentiometer.

Programmable 4mA to 20mA Current Source

A programmable 4 mA to 20 mA current source can be implemented with the circuit shown in Figure 64. The REF191 is a unique low supply headroom and high current handling accuracy reference that outputs 20mA at 2.048V. The load current is simply the voltage from the B terminal to the W terminal of the digital potentiometer divided by R.

The circuit is simple, but note that a dual supply op amp is ideal because the ground potential of the REF191 can swing from -2.048 V at zero scale to V at full scale set by the potentiometer. Although the circuit operates from a single supply, it reduces the programmable resolution of the system.

Programmable Bidirectional Current Source

For applications requiring bidirectional current control or higher voltage compliance, a Howland current pump can be used (see Figure 65). If the resistors are matched, the load current is:

Programmable Low Pass Filter

The AD5262 digital potentiometer can be used to construct a second-order Sallen key low-pass filter (see Figure 66). The design formula is as follows:

The user can first choose any convenient value for the capacitor. To achieve a maximum flat bandwidth of q = 0.707, let c1 be twice c2 and let r1 = r2. As a result, the user can tune r1 and r2 to the same setting to obtain the desired bandwidth.

programmable oscillator

In a classic wien bridge oscillator (see Figure 67), the wien network (r, r', c, c') provides positive feedback, while r1 and r2 provide negative feedback. At the resonant frequency f, the total phase shift is zero and the positive feedback causes the circuit to oscillate. R=R', C=C', and r2=r2a//(r2b+or), the oscillation frequency is:

where r is equal to r:

At resonance, set:

Balance the bridge. In practice, r2/r1 should be set slightly larger than 2 to ensure oscillations can start. However, the alternate conduction of diodes d1 and d2 ensures that r2/r1 is less than 2 momentarily, thereby stabilizing the oscillation. When the frequency is set, the oscillation amplitude can be tuned by r2b because:

v, i and v are interdependent variables. By appropriately choosing r2b, a balance of v convergence is achieved. r2b can be placed in series with discrete resistors to increase the amplitude, but the total resistance cannot be so large that it saturates the output.

In the two circuits of Figure 66 and Figure 67, frequency tuning requires that both RDACs be adjusted to the same setting. Because two channels are adjusted one at a time, intermediate states occur, which may not be acceptable for some applications. Therefore, different devices can also be used in daisy-chain mode so that parts can be programmed to the same settings at the same time.

Resistance scale

The AD5260/AD5262 offer nominal resistances of 20 kΩ, 50 kΩ, and 200 kΩ. For users who need lower resistance and still maintain the number of step adjustments, they can place multiple devices in parallel. For example, Figure 68 shows a simple scheme for two channels of parallel ad5262s. To linearly adjust half the resistance in each step, the user needs to program both channels consecutively with the same settings.

In voltage divider mode, lower resistances can be achieved as shown in Figure 69, with a discrete resistor in parallel. This equivalent resistance becomes:

Figure 68 and Figure 69 show that the change of the digital potentiometer is linear. However, in applications such as audio control, logarithmic taper adjustment is often preferred. Figure 70 shows an alternative resistance scaling method. In this circuit, the smaller r2 is relative to r, the more obvious the pseudo-logarithmic taper characteristic is.