introduce
The Spartan-II 2.5V field programmable gate array family provides users with high performance, rich logic resources and a rich feature set at a very low price. This six-person family offers system door densities ranging from 15,000 to 200,000. System performance supports up to 200 MHz.
Spartan II devices offer more gates, I/Os and features per dollar than other FPGAs by combining advanced process technology with a streamlined Virtex-based architecture. Features include block RAM (up to 56K bits), distributed RAM (up to 75264 bits), 16 selectable I/O standards, and 4 DLLs. Fast, predictable interconnects mean successive design iterations continue to meet timing requirements.
The Spartan II family is a superior alternative to mask-programmed ASICs. FPGAs avoid the initial costs, lengthy development cycles and inherent risks of traditional ASICs. Additionally, FPGA programmability allows design upgrades in the field without hardware replacement (not possible with ASIC).
Features Second-generation ASIC replacement technology
- Density up to 5292 logic cells
- Streamlined functions based on virtex architecture
- Unlimited reprogrammability
- very low cost
- Advanced 0.18 micron process system level features - SelectRAM + Hierarchical Memory:
16-bit/lut distributed ram
Configurable 4K-bit block RAM
· Fast interface to external RAM
- Fully PCI compliant
- Low-power segment routing architecture
- Complete readability of verification/observation
- Dedicated carry logic for high-speed operations
- Effective multiplier support
- Cascading chain of wide input functions
- Numerous registers/latches with enable, set, reset functions
- Four dedicated dlls for advanced clock control
- Four main low-skew global clock distribution nets
- IEEE 1149.1 Compliant Boundary Scan Logic Multifunction I/O and Package
- PB free tier option
- Low cost packaging in various densities
- Family footprint compatibility in public packs
- 16 high performance interface standards
- Hot-swappable compact PCI friendly
- Zero hold time simplifies system timing Full support for powerful Xilinx development system - base ISE series: fully integrated software
- Affiliate series: for 3rd party tools
- Fully automatic mapping, placement and routing

Overview
The Spartan II family of FPGs features a regular, flexible, programmable Configurable Logic Block (CLB) architecture surrounded by programmable input/output blocks (IOBs). There are four Delay Locked Rings (DLLs), one at each corner of the die. Two columns of block RAM are located on opposite sides of the die, between the CLB and IOB columns. These functional elements are interconnected through a robust hierarchy of versatile routing channels.
Spartan II FPGAs are customized by loading configuration data into internal static memory cells. An infinite number of reprogramming is possible using this method. The stored values in these cells determine the logic function and interconnection implemented in the FPGA. Configuration data can be read from an external serial prom (master serial mode) or written to the FPGA in slave serial, slave parallel or boundary scan mode.
Spartan II FPGAs are typically used in high-volume applications, and the versatility of a fast programmable solution adds to the benefits. Spartan II FPGAs are ideal for shortening product development cycles while providing a cost-effective solution for high-volume production.
Spartan Type II FPGAs enable high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan II devices offer system clock rates up to 200 MHz. Spartan II FPGAs provide the most cost-effective solution while maintaining leading performance. In addition to the traditional advantages of high-density programmable logic solutions, Spartan II FPGAs provide on-chip synchronous single- and dual-port RAM (block and distributed forms), dynamic link library clock drivers, programmable settings on all flip-flops, and reset, fast carry logic and many other functions.

Architectural Description Spartan II Array The Spartan II User Programmable Gate Array, shown in Figure 1, consists of five main configurable elements:
The IOB provides the interface between the package pins and the internal logic
The CLB provides the functional elements to build most of the logic Dedicated block RAM memory of 4096 bits each Clock dll for clock distribution delay compensation and clock domain control
Multifunctional Multilayer Interconnect Structure
The CLB forms the central logical structure with easy access to all support and routing structures. IOBs are located around all logic and memory elements to facilitate fast routing of signals on and off-chip.
Values stored in static storage cells control all configurable logic elements and interconnect resources. These values are loaded into the memory unit at power-up and can be reloaded if the functionality of the device needs to be changed.
The following sections discuss these elements in detail.
input/output block
The Spartan II IOB has input and output functions that support multiple I/O signaling standards. These high-speed inputs and outputs are capable of supporting a variety of state-of-the-art memory and bus interfaces.

The maximum user I/O available on the device and the number of user I/O available per device/package combination. The four global clock pins can be used as additional user I/O when not used as global clock pins. These pins are not included in the user I/O count.

The activation of the pull-up resistors before configuration is controlled globally by the configuration mode pins. If the pull-up resistors are not activated, all pins will float. Therefore, external pull-up or pull-down resistors must be set on pins that need to be at well-defined logic levels before configuration.
All pads are protected against damage from electrostatic discharge (ESD) and overvoltage transients. Two forms of overvoltage protection are provided, one that allows 5V compliance and one that does not. For 5V compliance, the zener type structure connected to ground turns on when the output rises to about 6.5V. When 5V compliance is not required, a conventional clamp diode can be connected to the output supply voltage VCCO. The type of overvoltage protection can be selected individually for each pad.
All Spartan II IOBs support IEEE1149.1 compliant boundary scan testing.
Input Path Buffers in the Spartan II IOB input path route input signals directly to internal logic or through optional input flip-flops.
There is an optional delay element on the D input of this flip-flop, which eliminates the pad-to-pad hold time. The delay matches the FPGA's internal clock distribution delay, ensuring that the pad-pad hold time is zero when used.
Each input buffer can be configured to conform to any supported low voltage signaling standard. In some of these standards, the input buffer utilizes a user-supplied threshold voltage vref. The need to provide VREF imposes restrictions on usage between standards. . I/O Banking Each input has optional pull-up and pull-down resistors for use after configuration.
Output Path The output path includes a tri-state output buffer that drives the output signal onto the pad. Output signals can be routed to buffers directly from internal logic or via optional iob output flip-flops.
Tri-state control of the outputs can also be routed directly from internal logic or by providing toggles that synchronize enable and disable.
Each output driver is individually programmable for a variety of low-voltage signaling standards. Each output buffer can source up to 24mA and sink up to 48mA. Drive strength and slew rate controls minimize bus transients.
In most signaling standards, the output high voltage depends on the externally supplied vcco voltage. The need to supply VCCOs imposes restrictions on the use of the standard. Look. The input and output banks an optional weak hold circuit connected to each output. When selected, the circuit monitors the voltage on the pad and weakly drives the pin high or low to match the input signal. If the pin is connected to a multi-source signal, the weak keeper will hold the signal in its last state if all drivers are disabled. Maintaining an efficient logic level in this way helps eliminate bus jitter.
Since the weak holdover circuit uses the iob input buffer to monitor the input level, the appropriate vref voltage must be provided if required by the signaling standard. The supplied voltage must comply with the I/O bank rules.

Input Output Banking Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are connected externally to device pins that serve a set of IOBs called a battery pack. Therefore, there are restrictions on which I/O standards can be combined in a given bank.
The eight I/O groups are the result of dividing each edge of the FPGA into two groups. Each bank has multiple VCCO pins that must be connected to the same voltage. The voltage is determined by the output standard in use. Some input standards require a user-supplied threshold voltage vref. In this case, some user I/O pins are automatically configured as inputs for the VREF voltage. About one-sixth of the I/O pins in the bank take on this role.
The VREF pins within a group are interconnected internally, so only one VREF voltage can be used within each group. However, all VREF pins in the group must be connected to an external voltage source for proper operation.
In a group, inputs that require vref can be mixed with those that do not require vref, but only one vref voltage can be used in a group. The input buffer using vref does not allow 5v. LVTTL, LVCMOS2 and PCI are 5V tolerant. The VCCO and VREF pins for each group appear in the device pin-out table.
In a given package, the number of vref and vcco pins can vary depending on the size of the device. In larger devices, more I/O pins are converted to VREF pins. Since these are a superset of the vref pins used for smaller devices, it is possible to design PCBs that allow migration to larger devices. All VREF pins of the intended largest device must be connected to the VREF voltage and not used for I/O.
The basic building block of the Configurable Logic Module Spartan II CLB is the Logic Cell (LC). The lc includes a 4-input function generator, carry logic and storage elements. The function generator output in each lc drives the clb output and d input of the flip-flop. Each Spartan II CLB contains four LCSs, organized into two similar slices. In addition to the four basic LCSs, the Spartan II CLB also contains logic that combines function generators to provide functions of five or six inputs .
Lookup Table The Spartan II function generator is implemented as a 4-input lookup table (lut). In addition to running as a function generator, each LUT can also provide 16 x 1 bits of synchronous ram. Additionally, two LUTs on-chip can be combined to create 16 x 2-bit or 32 x 1-bit synchronous ram, or 16 x 1-bit dual-port synchronous ram.
The spartan ii lut can also provide a 16-bit shift register, ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as digital signal processing.
storage element
The storage elements in the Spartan II chip can be configured as edge-triggered D-type flip-flops or level-sensitive latches. The d input can be driven by an on-chip function generator or directly by the on-chip input, bypassing the function generator.

Arithmetic logic dedicated carry logic provides fast operation carry capability for high-speed operation functions. The Spartan II CLB supports two independent conveyor chains, one for each slice. The height of the carry chain is two bits per CLB.
Arithmetic logic includes an XOR gate that allows a 1-bit full adder to be implemented in lc. In addition, dedicated AND gates improve the efficiency of the multiplier implementation.
A dedicated carry path is also available for cascading function generators to implement wide logic functions.
Tri-State Buffers Each Spartan II CLB contains two tri-state drivers (BUFTS) that drive the on-chip buses. Each Spartan II BUFT has an independent 3-state control pin and an independent input pin. Dedicated Routing Block Storage
Spartan II FPGAs contain several large block RAM memories. They complement distributed RAM look-up tables (LUTs), which provide shallow memory structures implemented in CLBs.
Block ram memory blocks are organized in columns. All Spartan II devices contain two of these posts, one for each vertical edge. These pillars extend the full height of the chip. Each memory block is four CLB highs, so a Spartan II device of eight CLB highs would contain two memory blocks per rank, for a total of four blocks.

Programmable Routing Matrix It is the longest delay path, limiting the speed of any worst-case design. Therefore, the Spartan II routing architecture and its location and routing software are defined in a single optimization process. This joint optimization minimizes long path delays for optimal system performance.
Joint optimization also reduces design compilation time because the architecture is software friendly. Due to the shortened design iteration time, the design cycle is correspondingly reduced.
local routing
Interconnect internal CLB feedback paths between luts, flip-flops, and general routing matrix (grm), providing high-speed connectivity for LUTs within the same CLB, linking them together with minimal routing delays providing high-speed between horizontally adjacent CLBs Direct path of connections, eliminating GRM latency

Generic Routing Most Spartan II signals are routed on generic routing, so most interconnect resources are associated with this level of routing hierarchy. General routing resources are located in horizontal and vertical routing channels associated with row and column clbs. Generic routing resources are shown below.
Adjacent to each CLB is a Generic Routing Matrix (GRM). GRM is a switching matrix that connects horizontal and vertical routing resources, and is also a means for CLB to gain access to general routing.
24 single wires route GRM signals to adjacent GRMs in four directions.
96 buffered hex lines route GRM signals in each of the four directions to other GRMs six blocks away. Organized in a staggered pattern, hex lines can only be driven at their endpoints. Hex line signals can be accessed at either the endpoints or the midpoint (three blocks away from the source). One third of the hex is bidirectional, the rest is unidirectional.
The 12 long lines are buffered bi-directional wires that distribute signals across equipment quickly and efficiently. Long vertical lines span the entire height of the device, and horizontal lines span the entire width of the device.
I/O Routing There are additional routing resources on the periphery of the Spartan II device that form the interface between the CLB array and the IOB. This extra routing, called Versaring, facilitates pin swapping and pin locking so that logic redesigns can fit into existing PCB layouts. Time to market is shortened because PCBs and other system components can be manufactured while the logic design is still in progress.
Dedicated Routing Certain types of signals require dedicated routing resources to maximize performance. In the Spartan II architecture, dedicated routing resources are provided for both types of signals.
Provides horizontal routing resources for the on-chip 3-state bus. Each CLB row provides four divisible buses, allowing multiple buses in a row

BUFT Connections for Dedicated Horizontal Buses Each CLB has two dedicated nets that propagate the carry signal vertically to adjacent CLBs.
Global Routing Global routing resources distribute clocks and other signals with very high fanout throughout the device. Spartan II devices include two layers of global routing resources, called primary and secondary global routing resources.
The main global routing resources are four dedicated global nets with dedicated input pins designed to distribute high fanout clock signals with minimal skew. Each global clock network can drive all CLB, IOB and block RAM clock pins. The main global net can only be driven by the global buffer. There are four global buffers, one for each global network.
The second global routing resource includes 24 backbones, 12 across the top of the chip and 12 across the bottom. From these lines, each column can distribute up to 12 unique signals through the 12 long lines in the column. These secondary resources are more flexible than primary resources because they are not restricted to routing only to clock pins.
clock distribution
The Spartan II family provides high-speed, low-slope clock distribution through the major global routing resources described above.
Four global buffers are provided, two in the upper center of the device and two in the lower center of the device. These drive the four main global nets, which in turn drive any clock pins.
Four dedicated clock boards are provided, one adjacent to each global buffer. Inputs to the global buffer can be selected from these pads or from signals in the general routing. Global clock pins do not have options for internal weak pull-up resistors.

Delay lock loop (dll)
Associated with each global clock input buffer is an all-digital delay-locked loop (DLL) that eliminates skew between the clock input board and the internal clock input pins throughout the device. Each dll can drive two global clock networks. The dynamic link library monitors input clocks and distributed clocks, and automatically adjusts clock delay elements. An additional delay is introduced so that the clock edge reaches the internal flip-flop exactly one clock cycle after reaching the input. This closed-loop system effectively eliminates clock distribution delays by ensuring that the clock edge arrives at the internal flip-flop synchronously with the clock edge arriving at the input.
In addition to eliminating clock distribution delays, DLLs provide advanced control over multiple clock domains. The dynamic link library provides four quadrature phases of the source clock and can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. It has six outputs.
The dynamic link library is also used as a clock mirror. The DLL can be used to eliminate board clocks across multiple Spartan II devices by driving the DLL's output off-chip and then turning it back on.
To ensure that the system clock works properly before the configured fpga starts, the DLL can delay the completion of the configuration process until after locking.
Boundary Scan Spartan II devices support all mandatory boundary scan commands specified in IEEE Standard 1149.1. A test access port (tap) and registers are provided for implementing the extest, sample/preload and bypass instructions. The tap also supports two user code instructions and an internal scan chain.
The GCN taps use dedicated package pins and always operate with LVTTL. For the TDO to work with LVTTL, the VCCO of bank 2 must be 3.3V. Otherwise, TDO will switch to orbit between ground and VCCO.
Boundary scan operations are independent of individual iob configurations and are not affected by packet type. All IOBs, including unbound IOBs, are treated as separate 3-state bidirectional pins in a scan chain. Maintaining bidirectional test capability after configuration facilitates testing of external interconnects.
Internal signals can be caught during extest by connecting them to unbound or unused IOBs. They can also be connected to unused outputs of iobs defined as unidirectional input pins.

Bit Sequence The bit sequence in each iob is: in, out, 3 states. Input-only pins only contribute bits to the boundary scan I/O data register, while output-only pins contribute to all three bits.
From the cavity-up view of the chip (as shown in the FPGA editor), starting from the upper right corner, the order of the Boundary Scan data register bits. The bsdl (Boundary Scan Description Language) files for spartan ii series devices can be found in the file download area of the xilinx website.

The development system Spartan II FPGA is supported by the Xilinx Foundation and Alliance CAE tools. The basic approach to Spartan II design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and simulation (such as Synopsys' FPGA Express), while Xilinx provides dedicated architecture-specific tools for implementation.
The xilinx development system is integrated under the xilinx design manager software, providing designers with a common user interface, regardless of their choice of input and validation tools. The software simplifies the selection of implementation options with drop-down menus and online help.
Applications ranging from schematic capture to placement and routing (PAR) can be accessed via software. Sequences of program commands are generated prior to execution and stored for documentation purposes.
Several advanced software features contributed to the design of the Spartan II. For example, Relatively Placed Macros (RPMs) are schematic-based macros that have relative position constraints to guide their placement. They help ensure optimal implementation of public functionality.
For hdl design entry, xilinx's fpga development system provides interfaces to multiple integrated design environments.
A standard interface file specification, Electronic Design Interchange Format (EDIF), simplifies file transfer to and from development systems.
Spartan II FPGAs are supported by a unified library of standard functions. This library contains over 400 primitives and macros ranging from 2-input AND gates to 16-bit accumulators, including arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, boolean functions , multiplexers, shift registers, and barrel shifters.
The "soft macros" section of the library contains detailed descriptions of common logic functions, but does not contain any partitioning or location information. Therefore, the performance of these macros depends on the partitions and locations obtained during implementation.
rpms, on the other hand, contain predetermined partitioning and placement information that allows optimal implementation of these functions. Users can create their own soft macro or RPM library based on the macros and primitives in the standard library.
The design environment supports hierarchical design entries, where high-level schematics contain major functional blocks and low-level schematics define the logic within those blocks. These hierarchical design elements are automatically combined by the implementation tool. Different design entry tools can be combined in a hierarchical design, allowing the most convenient entry method for each part of the design.
The Design Implementation Location and Path Tool (PAR) automatically provides the implementation flow described in this section. The partitioner is designed with the EDIF netlist and the logic is mapped into the FPGA's architectural resources (eg, CLBs and IOBs). The placer then determines the best locations for these blocks based on their interconnection and desired performance. Finally, routers interconnect the blocks.
The PAR algorithm supports fully automatic implementation of most designs. However, for demanding applications, the user can exercise varying degrees of control over the process. User partition, location, and routing information can optionally be specified during design entry. The realization of a highly structured design can benefit greatly from basic floorplanning.
Implementation software incorporates Timing Wizard® timing-driven placement and routing. Designers specify timing requirements along the entire path during design entry. The timing path analysis routine in the PAR then recognizes these user-specified requirements and adapts to them.
Timing requirements are entered on the schematic in a form directly related to the system requirements, such as the target clock frequency or the maximum allowable delay between two registers. In this way, the overall performance of the system along the entire signal path will automatically adjust to user-generated specifications. There is no need to provide specific timing information for individual networks.
Design Verification In addition to traditional software simulation, FPGA users can use in-circuit debugging techniques. Because xilinx devices are infinitely reprogrammable, designs can be verified in real-time without the need for extensive software simulation vector sets.
The development system supports software emulation and in-circuit debugging techniques. For simulation, the system extracts the post-placement timing information from the design database and re-annotates this information into the netlist for use by the simulator. Alternatively, users can use a static timing analyzer to verify timing-critical parts of the design.
For in-circuit debugging, the development system includes a download and readback cable that connects the fpga in the target system to a pc or workstation. After downloading the design to the fpga, the designer can single-step the logic and read the contents of the flip-flop to observe the internal logic state. Simple modifications can be downloaded to the system in minutes.
Configuration configuration is the process of loading the design bitstream generated by the xilinx development software into the FPGA's internal configuration memory. Spartan II devices support both serial configuration, using master/slave serial and JTAG modes, and byte-wide configuration, using slave parallel mode.
Profile Spartan II devices are configured by sequentially loading the data frames connected to the profile. Table 7 shows how much non-volatile storage space is required for Spartan II devices.
It's important to note that while a prom is typically used to store configuration data before loading it into the FPGA, it's not required. Various types of underpopulated non-volatile memory (i.e. hard disk, flash memory) already on or off the board
configuration mode

Clear Configuration Memory Device Indicates that clearing configuration memory is in progress by setting the initial value to low. At this point, the user can delay configuration by keeping program or init low, which will cause the device to remain in the memory clear phase. Note that the bidirectional initialization line is driving a low logic level during memory clear. So to avoid contention, an open drain driver can be used to keep init low.
In the absence of a delay, the device indicates that the memory is completely clear by driving init high. During this low-to-high transition, the FPGA samples its mode pin.
Loading configuration data Once init is high, the user can start loading the configuration data frame into the device. The details of loading configuration data are discussed in the separate chapters dealing with configuration modes. The sequence of operations required to load configuration data using serial mode is shown in Figure 13. Loading data using slave parallel mode is shown in Figure 18 on page 18.
CRC error checking During loading of configuration data, the crc value embedded in the configuration file is checked against the crc value calculated in the FPGA. If the crc values do not match, the fpga will start low to indicate a framing error and abort configuration.
To reconfigure the device, the program pin should be asserted to reset the configuration logic. Recycling power also resets the configured FPGAs. Look. The clear configuration memory boot boot sequence oversees the transition of the FPGA from the configuration state to full user operation. A match of the crc value, indicating a successful load of configuration data, starts the sequence.
During startup, the device performs four actions:
1. Completed assertions. A done to go high failure may indicate a configuration data load failure.
2. Launch of the Global Tri-State Network. This will activate the I/O that assigns the signal. The remaining I/Os remain in a high-impedance state with weak internal pull-down resistors.
3. Negative Global Settings Reset (GSR). This allows all triggers to change state.
4. Global write enable (gwe) assertion. This allows all ram and triggers to change state.
By default, these operations are synchronized with cclk. The entire boot sequence lasts 8 cycles, called C0-C7, after which the loaded design works perfectly fine. These four operations can be selected to open any cclk cycle c1-c6 through the settings in the xilinx development software. Thick lines show default settings.
Select sync to done timing by setting the gts, gsr and gwe periods to done values in the configuration options. This causes these signals to transition one clock cycle after completing an external high transition.

Serial Mode There are two serial configuration modes: In master serial mode, the FPGA controls the configuration process by driving the cclk as an output. In slave serial mode, the fpga passively receives cclk as input from an external agent that controls the configuration process (such as a microprocessor, cpld, or a second fpga in master mode). In both modes, the FPGA is configured by loading one bit per cclk cycle. The msb of each configuration data byte is always written to the DIN pin first.

Startup waveform loads serial mode configuration data Slave serial mode In slave serial mode, the cclk pin of the FPGA is driven by an external source, allowing the FPGA to be configured from other logic devices such as a microprocessor or in a daisy-chain configuration. Figure 14 shows the master serial fpga slave prom configuration slave serial fpga connection. The serial bit stream must be set on the DIN input pin a short time before each rising edge of the externally generated cclk. Multiple FPGAs in slave serial mode can be daisy-chained from one source to configure. After an FPGA is configured, the data for the next device is routed to the DOUT pins. Change data when Douban rises

edge of CCLK. Configuration must be delayed until the initial pins of all daisy-chained FPAs are high.

Serial Mode In master serial mode, the fpga's cclk output drives the xilinx prom, which feeds the serial stream of configuration data to the fpga's din input. The Spartan II device in master serial mode should be connected as shown on the left device. The master serial mode is selected by <00x> on the mode pins (m0, m1, m2). The prom reset pin is driven by init and the ce input is driven by done. This interface is the same as the slave serial mode except that an internal to fpga oscillator is used to generate the configuration clock (cclk). Any different frequency from 4 to 60 MHz can be set using the configrate option in the xilinx development software. At power up, when the first 60 bytes of configuration data are loaded, the cclk frequency is always 2.5mhz. The frequency is used until the configrate bits, part of the config file, are loaded into the FPGA, at which point the frequency will be changed to the selected configrate. The default configuration rate is 4 MHz unless a different frequency is specified in the design. The period of the cclk signal generated by the internal oscillator deviates from the specified value by +45%–30%.

From parallel mode From parallel mode is the fastest configuration option. Byte-range data is written to the fpga. A busy flag is provided to control data flow with clock frequency fccnh above 50mhz.
Connection of two Spartan II devices using slave parallel mode. Slave parallel mode is selected by a<011> on the mode pins (m0, m1, m2).
If using .bit, .rbt, or non-interchange hexadecimal format configuration files for parallel programming, the most significant bits (that is, the leftmost bits of each configuration byte, as shown in a text editor) must be routed to the d0 input on the fpga.
The proxy control configuration is not shown. Typically, a processor, microcontroller or cpld controls the slave parallel interface. The control agent provides byte-range configuration data, CCLK, chip select (CS) signals, and write signals (write). If the fpga asserts busy (high), it must hold the data until busy goes low.
Once configured, the pins of the slave parallel port (d0-d7) can be used as additional user I/O. Alternatively, the port can be reserved to allow high-speed 8-bit reads -
return. The data can then be read by deasserting the write.

Slave Parallel Configuration Circuit Diagram Multiple Spartan II FPAs can be configured in Slave Parallel Mode with an analog start-
Naively. To configure multiple devices this way, connect the individual cclk, data, write, and busy pins of all devices in parallel. Load each device individually by asserting each device's cs pin in turn and writing the appropriate data. The sync to done startup timing is used to ensure that the startup sequence does not begin until all fpgas have been loaded. For this example, the user keeps write and cs low throughout the sequence of write operations. Note that when asserting cs on successive cclks, write must either keep asserting or de-asserting. Otherwise an abort is initiated, as described in the next section.
1. Drive data onto d0-d7. Note that to avoid contention the datasource should not be enabled when cs is low and write high. Likewise, when write is high, no
CS for multiple devices should be asserted.
2. On the rising edge of cclk: If busy is low, accept data on this clock. If busy is high (from a previous write), data is not accepted. Instead, an accept occurs on the first clock after busy goes low, and data must be held until that happens.
3. Repeat steps 1 and 2 until all data is sent.
4. Deassert CS and write.
If cclk is slower than fccnh, the fpga will never assert busy. In this case the above handshake is unnecessary and the data can simply be fed into the FPGA per cclk.

Boundary Scan Mode In boundary scan mode, no non-designated pins are required, and the configuration is completely done through the IEEE 1149.1 test access port.
Configuration via TAP uses special CFG instructions. This instruction allows the data input on the TDI to be converted into packets for the internal configuration bus.
The following steps are required to configure fpga via boundary scan port.
1. Load the cfg_-in instruction into the boundary scan instruction register (ir)
2. Enter shift dr (sdr) state
3. Convert the standard configuration bitstream to TDI
4. Return to Run Test Idle (RTI)
5. Load the jstart instruction into ir
6. Enter SDR state
7. Through the sequence clock TCK (length programmable)
8. Return to RTI
Configuration and readback is always possible with a click. Boundary scan mode simply locks the other modes. Boundary scan mode is selected by a<10x> on the mode pins (m0, m1, m2).
Configuration data stored in the Spartan II configuration memory can be read back for verification. In addition to configuration data, the contents of all flip-flops/latches, lut ram and block ram can be read. This function is used for real-time debugging.
See xapp176, Spartan II FPGA Family Configuration and Readback for more details.

Use a delay lock loop
Spartan II's family of FPGAs offers up to four all-digital dedicated on-chip delay-locked loop (DLL) circuits that provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control . These specialized dlls can be used to implement circuits that improve and simplify system-level designs.
Introduction As fpgas sizes increase, the quality distribution of on-chip clocks becomes more and more important. Clock skew and clock delay can affect device performance, and in large devices the task of managing clock skew and clock delay becomes more difficult using traditional clock trees. The Spartan II family of devices addresses this potential problem by providing up to four all-digital dedicated on-chip delay-locked loop (DLL) circuits that provide zero propagation delay and low clock skew between output clock signals distributed throughout the device.
Each dll can drive up to two global clock routing networks within the device. A global clock distribution network minimizes clock skew due to load differences. By monitoring a sample of the DLL's output clock, the DLL can compensate for delays on the routing network, effectively eliminating delays from external input ports to individual clock loads within the device.
In addition to providing zero latency to the user source clock, the DLL can also provide multiple phases of the source clock. The dll can also act as a clock multiplier, or it can divide the user source clock by 16.
Clock multiplication provides designers with many design options. For example, a 50mhz source clock multiplied by the dll can drive an FPGA design operating at 100mhz. This technique simplifies board design because the clock paths on the board no longer distribute such high-speed signals. Multiplying clocks also give designers the option of time-domain multiplexing, using a circuit twice per clock cycle, occupying less area than two copies of the same circuit. The two dlls in can be concatenated to increase the effective clock multiplication factor to 4.
The dll can also act as a clock mirror. By driving the dll out of the chip, and then in again, the dll can be used to smooth out board clock skew across multiple devices.
To ensure that the system clock is established before the device "wakes up", the DLL can delay the completion of the device configuration process until the DLL achieves lock.
Eliminating on-chip clock delays with dynamic-link libraries (DLLs) can greatly simplify and improve system-level designs involving high-fanout, high-performance clocks.

The clkdll primitives pin description library clkdll primitives provide access to the full set of dll functions required when implementing more complex applications using the dll.
source clock input -clkin
The clkin pin provides the user source clock (the clock signal when the dll is running) to the dll. The clkin frequency must be within the range specified in the datasheet. This clock signal must be provided by a global clock buffer (bufg) driven from another clkdll or a global clock input buffer (ibufg).
Feedback Clock Input - CLKFB
The dynamic link library requires a reference or feedback signal to provide delay compensation output. Only connect the clk0 or clk2x dll output to the feedback clock input (clkfb) pin to provide the necessary feedback to the dll. A feedback clock input can also be provided through one of the following pins.
IBUFG - Global Clock Input Board If the ibufg is sourced from the clkfb pin, the following special rules apply.
1. The external input port must provide a signal to drive the ibufg i pin.
2. If both the CLK0 and CLK2X outputs drive off-chip devices, the CLK2X output must be fed back to the device.
3. This signal must drive obufs directly and nothing else.
These rules enable software to determine which dll clock output source clkfb pin.
Reset Input-Reset When the reset pin reset is active, the lock signal is deactivated for four source clock cycles. The RST pin (active high) must be tied to a dynamic signal or ground. When the DLL delay tap is reset to zero, the DLL clock output pin may malfunction. Activation of the RST pin also heavily affects the duty cycle of the clock output pins. Also, the dll's output clocks no longer cancel each other out. For these reasons, the reset pin is rarely used unless the device is reconfigured or the input frequency is changed.
2X clock output - CLK2X
The output pins clk2x provide a multiplied clock with automatic 50/50 duty cycle correction. Before CLKDLL achieves lock, the CLK2X output appears as a 1X version of the input clock with a 25/75 duty cycle. This behavior allows the DLL to lock on the correct edge relative to the source clock. This pin is not available on the clkdllhf primitive.
Clock divider output - CLKDV
The clock divider output pin, clkdv, provides a low frequency version of the source clock. The clkdv_u divide attribute controls clkdv such that the source clock is divided by n, where n is 1.5, 2, 2.5, 3, 4, 5, 8, or 16.
This feature provides automatic duty cycle correction so that the CLKDV output pin always has a 50/50 duty cycle.
1x Clock Out - CLK [0 90 180 270]
The 1X clock output pin clk0 represents the delay compensated version of the source clock (clkin) signal. The clkdll primitive provides three phase-shifted versions of the clk0 signal, while clkdllhf provides only 180 phase-shifted versions.
The dynamic link library provides duty cycle correction on all 1X clock outputs, making all 1X clock outputs have a 50/50 duty cycle by default. The duty cycle correction feature (true by default) controls this feature. To disable dll duty cycle correction, append the duty cycle correction=false attribute to
DLL symbols. When duty cycle correction is disabled, the output clock has the same duty cycle as the source clock.
The dll clock output can drive obuf, bufg, or route directly to the target clock pin. The dll clock output can only drive bufgs that are on the same edge (top or bottom).
Lock Out - Lock In order to implement the lock, the DLL may need to sample several thousand clock cycles. After the dll is locked, the lock signal is activated. The DLL Timing Parameters section of the datasheet provides an estimate of lock time.
To ensure that the system clock is established before the device "wakes up", the DLL can delay the completion of the device configuration process until after the DLL is locked. The startup_wait property activates this feature.
The DLL output clock is invalid until the lock signal is activated, and may experience glitches, spikes, or other spurious movements. In particular the CLK2X output will appear as a 1X clock with a 25/75 duty cycle.
The dll properties attribute provides access to Spartan II series DLL functions such as clock division and duty cycle correction.
Duty Cycle Correction Characteristics
The 1X clock outputs CLK0, CLK90, CLK180 and CLK270 use duty cycle corrected defaults to show a 50/50 duty cycle. The duty cycle correction property (true by default) controls this feature. To disable DLL duty-cycle correction for 1X clock output, append duty-cycle-correction=pair
DLL symbols. When duty cycle correction is disabled, the output clock has the same duty cycle as the source clock.

Clock Split Properties
The clkdv_divide attribute specifies how the signal on the clkdv pin is frequency divided relative to the clk0 pin. Allowed values for this property are 1.5, 2, 2.5, 3, 4, 5, 8, or 16; the default is 2.
Startup Delay Property The value of this property startup_wait is true or false (default). If true, the device configuration complete signal will wait until the dll is locked, then go high.
dll location constraints
The distribution of dlls is such that there is one dll in every corner of the device. The location constraint loc attached to a dll symbol with numeric identifier 0, 1, 2, or 3 controls the dll location. Figure 26 shows the orientation of the four DLLs and their corresponding clock resources.
The loc attribute uses the following form.

Design Factors Use the following design considerations to avoid pitfalls and increase the success rate of designing with xilinx devices.
input clock
The dll's output clock signal, which is essentially a delayed version of the input clock signal, reflects any instabilities in the input clock in the output waveform. Therefore, the quality of the dll input clock is directly related to the quality of the output clock waveform generated by the dll. dll input clock requirements are specified in the datasheet.
In most systems, a crystal oscillator generates the system clock. The dynamic link library can be used with any commercial crystal oscillator. For example, most crystal oscillators produce output waveforms with a frequency tolerance of 100ppm, which means a 0.01% variation in clock cycles. The dynamic link library works reliably on input waveforms with a frequency drift of up to 1 nanosecond, which exceeds the order of magnitude required to support any crystal oscillator in the industry. However, cycle-to-cycle jitter must be kept to less than 300ps at low frequencies and less than 150ps at high frequencies.
Changes in the input clock that change the period of the input clock by more than the maximum drift amount require a manual reset of clkdll. Failure to reset the dll will produce unreliable lock signals and output clocks.
The input clock can be stopped with little impact on the dll. Stopping the clock should be limited to less than 100 microseconds to keep the device cool to a minimum. The clock should stop during the low phase and should see a full high period when it resumes. During this time, the lock will be held high and will remain high when the clock is recovered.
When the clocks are stopped, one to four clocks are still observed when the delay line is refreshed. When the clock restarts, one to four clocks will not observe the output clock because the delay line is full. The most common case is two or three clocks.
In a similar manner, a phase shift of the input clock is also possible. The phase shift will propagate to the output 1 to 4 clocks after the original shift, without interrupting clkdll control.
Output Clock As mentioned earlier in the dll pin description, some restrictions apply to the connection of the output pins. The dll clock output can drive the obuf, the global clock buffer bufg, or route directly to the target clock pin. The only bufgs that the dll clock output can drive are two bufgs located on the same edge (top or bottom) of the device.
Do not use the dll to output the clock signal until the lock signal is activated. Until the lock signal is activated, the DLL output clock is invalid and may experience glitches, spikes, or other spurious movements.
Useful Application Examples The Spartan II dynamic link library can be used in a variety of creative and useful applications. The following examples show some of the more common applications.

Using the block RAM function
The Spartan II FPGA family offers a dedicated on-chip, true dual read/write port synchronous RAM with 4096 memory cells. Each port of the block ram memory can be independently configured as a read/write port, read port and write port, and can be configured to a specific data width. Block RAM memory provides new features that enable FPGA designers to simplify their designs.
Operating Modes The block RAM memory supports two operating modes.
read through

Write-back read (one clock edge)
The read address is registered on the read port clock edge, and the data appears on the output after the RAM access time. Some memories may put latches/registers on the output, depending on whether you want a faster clock output compared to the setup time. This is generally considered a lower solution because it changes the read operation to an asynchronous function and may lose address/control line transitions during the generation of the read pulse clock.

Write Back (Single Clock Edge)
The write address is registered on the write port clock edge, and the data input is written to memory and mirrored to the write port input.
Block RAM Features
1. All inputs are registered with the port clock and have timing specifications set to the clock.
2. All outputs are capable of reading and writing, depending on the state of the port. The output relative to the port clock is available after the clock-to-output timing specification.
3. Block ram is real sram memory, there is no combinatorial path from address to output. This feature is still available for lut units in clbs.
4. Complete independence between ports (ie clock, control, address, read/write function and data width) without arbitration.
5. Only one clock edge is required for a write operation.
6. A read operation requires only one clock edge.
The output ports are locked by an automatic timing circuit to ensure trouble-free reading. The state of the output port does not change until the port performs another read or write operation.

enable en[ab]
Enabling the pins affects the port's read, write, and reset functions. Ports with inactive enable pins keep the output pins in their previous state and do not write data to the memory cell.
Write Enable WE[AB]
Activating the write enable pin allows the port to write to the memory cell. When activated, the content of the data input bus is written to the ram at the address pointed to by the address bus, and the new data is also reflected on the data output bus. When inactive, a read operation occurs and the contents of the memory cells referenced by the address bus are reflected on the data output bus.
reset RST[AB]
The reset pin forces the data output bus latch to return to zero synchronously. This doesn't affect the RAM's memory cells, nor does it interfere with writes on the other port.
Address Bus Address[AB]<:0>
The address bus selects the memory cell for reading or writing. The width of the port determines the required width of the bus,
data<:0> in bus di[ab]
The data in the bus provides the new data value to be written to RAM. The width of this bus and port is the same as the data output bus do[ab]<:0>
The data output bus reflects the contents of the memory cell referenced by the address bus on the last active clock edge. During a write operation, the data out bus reflects the data on the bus. The width of this bus is equal to the width of the port.
Each port's four control pins (CLK, EN, WE, and RST) have independent inversion control as a configuration option.
Address Map Each port accesses the same set of 4096 memory cells using an addressing scheme that is related to the port width. The following formula describes the physical ram location addressed for a specific width (of interest only if the two ports use different aspect ratios).
start=([addrport+1]*widthPort) – 1
end=addrport*widthport

Creating larger RAM structures blocks RAM columns with dedicated routing, allowing cascading blocks with minimal routing delays. This enables wider or deeper ram structures with less timing penalty than using normal routing channels.
Location Constraint Block RAM instances can have a loc attribute attached to constrain placement. The placement of the block ram is independent of the clb location naming convention, allowing the loc attribute to be easily transferred from one array to another.
The loc attribute uses the following form:
location=Ramb4RC#
Ramb4_r0c0 is the Ramb4 location in the upper left corner of the device.
Conflict resolution block ram memory is a true dual read/write port ram that allows simultaneous access to the same memory cell from both ports. When one port writes to a given memory cell, the other port cannot address that memory cell (for writing or reading) in the Clock-to-Clock Settings window. Details of port and memory cell write conflict resolution are listed below.
If two ports simultaneously write to the same memory cell, violating the clock-to-clock setup requirements, the stored data is considered invalid.
If one port attempts to read the same memory cell while the other port writes at the same time, violating the clock-to-clock setup requirements, the following will occur.
- write success
- The data written on the port accurately reflects the data written.
- Invalid data output on read port.
The conflict will not cause any bodily harm.
The block RAM AC switching characteristics are specified in the single-port timing data sheet. Block RAM memory is initially disabled.
On the first rising edge of the clk pin, the addr, di, en, we, and rst pins are sampled. The en pin is high and the we pin is low, indicating a read operation. The do bus contains the contents of the memory location 0x00 indicated by the addr bus.
On the second rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The en and we pins are high to indicate a write operation. The do bus mirrors the di bus. The DI bus is written to memory location 0x0f.
On the third rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The en pin is high and the we pin is low, indicating a read operation. The do bus contains the contents of the memory location 0x7e indicated by the addr bus.
On the fourth rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The en pin is low to indicate that the block ram memory is now disabled. The do bus retains the last value.
Dual port timing tbcc only matters when both ports have the same address and at least one port is doing a write. When the write conditions of the clock-to-clock setup parameters are violated, the memory contents of this location will be invalidated. When the write-read condition violates the clock-to-clock setup parameters, the contents of the memory will be correct, but the read port will contain invalid data. On the first rising edge of clka, memory location 0x00 will be written with the value 0xaaaa and mirrored on the doa bus. The last operation on port B was a read to the same memory location 0x00. The DOB bus of port B does not change with the new value on port A and retains the last value read. Soon after, port B performs another read to memory location 0x00, and the DOB bus now reflects the new memory value written by port A.
On the second rising edge of clka, memory location 0x7e is written with the value 0x9999 and mirrored on the doa bus. Port b then performs a read operation on the same memory location without violating the tbccs parameter, and dob reflects the new memory value written by port a.

Timing diagram for a true dual port read and write block RAM memory violation of the TBCC parameter on the third rising edge of CLKA, two writes to memory location 0x0F. The DOA and DOB buses reflect the contents of the DIA and DIB buses, but the value stored at 0x7E is invalid.
On the fourth rising edge of clka, a read operation is performed at memory location 0x0f and there is invalid data on the doa bus. Port B also performs a read to memory location 0x0f and reads invalid data.
On the fifth rising edge of clka, a read operation is performed that does not violate the tbccs parameter previously written to 0x7e by the b port. The doa bus reflects the most recently written value of the b port.
The initialization block ram memory can be initialized during the device configuration sequence. 16 initialization properties of each 64 hex values (4096 bits in total) set the initialization of each RAM. These properties are shown in Table 13. Any initialization property not explicitly set to zero. Part of the initialization string is padded with zeros. Initialization strings larger than 64 hex values generate errors. Use generics in vhdl emulator, use parameters in verilog emulator, emulate ram with init values
Initialization block ram structures in vhdl and synopsys can be initialized with vhdl for simulation and synthesis for inclusion in edif output files. The mocking of the vhdl code uses generics to pass initialization. The synopsys fpga compiler does not currently support generics. Initialization values are attached to RAM as attributes via the built-in synopsys dc_script. The translate_off statement stops the synthetic translation of generic statements. The code below demonstrates a module that uses these techniques.
Initializing block ram structures in verilog and synopsys can be initialized in verilog for simulation and synthesis for inclusion in edif output files. The simulation of verilog code uses defparam to pass initialization. Synopsys' fpga compiler currently does not support defparam. Initialization values are attached to RAM as attributes via the built-in synopsys dc_script. The translate_off statement stops the synthetic translation of the defparam statement. The code below demonstrates a module that uses these techniques.
block memory generation
The coregen program uses the block ram feature to generate memory structures. The program outputs vhdl or verilog simulation code templates and edif files for inclusion in designs.

Using Multifunction I/O
The Spartan II FPGA family includes a highly configurable high-performance I/O resource called multipurpose I/O that supports multiple I/O standards. The versatile I/O resource is a powerful set of features including programmable control of output drive strength, slew rate, input delay and hold time. System-level design can be improved and simplified by taking advantage of the flexibility and general-purpose I/O features and design considerations described in this document.
Introduction As FPGAs continue to grow in size and capacity, so do the larger and more complex systems they are designed for that require higher I/O standards. Additionally, as system clock speeds continue to increase, the need for high-performance I/O becomes more important. While chip-to-chip latency has an increasing impact on overall system speed, the task of achieving the required system performance has become more difficult as low-voltage I/O standards become more common. General Purpose I/O is a revolutionary input/output resource for Spartan II devices that addresses this potential problem by providing a highly configurable, high-performance alternative to the I/O of more traditional programmable devices O resources. Spartan II multifunction I/O capabilities combine the flexibility and time-to-market advantages of programmable logic with the high performance previously only available in ASICs and custom ICs.
Each general-purpose I/O block can support up to 16 I/O standards. Supporting such a variety of I/O standards can support a variety of applications from general-purpose standard applications to high-speed low-voltage memory buses.
The multifunction I/O block also provides selectable output drive strength and programmable slew rate for LVTTL output buffers, as well as selectable, programmable weak pull-up, weak pull-down, or weak "hold" circuits ideal for For external bus applications Each input/output block (iob) includes three registers, each for input, output, and tri-state signals within the iob. These registers can optionally be configured as d-type flip-flops or level-sensitive latches.
The input buffer has an optional delay element to guarantee a zero hold time requirement for the input signal registered in the iob.
The multi-function I/O function also provides dedicated resources for input reference voltage (VREF) and output source voltage (VCCO), as well as a convenient banking system that simplifies board design.
The built-in features and multiple I/O standards supported by the versatile I/O feature can greatly simplify and improve system-level design and board design.
Fundamentals Modern bus applications pioneered by the largest and most influential companies in the digital electronics industry often employ new I/O standards tailored specifically to the needs of the application. The bus I/O standard provides specifications for other vendors who create products designed to interface with these applications. Each standard typically has its own specifications for current, voltage, I/O buffering, and termination.
The ability to provide the flexibility and time-to-market advantages of programmable logic increasingly depends on the ability of programmable logic devices to support an ever-increasing variety of I/O standards Multipurpose I/O resources with highly configurable input and output buffers , which provides support for various I/O standards.

Overview of Supported I/O Standards While most I/O standards specify allowable voltage ranges, only typical voltage values are recorded in this document. For details on each specification, visit the Electronic Industries Alliance jedec website h
LVTTL - Low Voltage TTL
The low voltage ttl (lvttl) standard is a general eia/jesdsa standard for 3.3v applications using lvttl input buffers and push-pull output buffers. This standard requires a 3.3V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a terminal voltage (VTT).
2.5V Low Voltage CMOS
The low voltage cmos for 2.5v or lower (lvcmos2) standard is an extension of the lvcmos standard (jesd 8.5) for general 2.5v applications. This standard requires a 2.5V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or board terminal voltage (VTT).
PCI - Peripheral Component Interface The Peripheral Component Interface (PCI) standard specifies support for 33 MHz and 66 MHz PCI bus applications. It uses lvttl input buffers and push-pull output buffers. This standard does not require the use of a reference voltage (VREF) or board termination voltage (VTT), but does require a 3.3V output source voltage (VCCO). I/Os configured for the PCI, 33 MHz, 5V standard also allow 5V.
GTL - Gun Transceiver Logic Terminates Gun Transceiver Logic (gtl) standard is a high-speed bus standard (jesd8.3) invented by xerox company. xilinx implements terminating changes to this standard. This standard requires differential amplifier input buffers and open-drain output buffers.
GTL+ - Gun Transceiver Logic Enhancement The Gun Transceiver Logic Enhancement (GTL+) standard is a high-speed bus standard (Jesd 8.3) first used by the Pentium Pro processor.
High Speed Transceiver Logic The High Speed Transceiver Logic (hstl) standard is a general purpose high speed 1.5v bus standard initiated by IBM (Eia/Jesd 8-6). There are four variants or levels of this standard. General purpose I/O devices support classes I, III, and IV. This standard requires differential amplifier input buffers and push-pull output buffers.
Stub Family Termination Logic for sstl3-3.3v Stub Family Termination Logic for 3.3V (SSTL3) standard is a general purpose 3.3V memory bus standard also sponsored by Hitachi and IBM (Jesd8-8). This standard is divided into Class I and Class II. Multifunction I/O devices support two classes of the SSTL3 standard. This standard requires differential amplifier input buffers and push-pull output buffers.
SSTL2-2.5V Short String Termination Logic Stub Series Termination Logic for the 2.5V (SSTL2) Standard is a common 2.5V memory bus standard sponsored by Hitachi and IBM (Jesd8-9). This standard is divided into Class I and Class II. Multifunction I/O devices support two classes of the SSTL2 standard. This standard requires differential amplifier input buffers and push-pull output buffers.
CTT - Center Tap Termination The Center Tap Termination (CTT) standard is a 3.3V memory bus standard sponsored by Fujitsu (Jesd8-4). This standard requires differential amplifier input buffers and push-pull output buffers.
AGP-2X - Advanced Graphics Port The Intel AGP standard is a 3.3V Advanced Graphics Port 2x bus standard used with Pentium II processors for graphics applications. This standard requires push-pull output buffers and differential amplifier input buffers.
library symbols
The xilinx library contains an extensive list of symbols designed to support a wide variety of i/o features. Most of these symbols represent variants of the five general-purpose general-purpose I/O symbols:
8226 ; IBUF (input buffer)
• IBUFG (Global Clock Input Buffer)
• obuf (output buffer)
• OBUFT (Tri-State Output Buffer)
• IOBUF (input/output buffer)

Design Considerations Voltage Reference (V) Pins Refer to Low Voltage I/O Standards with Differential Amplifier Input Buffers that require an input voltage reference (VREF). Provides VREF as an external signal to the device.
The voltage reference signals are "lined" in a half-edge fashion within the device so that there are eight independent VREF arrangements inside all packages. See Figure 35 on page 32 for a representation of the I/O bank. Within each group, approximately one out of every six I/O pins is automatically configured as a VREF input.
Within each vref group, any input buffers that require a vref signal must be of the same type. Any type of output buffer and input buffer can be placed in the same VREF group without the need for a reference voltage.
Output drive source voltage (V) pin CCO
Many low-voltage i/o standards supported by multifunction i/o require different output drive source voltages (vcco). Therefore, each device must typically support multiple output drive source voltages.
The supply of VCCO is a number of packages bundled together internally. The VQ100 and PQ208 provide a combined VCCO power supply. Four independent VCCO supplies are available in the TQ144 and CS144 packages. The fg256 and fg456 provide eight independent vcco power supplies.
The output buffers in a given vcco library must share the same output drive source voltage. The input buffers of lvttl, lvcmos2, pci33_3 and pci 66_3 use the vcco voltage as the input vcco voltage.
Transmission Line Effects The delay of an electrical signal along a wire depends on the rise and fall times of the signal as it travels short distances. Transmission line delay varies with inductance and capacitance, but a well-designed board can experience about 180 ps of delay per inch.
Transmission line effects or reflections typically start at 1.5 inches for fast (1.5 ns) rise and fall times. Poor (or non-existent) termination or changes in transmission line impedance can cause these reflections and can cause additional delays in longer traces. As system speeds continue to increase, the impact of i/o latency can become a limiting factor, so transmission line termination becomes increasingly important.

Simultaneous Switching Guidelines High-speed digital integrated circuits can experience ground bounce when multiple outputs change states simultaneously, causing unwanted transient behavior of the outputs or internal logic. This problem is also known as the simultaneous switching output (sso) problem.
Ground bounce is primarily due to current changes in the combined inductance of the ground pins, bond wires, and ground metallization. After multiple outputs change state simultaneously, the IC's internal ground level deviates from the external system ground level for a short period of time (a few nanoseconds).
Ground bounce affects stable low outputs and all inputs because they interpret the input signal by comparing it to internal ground. If the ground bounce magnitude exceeds the actual instantaneous noise margin, the unchanged input can be interpreted as a short pulse of opposite polarity to the ground bounce.

Switching Characteristics Testing of switching parameters is modeled according to the test method specified in mil-m-38510/ 605 . All devices are 100% functionally tested. Internal timing parameters are obtained by measuring internal test patterns. Listed below are representative values. For more specific, precise, and worst-case guaranteed data, use the value reported by the static timing analyzer (trce in the Xilinx development system) and re-annotate it into the list of simulated nets. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Unless otherwise stated, this value applies to all Spartan II devices.