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Industry Standard Pinout 4.5-V to 18-V Operating Range 5-A peak sink/source at VDD=12V; 4.3-A sink/2.8-A source at VOUT=6V; TTL or CMOS input threshold selection Three versions Dual independent drivers: - Dual Invert + Enable (FAN3223) - Dual Non-Invert + Enable (FAN3224) - Dual Input (FAN3225) - Internal resistor shuts down driver if no input MillerDrive 8482 ; technology 12 ns/9 ns Typical rise/fall time (2.2-nf load); 20 ns typical propagation delay matched to another channel Dual current capability of 1ns parallel channel 8-lead 3x3 mm MLP or 8-lead SOIC package Ambient temperature from -40°C to +125°C Automotive Qualified to AEC-Q100 (Version F085)

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Software Itch Mode Power Efficient Mosfet Switch Synchronous Rectifier Circuit DC-DC Converter Motor Control Automotive Qualification System (F085 Version)

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The FAN3223-25 dual 4A gate driver family is designed to drive N-channel enhancement mode mosfet applications in low-side sw-itch applications to provide high peak current pulses in short sw intervals. The driver can select TTL or CMOS input thresholds. Internal circuitry provides an undervoltage lockout function by keeping the output low until the supply voltage is within the operating range. Additionally, the driver characteristics and the internal propagation delay between the A and B channels are timed for applications that require dual gate drivers, such as synchronous rectifiers. This also supports twice the current capacity of connecting TWO drivers in parallel to efficiently drive a single mosfet. The FA N322X driver contains the architecture of the final output stage of MillerDrive™. This bipolar mosfet combination minimizes switching losses at the miller platform level of the mosfet switch while providing rail-to-rail voltage switching and reverse current capability. The FAN3223 provides two inverting drivers and the fan3224 provides two non-inverting drivers. Each device has dual independent enable pins, which are open and unconnected by default. In the FA N3225, each channel has two inputs of opposite polarity, allowing S to be configured as non-inverting or inverting with an optional enable function using the second input. If one or both inputs are left unconnected, an internal resistor biases the input and output to be pulled low to keep the power off of the mosfet.

Application Information Input Thresholds: Each member of the FA N322X driver family includes two identical channel current ratings that can be used independently or a single current capacity in parallel. In FA N3223 and FA N3224, channels A and B can be enabled or disabled independently using ena or enb respectively. UK for thresholds with CMOS or TTL inputs. If ena and enb are not connected, internal pull-up resistors make the driver channel by default. ena and enb have ttl thresholds in parts with ttl or cmos inx thresholds. If the input and output of channel A and channel B are connected in parallel to increase the drive current capacity, connect ENA and ENB to switch together. The FA N322X series offers TTL or CMOS input thresholds. In the fan322xt, the input threshold meets the industry standard TTL logic threshold independent of the VDD voltage and the hysteresis voltage is approximately 0.4 V. Allows input logic to be driven from a range of inputs to account for signal level logic high at voltages over 2V. The drive signal for the TTL input should have fast rising and falling edges with a slew rate of 6 V/µs or faster, so the rise time from 0 to 3.3 V should be 550 ns or less. Reduced slew rate and circuit noise can cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, resulting in unstable operation. In the fan322xc, the logic input threshold depends on the VDD level, when VDD is 12V, the logic rising edge threshold is about 55% of VDD. The input falling edge threshold is approximately 38% of VDD. The CMOS input configuration provides a hysteresis voltage of approximately 17% of VDD. This CMOS input can use relatively slow edges (near DC) if good decoupling and bypassing techniques are included in the system design to prevent noise from corrupting the input voltage hysteresis window. This allows to pass in the control signal and the driver's latch. The slowly rising edge of the driver's pin is the control signal and the driver's output pin. The quiescent supply current generates a curve in IDD (static) typical performance characteristics with all inputs/floating (output) enabled) and indicates the test configuration.

For other states, additional current flows through the input and 100 kΩ resistors on the output shown as n in the block diagram of each section (see figure). In these cases, the actual quiescent idd current is the value obtained from the curve plus the additional current. MillerDrive™ Door Drive Technology The FA N322X door driver incorporates the MillerDrive™ architecture as shown. For the output stage, a combination of bipolar and MOS devices provides changes in supply voltage and temperature. Bipolar devices carry most of the current between 1/3 and 2/3 of the output switch vdd and mos devices pull the output high or low rail. The MillerDrive™ architecture is designed to act as an on/off process through the gate-to-drain capacitance mosfet in the miller plateau region. For the switching interval in the MOSFET, the driver provides high peak current for fast switching although the Miller plateau does not exist. This situation often occurs in synchronous rectifier applications because the body diode is usually switched on in the mosfet. The output pin slew rate is determined by the VDD voltage and the output load. It's not user adjustable, but if the current gets slower rise or fall times, you can increase the series resistance needed at the mosfet gate.

Undervoltage Lockout The FAN322X startup logic is optimized to drive the low voltage grounded N-channel mosfet lockout (uvlo) function, ensuring that the ic starts up in an orderly manner. When VDD rises, but falls below the uvlo level, the circuit maintains a low output regardless of the state of the input pins. When activating after that part, the supply voltage must be turned off in the part down. This hysteresis helps prevent chattering when low VDD supply voltages have itching from the power switch. This configuration is not suitable for driving a high-side p-channel mosfet because the output voltage of the driver will turn a mosfet with a p-channel power density below uvlo. VDD Bypass Capacitor Guidelines To make this IC turn on the device quickly, the local high frequency bypass capacitor, CBYP, low ESRESL should be connected at VDD and the ground pin with minimum trace length. This capacitor is typically a 47µF bias circuit on the driver and controller in addition to the bulk electrolytic capacitor, which is 10µF. A typical criterion for choosing the value of cbyp is to keep the ripple voltage on the VDD supply less than or equal to 5%. This usually reaches the load capacitance ceqv at a value greater than or equal to 20 times, defined here as qgate/vdd. A common choice for 0.1µf to 1µf or larger ceramic capacitors, such as X5R and with good temperature characteristics and high pulse current capability.

If circuit noise affects normal operation, CBYP can be increased to 50-100 times CEQV, or cbyp can be divided into tw-o capacitors. One should be a larger value based on the equivalent load capacitance, and another smaller value like 1-10nf mounted closest to the VDD and GND pins to carry the higher frequency content of the current pulse. This bypass capacitor has to supply from both driver channels, if the driver sw happens at the same time, the composite peak current from the CBYP ice should be as large as the W-hen one channel is sw-itching. Layout and Hookup Guidelines The FA N3223-25 series gate drivers include fast-reacting input circuitry, short propagation delays, and power stages capable of outputting current peaks in excess of 4 A to facilitate voltage transition times below 10 ns to over 150 ns. The following layout and hookup guidelines are strongly recommended: Keep high current output and power ground paths separate from logic and enable input signal and signal ground paths. It is especially important to handle TTL level logic threshold inputs and enable pins in the driver.

Keeping the driver as close to the load as possible minimizes the length of the high current trace. This reduces series inductance to improve high-speed switching itch while reducing EMI that can radiate to the driver input and surrounding circuitry. If the input of the channel is not connected externally, instruct the internal 100 kΩ resistor on the block diagram to command the low output. In noisy environments, it may be necessary to switch an unused channel to a short output switch to prevent noise from causing spurious traces. Many high-speed power circuits can be affected from their outputs or other external sources, possibly causing the output to retrigger. Test layouts with long input, enable, or output leads if the circuit is on a breadboard or non-optimal circuit. For best results, connect all pins as short and direct as possible. The Fan 322X is compatible with many other industry standard drivers. To enable the pin in a single input part, there is an internal 100 kΩ resistor connected to vdd to enable the driver by default; this should be considered in the PCB layout. On and off current paths should be minimized, as described in the next section. The diagram shows the pulsed gate drive current path when the gate driver provides the gate charge to turn the mosfet on. Current is provided locally by the bypass capacitor, CBYP, and S current through the driver mosfet gate and ground. To reach the peak possible peak current, resistive and inductive paths should be minimized. The localized cbyp behavior contains peak current pulses in the driver bank circuit, preventing them from interfering with sensitive analog circuits in the pwm controller.

The figure shows the current path of the gate driver to turn off the mosfet. Ideally, the driver shuns the current loop loop directly to the mosfet source. For fast turn-off times, resistance and inductance in this path are minimized. PWM VDD Volts

Logic Operation Truth Table The FAN3225 truth table indicates the operating state using a two-input configuration. In a non-inverted driver configuration, the in-pin should be a logic low signal. If the in-pin is connected to logic high, the disable function is implemented and the drive output remains low regardless of the state of the in+ pin.

Operating Waveform At power-up, the driver output remains low until the VDD voltage reaches the turn-on threshold. The amplitude of this output pulse rises with VDD until steady state VDD is reached. The operation shown in the irreversible diagram shows that the value remains low until the uvlo threshold is reached, then the output is in phase with the input.

For the inverted configuration of the graph, the startup waveform is as shown. Bind VDD to in+ and the input signal pulses applied to input and output are opposite to the input. In POWERUP, the inverting output remains low until the VDD voltage reaches the turn-on threshold, then the inverting input.