The A3955SB and A3955SLB are designed to drive one winding of a bipolar stepper motor in microstepping mode. The output is rated for a continuous output current of ±1.5 A and operates at 50 V. Internal pulse width modulation (PWM) current control combined with an internal three-bit nonlinear digital-to-analog converter allows motor current to be controlled in full-, half-, fourth-, or eight-order (microstep) mode. Nonlinear increments minimize the number of control lines required for microstepping. Microstepping provides higher step resolution and reduces torque variations and low speed resonance issues.

Internal circuitry determines whether the pwm current control circuit operates in slow (recirculating) current decay mode, fast (regenerative) current decay mode, or mixed current decay mode where the off time is divided into Fast current decay cycle, the remaining fixed off-time is used for slow current decay. A combination of user-selectable current sense resistors and reference voltages, digitally selectable output current ratios, and slow, fast or mixed current decay modes provide users with a wide, variable range of motor control. Internal circuit protection includes hysteretic thermal shutdown, TVS diode, and cross-current protection. No special power-up sequence is required.

A3955S - There are two power packs to choose from; A. 16-pin dual in-line plastic package with copper heatsink (suffix "b") and 16-pin plastic SOIC with copper heatsink (suffix "lb"). For both package types, the power label is at ground potential and electrical isolation is not required.

feature

±1.5 A continuous output current; 50 V output voltage rating; internal PWM current control; 3-bit nonlinear DAC; fast, mixed fast/slow and slow current decay modes; internal TVS diode; internal thermal shutdown circuit; cross-current and UVLO protection.

Function description

The windings of a bipolar stepper motor require two A3955S full-bridge PWM microstepper motor drivers. An internal pulse width modulation (pwm) control circuit regulates the current in each motor winding. The peak motor current is set by the value of the external current sense resistor (RS), the reference voltage (VREF), and the digital-to-analog converter (DAC) data inputs (d0, d1, and d2).

To improve motor performance, especially when using the sinusoidal current distribution required for microstepping, the A3955S has three different current decay modes: slow decay, fast decay and mixed decay.

Phase input. The phase input controls the direction of current flow in the load (Table 1). An internally generated dead time of approximately 1 microsecond prevents cross currents that can occur when switching phase inputs.

DAC data input (d0, d1, d2). The output current is digitally controlled using a nonlinear DAC. The output of the DAC is used to set the trigger point of the current sense comparator. Table 3 shows the DAC output voltage for each input condition. When d0, d1 and d2 are all logic low, all power output transistors are turned off.

Internal PWM current control. Each motor driver contains an internal fixed off-time pwm current control circuit that limits the load current to the desired value (itrip). Initially, a pair of diagonal source and sink transistors are enabled and current flows through the motor windings and RS (Figure 1). When the voltage on the sense resistor equals the DAC output voltage, the current sense comparator resets the PWM latch, turning off the source driver (slow decay mode) or the sink and source driver (fast decay mode or mixed decay mode) .

When the data input line is connected to VCC, by choosing RS and the transconductance function is approximated as: itrip≈vref/3rs vref.

Due to internal logic and switching delays, the actual peak load current (IPEAK) will be slightly higher than ITRIP. The driver remains off for a time period determined by a user-selected external resistor-capacitor combination (rtct). At the end of the fixed off time, the driver is re-enabled, allowing the load current to increase again to itrip, maintaining the average load current.

The DAC data input lines are used to provide up to 8 levels of output current. An internal 3-bit digital Toanalog converter reduces the reference input of the current sense comparator in precise steps (step-to-reference current ratio or SRCR) to provide half-step, quarter-step or "microstep" load current levels.

Slow current decay mode. When vpfd ≥ 3.5v, the device is in slow current decay mode (source driver is disabled when load current reaches itrip). During the fixed off time, the load inductance circulates current through the motor windings, receiver driver, ground clamp diode, and sense resistor (see Figure 1). Slow decay mode produces low ripple current for a given condition Figure 1 - Load current path with fixed off time (see Figure 2). Low ripple current is desirable because the average current in the motor windings is closer to the desired reference, improving the performance of the motor in microstepping applications.

For a given ripple current level, slow decay provides the lowest pwm frequency, which reduces heating in the motor and drive IC due to a corresponding reduction in hysteretic core losses and switching losses, respectively. Slow decay also has the advantage that the pwm load current regulation can follow a more rapidly increasing reference before the pwm frequency drops into the audible range. For these reasons, slow decay mode is usually used as long as good current regulation is maintained.

In some cases, slow decay mode PWM may not maintain good current regulation:

1) Load current will not be regulated in slow decay mode due to sufficiently negative back EMF voltage and low voltage drop across the load during slow decay recirculation. A negative back EMF voltage can cause the load current to actually increase during the slow decay time. When driving a stepper motor, a negative back-EMF voltage situation is usually present because the phase leads of the rotor typically cause the back-EMF voltage to be negative at the end of each step (see Figure 3A).

2) When the required load current drops rapidly, the slow rate of load current decay prevents the current from following the required reference value.

3) When the required load current is set to a very low value, the current control loop may not be adjustable due to its minimum duty cycle, which is the user-selected TOFF value and resets the PWM latch each time A function of the minimum on-time pulse width ton (min) that occurs when .

Fast current decay mode. When vpfd ≤ 0.8v, the device is in fast current decay mode (both sink and source drivers are disabled when the load current reaches itrip). During the fixed off time, the load inductance causes current to flow from ground to the load supply through the motor windings, ground clip, and flyback diode (see Figure 1). Since the entire motor supply voltage passes through the load during fast decay recirculation, the load current decays very quickly, producing high ripple currents for a given fixed off time (see Figure 2). This fast decay rate keeps good current regulation at the cost of reducing average current accuracy or increasing driver and motor losses.

Hybrid current decay mode. If vpfd is between 1.1v and 3.1v, the device will be in mixed current decay mode. The mixed decay mode allows the user to achieve good current regulation with minimal ripple current and motor/driver losses by selecting the minimum fast decay percentage required for their application (see also Stepper Motor Applications).

Like fast current decay mode, mixed decay begins by disabling the sink and source drivers after the load current reaches itrip. When the voltage on the RC terminal decays to a value below VPFD, the receiver driver is re-enabled, leaving the device in slow current decay mode for the remainder of the fixed off time (Figure 2). The percent fast decay (pfd) is determined by the user via vpfd or two external resistors.

As the toff value increases, the switching loss decreases, the low-level load current regulation improves, the emi decreases, the pwm frequency decreases, and the ripple current increases. The toff value can be chosen to optimize these parameters. For applications involving audible noise, a typical value of toff is chosen in the range of 15 μs to 35 μs.

In addition to determining the fixed turn-off time of the pwm control circuit, the ct component also sets the comparator blanking time. This feature will blank the output of the current sense comparator when the internal current control circuit (or the phase input, or when the device is enabled via the DAC data input) switches the output. The comparator output is shielded to prevent false overcurrent detection due to reverse recovery current of the clamp diode and/or switching transients related to distributed capacitance in the load.

During internal pwm operation, at the end of the toff time, the output of the comparator is masked and CT starts to be charged internally from about 0.22vcc.

fixed rest periods. An internal PWM current control circuit uses one trigger to control how long the driver remains off. The primary off-time toff depends on the choice of external resistor (rt) and capacitor (ct) connections from the rc timing terminal to ground. Over the range of CT=470 pF to 1500 pF and RT=12 kΩ to 100 kΩ, the off time is approximated by:

When the load current increases, but has not yet reached the sense current comparator threshold (itrip), the voltage on the rc terminal is about 0.6vcc. When ITRIP is reached, the PWM latch is reset by the current sense comparator and the voltage on the RC terminal will decay until it reaches approximately 0.22VCC. The pwm latch is then set, re-enabling the driver and allowing the load current to increase again. The pulse width modulation cycle repeats to maintain the peak load current at the desired value.

The current source is about 1 mA. The comparator output remains blank until the voltage on CT reaches approximately 0.6VCC. The blanking time tblank can be calculated as:

When the phase input transitions, CT is discharged to near ground during the crossover delay time (which exists to prevent the source and sink drivers from turning on at the same time). After the crossover delay, CT is charged by an internal current source of approximately 1 mA. The comparator output remains blank until the voltage on CT reaches approximately 0.6VCC.

Similarly, when the device is disabled, the CT is discharged to near ground through the DAC data input. When the device is re-enabled, the CT is charged by an internal current source of approximately 1 mA. The comparator output remains blank until the voltage on CT reaches approximately 0.6VCC. The blanking time tblank can be calculated as:

The minimum recommended value for CT is 470 pF ± 5%. This value ensures that the blanking time is sufficient to avoid false tripping of the comparator under normal operating conditions. To optimize load current regulation, this value of CT is recommended, and the value of RT can be adjusted to determine TOFF.

thermal factor. Thermal protection circuitry turns off all output transistors when the junction temperature reaches approximately +165°C. This is only used to protect the device from faults caused by excessive junction temperature and should not mean output short circuits are allowed. When the junction temperature drops to approximately +150°C, the output transistors are re-enabled.

Stepper motor applications. The A3955SB or A3955SLB are used to optimize the performance of microstepping/sine stepper motor drive applications (see Figures 4 and 5). When the load current increases, a slow current decay method is adopted to limit the switching loss of the driver and the iron loss of the motor. This also increases the maximum rate at which load current increases due to slow decay during toff (compared to fast decay). When the load current decreases, the mixed current decay mode is used to regulate the load current to the desired level. This prevents the back-EMF from smearing the current waveform of the stepper motor voltage (see Figure 3A).