feature

256-bit, 4-channel; end-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ; pin selectable SPI® or I2C® compatible interface; power on preset to midscale; two packet address decode pins AD0 and AD1 ; varistor mode temperature coefficient 30ppm/°C; voltage divider temperature coefficient 5ppm/°C; wide operating temperature range –40°C to +125°C; 10 V to 15 V single supply; ±5 V dual supply.

application

Mechanical Potentiometer Replacement; Optical Network Adjustment; Instrumentation: Gain, Offset Adjustment; Stereo Channel Audio Level Control; Automotive Electronics Adjustment; Programmable Power Supply; Programmable Filter, Delay, Time Constant; Line Impedance Matching; Low Resolution rate DAC/trimmer replacement; base station power amplifier biasing; sensor calibration.

General Instructions

The AD5263 is the industry's first quad 256-bit digital potentiometer with an optional digital interface. The device features the same electronic adjustment as a mechanical potentiometer or variable resistor, with higher resolution, solid-state reliability, and superior low temperature coefficient performance.

Each channel of the AD5263 provides a fully programmable resistance value between the A terminal and the wiper or between the B terminal and the wiper. The 20 kΩ, 50 kΩ, or 200 kΩ fixed AB terminal resistors have a nominal temperature coefficient of ±30 ppm/°C and a channel-to-channel matching tolerance of ±1%. Another key feature of this part is the ability to operate from +4.5 V to +15 V or ±5 V.

At power-up, wiper position programming is preset to mid-scale. After power up, the virtual reality wiper position is programmed by a 3-wire SPI or 2-wire IC compatible interface. In integrated circuit mode, additional programmable logic outputs allow users to drive digital loads, logic gates and analog switches in their systems.

The AD5263 is available in a narrow body, 24 lead TSSOP. All parts are guaranteed to operate over the automotive temperature range of -40°C to +125°C. For single or dual channel applications, see the AD5260/AD5280 or AD5262/AD5282 data sheets. 1 The terms digital potentiometer, virtual reality, and RDAC are used interchangeably.

operate

The AD5263 is a quad-channel, 256-bit, digitally controlled, variable resistance (VR) device. To program the VR setup, see the SPI Compatible Digital Interface (dis=0) section and the i2C Compatible Digital Interface (dis=1) section. The part has a built-in power-up preset that places the wipers in mid-scale at power-up, simplifying fault state recovery at power-up. Additionally, the shutdown (SHDN) pin of the AD5263 places the RDAC in a near-zero power consumption state where terminal A is open and wiper W is connected to terminal B, resulting in only leakage current consumption in the virtual reality configuration. During shutdown, the virtual reality latch setting will be maintained, or a new setting can be programmed. When the part returns from the closed state, the corresponding VR settings are applied to the RDAC.

Variable Resistor Programming

Rheostat operation

The nominal resistances of the RDAC between Terminal A and Terminal B are 20 kΩ, 50 kΩ, and 200 kΩ. The last two or three digits of the part number determine the nominal resistance value, for example, 20 kΩ=20; 50 kΩ=50; 200 kΩ=200. The nominal resistance (r) of the vr has 256 contact points through the wiper terminal and the b terminal. The 8 bits of data in the rdac latches are decoded to select one of 256 possible settings. Assuming a 20 kΩ part is used, the first connection of the wiper gets data 0x00 starting from the B terminal. Because of the wiper contact resistance of 60Ω, such a connection creates a minimum resistance of 2 x 60Ω between the W and B terminals. The second connection is the first tap point, corresponding to 198Ω for data 0x01 (r=r/256+r=78Ω+2×60Ω). The third connection is the next tap point of 276 (r=78Ω×2+2×60Ω) representing data 0x02, and so on. For each additional LSB data value, the wipers move up the resistor ladder until the last tap point reaches 20042Ω (R – 1 LSB + 2 × R). Figure 45 shows a simplified diagram of the equivalent RDAC circuit, where the last resistor string is not connected; therefore, the LSB of the nominal resistor at full scale is 1 less than the wiper resistor.

The general formula for determining the digitally programmed output resistance between the w and b terminals is:

Where:

D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register.

The R antibody is the end-to-end resistance.

RW is the wiper resistance generated by the energization resistance of an internal switch.

In summary, if R=20 kΩ and the A terminal is open, the RDAC latch code in Table 5 produces the corresponding output resistance R.

Table 5. Codes and corresponding R resistors

NOTE: There is a finite wiper resistance of 120Ω at zero scale conditions. In this state, care should be taken to limit the current between W and B to a maximum pulsed current of no more than 20 mA. Failure to do so may result in degradation or damage to the internal switch contacts.

Similar to the mechanical potentiometer, the RDAC resistor between the W wiper and terminal A also produces a digitally controlled complementary resistor R. When using these terminals, the B terminal can be opened. The resistance value that sets r starts at the maximum value of the resistance and decreases as the value of the data loaded in the latch increases. The general equation for this operation is:

If R = 20 kΩ and the B terminal is open, the RDAC latch code in Table 6 produces the corresponding output resistance R.

Table 6. Codes and corresponding R resistors

The typical distribution of end-to-end resistance r between channels is within ±1%. Equipment-to-equipment matching is process batch dependent and may vary by ±30%. Since the resistive element is processed using thin film technology, the variation of R with temperature has a very low temperature coefficient of 30ppm/°C. abab

Program Potentiometer Divider Voltage Output Operation

Digital potentiometers easily create voltage dividers at wiper-to-B and wiper-to-A proportional to the input voltages at terminals A and B. Unlike the polarity between V to V, which must be positive, if V is powered by a negative supply, the voltages between A to B, W to A, and W to B can be in either polarity.

If you ignore the effect of the wiper resistance on the approximation, connecting the A terminal to 5 V and the B terminal to ground will produce an output voltage from the wiper to B, starting at 0 V and ending at 1 LSB below 5 V. Each LSB step in voltage is equal to the voltage applied from the A terminal to the B terminal divided by 256 positions of the potential. Measure the voltage divider. Since the AD5263 can be powered by dual supplies, the general equation defining the output voltage v with respect to ground for any valid input voltage applied to terminal a and terminal b is:

Operation of the digital potentiometer in voltage divider mode results in more accurate overtemperature operation. Unlike the varistor mode, the output voltage is mainly determined by the ratio of the internal resistances r and r, rather than their absolute values; therefore, the temperature drift is reduced to 5ppm/°C.

Pin select digital interface

The AD5263 offers the flexibility of optional interfaces. SPI mode is turned on when the digital interface select (DIS) pin is tied low. IC mode is turned on when the DIS pin is tied high to the V supply.

SPI compatible 3-wire serial bus (dis=0)

The AD5263 contains a 3-wire SPI compatible digital interface (SDI, CS, and CLK). The 10-bit serial word must be loaded with address bits a1 and a0, followed by the data byte msb. The format of the word is shown in the Serial Data Word Format section and in the bitmap.

The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work fine. If a mechanical switch is used for product evaluation, it should be de-noised using a trigger or other suitable method. When CS is low, the clock loads data into the serial register on each positive clock edge (see Figure 40).

Table 7, AD5263 address decoding table

The data settings and data hold times in the specification table determine the effective timing requirements. The AD5263 uses a 10-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. Note that only the last 10 bits into the register are locked in the decoder. When cs goes high, it activates the address decoder and updates the corresponding channel according to Table 7.

During shutdown (SHDN), the serial data output (SDO) pin is forced to logic high to avoid power dissipation in external pull-up resistors. See Figure 46 for an equivalent SDO output circuit schematic.

Unlike the SHDN, the wipers stay at mid-scale when the part is taken out of reset and don't return to their pre-reset setting.

Daisy Chain Operation

The Serial Data Out (SDO) pin contains an open-drain N-channel FET. This output requires a pull-up resistor in order to transfer data to the SDI pin of the next package. This allows several RDACs to be daisy-chained from a single-processor serial data line. The pull-up resistor termination voltage can be greater than the V supply voltage. It is recommended to increase the clock period when using pull-up resistors on the sdi pins of the following devices, as capacitive loading at the daisy-chain nodes (sdo to sdi) between devices may cause time delays for subsequent devices. Users should be aware of this potential problem in order to successfully implement data transfers (see Figure 47). If two AD5263s are daisy-chained, a total of 20 bits of data are required. The first 10 bits conform to the format shown in the Serial Data Word Format section and bitmap, go to u2, the last 10 bits are in the same format, go to u1. All 20-bit DDs go into their respective serial registers. After this, pull CS high to complete the operation and load the RDAC latch. Data appears on SDO on the negative edge of the clock, making it available to the input of the daisy-chained device on the next rising edge of the clock.

IC-compatible 2-wire serial bus (dis=1) In IC-compatible mode, the RDAC is connected to the bus as a slave device. Referring to the bitmap in the IC Compatible Digital Interface (dis=1) section, the first byte of the AD5263 is the slave address byte, consisting of 7 bits of slave address and R/W bits. The five msbs are 01011, the next two bits are determined by the state of the device's ad0 and ad1 pins. AD0 and AD1 allow the user to place up to four ICCompatible devices on a single bus. The 2-wire IC serial bus protocol operates as follows.

1. The host initiates a data transfer by establishing a start condition, a high-to-low transition on the SDA line when SCL is high (see Figure 43). The following bytes are the slave address byte, consisting of 7 bits of the slave address and one R/W bit. This r/w bit determines whether data is read from or written to the slave device.

The slave whose address corresponds to the transmit address responds by pulling the sda line low during the ninth clock pulse (this is called the acknowledge bit). During this phase, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial registers. If the r/w bit is high, the master reads from the slave. If the r/w bit is low, the master writes to the slave.

2. In write mode, the second byte is the instruction byte. The first bit (msb) of the instruction byte is a don't care byte. The following two bits (labeled A1 and A0) are the RDAC subaddress selection bits.

The fourth msb(rs) is the midscale reset. A logic high on this bit moves the wiper of the selected channel to the center tap, where rwa = rwb. This function effectively rewrites the contents of the registers so that the RDAC remains at midscale when exiting reset mode.

The fifth msb (sd) is the off bit. A logic high causes the selected channel to be open at terminal A when the wiper is shorted to terminal B. This operation produces almost 0Ω in rheostat mode and almost 0 V in potentiometer mode. This sd bit has the same function as the shdn pin, except that the shdn pin responds to active low. Also, the shdn pin affects all channels, while the sd bit only affects the channel being written to. It should be noted that the shutdown operation does not interfere with the contents of the registers. When resuming from a shutdown state, the previous settings will be applied to the RDAC.

The next two digits are O2 and O1. They are additional programmable logic outputs that can be used to drive other digital loads, logic gates, LED drivers, analog switches, and more. The LSB is a don't care bit (see the bitmap in the IC Write Mode Data Word Format section).

After acknowledging the command byte, the last byte in the write mode is the data byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (8 data bits followed by an acknowledge bit). A transition on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 43).

3. In read mode, the data byte follows the acknowledgment of the slave address byte. Data is transferred over the serial bus in a sequence of 9 clock pulses (slightly different from write mode, where there are 8 data bits followed by an acknowledge bit). Likewise, transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 44). Note that the channel of interest is the channel previously selected in write mode. If the user needs to read the RDAC value of both channels, the first channel must be programmed to write mode and then changed to read mode to read the first channel value. Afterwards, they must switch back to write mode with the second channel selected, and read the second channel value again in read mode. The user does not need to issue frame 3 data bytes in write mode for subsequent readback operations. The programming format is shown in Figure 44.

4. After reading or writing all data bits, the master will establish a stop condition. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition (see Figure 43). In read mode, the master responds with a no to the ninth clock pulse (ie the sda line is held high). Then, before the tenth clock pulse, the master pulls the SDA line low, which goes high to establish a stop condition (see Figure 44).

The Repeat Write feature gives the user the flexibility to update the RDAC output multiple times after only addressing and indicating the part once. For example, after the RDAC acknowledges its slave address and instruction byte in write mode, the RDAC output is updated on each successive byte. If a different instruction is required, the write/read mode must start over with a new slave address, instruction and data bytes. Likewise, the repeated read function of rdac is also allowed.

Additional programmable logic outputs

The AD5263 has additional programmable logic outputs O1 and O2 that can be used to drive digital loads, analog switches, and logic gates. O1 and O2 default to logic 0. The voltage level can swing from GND to V. The logic states of O1 and O2 can be programmed in frame 2 in write mode (see Figure 43). These logic outputs have enough current drive capability to handle milliamp loads.

Users can also activate O1 and O2 in three different ways without affecting the wiper settings. They can do the following:

(1) Start, from the address byte, confirm, specify the instruction bytes of O1 and O2, confirm, stop.

(2), complete the write cycle, stop, then start, from the address byte, confirm, specify the instruction bytes of O1 and O2, confirm, stop.

(3) Do not complete the write cycle by not issuing stop, then start, slave address byte, acknowledge, and the instruction byte specifies O1 and O2, acknowledge, stop.

Independent shutdown function

Shutdown can be activated by swiping on the SHDN pin or by programming the SD bit in the write mode command byte. In addition, shutdown can even be achieved through the digital output of the device, as shown in Figure 48. In this configuration, the device is turned off during power up, but the user is allowed to program the device. Therefore, when O1 is programmed high, the device exits shutdown mode and responds to the new setting. This independent shutdown function allows absolute shutdown during power-up, which is critical in hazardous environments, without adding additional components.

If using the SD bit to enable the shutdown feature, see the IC Write Mode Data Word Format section. Tables 8 and 9 show the sequences that can put any channel into an undesired off state.

Multiple devices on a bus

Figure 49 shows four AD5263 devices on the same serial bus. Each has a different slave address because of the different states of their AD0 and AD1 pins. This allows each RDAC in each device to be independently written to or read from. The master output bus driver is an open-drain, pull-down interface in a fully IC-compatible interface.

Level Shift for Negative Voltage Operation

Digital potentiometers are popular in laser diode drivers and some telecom equipment level setting applications. These applications sometimes operate between ground voltage and some negative supply voltage so that the system can be biased on a circle to avoid large bypass capacitors that can severely hinder AC performance. Like most digital potentiometers, the AD5263 can be configured with a negative supply (see Figure 50).

However, the digital inputs must also be level shifted to allow proper operation, since ground is referenced to a negative potential. As a result, Figure 51 shows an implementation with a few transistors and a few resistors. When v is high, q1 is turned on and its emitter is clamped one threshold above ground. This threshold occurs at the bottom of q2, which causes q2 to close. In this state, V is close to -5 V. When V is low, Q1 is turned off and the bottom of Q2 is pulled low, causing Q2 to turn on. In this state, V is close to 0 V. Note that an appropriate time offset is also required to successfully communicate with the device.

ESD protection

All digital inputs are protected with series input resistors and parallel Zener ESD structures, as shown in Figure 53.

Thorium IS protection applies to digital input pins SDI/SDA, CLK/SCL, CS/AD0, RES/AD1, and SHDN.

Terminal voltage operating range

The AD5263 positive V and negative V supplies define the boundary conditions for proper operation of the 3-terminal digital potentiometer. Supply signals in excess of V or V appearing on the A, B, and W terminals are clamped by the internal forward-biased diodes shown in Figure 54.

power-on sequence

Since ESD protection diodes limit voltage compliance at the A, B, and W terminals (see Figure 54), it is important to power V and V before applying any voltage to the A, B, and W terminals; otherwise, the diodes will be forward biased so that V and V are inadvertently powered up, possibly affecting the rest of the circuit. The ideal power-up sequence is as follows: GND, V, V, V, digital input, and V. The relative order of V, V, V, and digital inputs does not matter as long as power is applied after V and V.

V Power Logic

The AD5263 is capable of operating at higher voltages than internal logic levels, which are limited to 5 V operation. Therefore, V always needs to be connected to a separate 2.7 V to 5.5 V supply to ensure proper digital signal levels. Logic levels must be limited to V regardless of V. Also, V should always be less than or equal to V.

Layout and Power Bypass

It is good practice to design a layout with a compact, minimum lead length. Wires to the input should be as direct as possible with minimal wire length. The ground path should have low resistance and low inductance.

Also, for best stability, it is a good practice to bypass the power supply with a high quality capacitor. A 0.01µf to 0.1µf ceramic disk or chip capacitor should be used to bypass the device's power supply lines. A low ESR 1µF to 10µF tantalum or electrolytic capacitor should also be used at the power supply to minimize any transients and low frequency fluctuations (see Figure 55). Note that the digital ground should also be remotely connected to a point on the analog ground to minimize ground bounce.

RDAC circuit simulation model

Internal parasitic capacitance and external capacitive loading control the AC characteristics of the RDAC. The –3 dB bandwidth of the AD5263 (20 kΩ resistor) is configured as a potentiometric divider, measuring 300 kHz at half scale. Figure 22 provides the large-signal Bode plot characteristics for the three available resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. The parasitic simulation model is shown in Figure 56. The following code provides a macromodel netlist for a 20 kΩ RDAC.

application information

Dual Power Bipolar DC or AC Operation

The AD5263 can be operated with dual power supplies, allowing control of ground referenced AC signals or bipolar operation. AC signals up to V/V can be directly applied to DD SS terminal A to terminal B, and the output is taken from terminal W.

Gain Control Compensation

Digital potentiometers are often used for gain control, such as the non-rotating gain amplifier shown in Figure 58.

Note: The RDAC B terminal parasitic capacitance is connected to the op amp non-converting node. It introduces a zero for the 1/β term, with +20db/dec, while a typical op-amp gbp has a -20db/dec characteristic. A large r2 and limited c1 can make the frequency of this zero much lower than the crossover frequency. Therefore, at the crossover frequency, the closing rate becomes 40db/dec and the system has 0 phase margin. If the input is a rectangular pulse or step function, the output may ring or oscillate. Similarly, it may also ring when switching between two gain values, as this is equivalent to a step change at the input. o°

Depending on the op amp gbp, reducing the feedback resistor can extend the frequency of the zero enough to overcome the problem. A better approach is to include compensation capacitor c2 to remove the effect caused by c1. The best compensation occurs when r1×c1=r2×c2. This is not an option because of the R2 change. Therefore, one can use the relationship described and scale c2 to be the maximum value of r2. Doing so may overcompensate and affect performance slightly when r2 is set to a low value. However, in the worst case, it avoids gain peaking, ringing or oscillation. For critical applications, C2 should be found empirically to meet the needs. In general, c2 in the range of a few pf to no more than a few tenths of a pf is usually sufficient to compensate. Similarly, there are w and a terminal capacitors connected to the output (not shown); fortunately, they have less effect at this node and compensation can be ignored in most cases.

Programmable Voltage Reference

For voltage divider mode operation (Figure 59), the output of the digital potentiometer is normally buffered unless the load is much greater than R. Buffering is not only used for impedance conversion, but also allows heavier loads to be driven.

Bit Bipolar DAC

Figure 60 shows a low-cost 8-bit bipolar DAC. It offers the same adjustable number of steps as a traditional dac, but with less precision. Linearity and temperature coefficient, especially at low value codes, can be skewed by the wiper resistance of the digital potentiometer. The output of this circuit is:

Bipolar Programmable Gain Amplifier

For applications requiring bipolar gain, Figure 61 shows an implementation similar to the previous circuit. Digital potentiometer U1 sets the adjustment range. Therefore, for a given U2 setting, the wiper voltage at W2 can be programmed to be between V and –KV. Configuring A2 in non-vertical mode allows linear gain and attenuation. The transfer function is:

where k is the ratio of r/r set by u1.

Similar to the previous example, in the simpler (and more common) case of k=1, using a single channel, replace u1 with a matched pair of resistors to apply v and –v at the ends of the digital potentiometer. The relationship becomes:

If r2 is large, a compensation capacitor of several pf may be required to avoid any gain peaking.

Programmable Voltage Source

Increase production

For applications that require high current regulation, such as laser diode drivers or tunable lasers, a boost power supply can be considered. See Figure 62.

In this circuit, the inverting input of the op amp forces V to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the power supply through the n-channel fet, n1. The n1 power handling must be sufficient to dissipate power equal to (vv)×i. This circuit can supply up to 100mA from a 5v supply. For precision applications, a voltage reference such as adr421 or adr03 can be applied to the a terminal of a digital potentiometer.

Programmable 4 to 20 mA current source

A programmable 4-20 mA current source can be implemented with the circuit shown in Figure 63. The REF191 is a unique low supply headroom and high current handling accuracy reference that outputs 20mA at +2.048V. The load current is simply the voltage between terminals B and W of the digital potentiometer divided by R:

The circuit is simple, but there are two things to watch out for. First, a dual-supply op amp is ideal because the ground potential of the REF191 can swing from -2.048 V at zero scale to V at full scale set by the potentiometer. Although the circuit operates on a single power supply, the programmable resolution of the system is reduced.

For applications requiring higher current capability, a few modifications to the circuit in Figure 63 can produce adjustable currents in the hundreds of milliamps range. First, the voltage reference needs to be replaced with a high-current, low-loss regulator, such as the AD3333, and the op amp needs to be replaced with a high-current, dual-supply mode, such as the AD5263. Depending on the desired current range, an appropriate value for r must be calculated. Because of the high current flowing to the load, the user must be careful about the load impedance so as not to drive the op amp past the positive rail.

Programmable Bidirectional Current Source

For applications requiring bidirectional current control or higher voltage compliance, a Howland current pump can be used (see Figure 64). If the resistors are matched, the load current is:

In theory, r2b can be as small as needed to achieve the desired current within the output current drive capability of a2. In this circuit, the op2177 can output a voltage of ±5ma in any direction, and the voltage compliance is close to +15v, indicating that the output impedance is:

If resistors r1' and r2' are precisely matched to r1 and r2a+r2b, respectively, the output impedance is infinite. On the other hand, if the resistors don't match, it could be negative. Therefore, c1 in the range of 1 pf to 10 pf is required to prevent oscillation.

Programmable Low Pass Filter

In analog-to-digital conversion applications, anti-aliasing filters are often included to limit the frequency band of the sampled signal. A two-channel digital potentiometer can be used to construct a second-order Sallen key low-pass filter (see Figure 65). The design formula is as follows:

The user can start by choosing some convenient values for the capacitors. To achieve the maximum flat bandwidth at Q=0.707, set C1 to twice the size of C2 and set R1 to R2. As a result, the user can tune r1 and r2 to the same setting to obtain the desired bandwidth.

programmable oscillator

In a classic wien bridge oscillator (Figure 66), the wien network (r, r', c, c') provides positive feedback, while r1 and r2 provide negative feedback. At the resonant frequency f, the total phase shift is zero and the positive feedback causes the circuit to oscillate.

When r=r′, c=c′, r2=r2a (r2b+r), when resonating, set:

Balance the bridge. In practice, r2/r1 should be set to be slightly larger than 2 to ensure oscillations can start. On the other hand, the alternate conduction of diodes d1 and d2 ensures that r2/r1 is less than 2 momentarily, thereby stabilizing oscillation.

Once the frequency is set, the oscillation amplitude can be tuned by r2b because:

v, i and vare are interdependent variables. By appropriately choosing r2b, a balance of v convergence is achieved. R2b can be placed in series with a discrete resistor to increase the amplitude, but the total resistance should not be so large that it saturates the output.

Resistance scale

The AD5263 is available in nominal resistances of 20 kΩ, 50 kΩ, and 200 kΩ. Users who require lower resistance and the same number of step adjustments can place multiple devices in parallel. For example, Figure 67 shows a simple scheme using two channels in parallel. In order to linearly adjust half the resistance in each step, the user needs to program both channels to the same setting.

Available in voltage divider mode only, a proportionally lower voltage appears at terminal A by connecting discrete resistors in parallel, as shown in Figure 68. This translates to finer accuracy because the step size at terminal W is smaller.

The voltage can be found as:

Figure 67 and Figure 68 show the application of the linear change of the digital potentiometer. On the other hand, logarithmic taper adjustment is often the preferred application, such as volume control. Figure 69 shows an alternative resistance scaling method that produces a pseudo log taper output. In this circuit, the smaller the value of r2 relative to r, the closer the output is to logarithmic behavior.

Resistor Tolerance, Drift, and Temperature Coefficient Mismatch Considerations

In rheostat mode, like the gain control circuit in Figure 70, the tolerance mismatch between the digital potentiometer and the discrete resistors can cause repeatability problems between different systems. Due to the inherent matching of the silicon process, the use of multi-channel devices in this application is feasible. Therefore, R1 should be replaced with one channel of the digital potentiometer. r1 should be programmed to a specific value and r2 can be used for adjustable gain. While adding cost, this approach minimizes the tolerance and temperature coefficient mismatch between r1 and r2. In addition, this method tracks drag drift over time. Therefore, these non-ideal parameters are less sensitive to system changes.

NOTE: The circuit in Figure 71 can also be used to track tolerances, temperature coefficients, and drift in this particular application. However, the properties of the transfer function change from linear to a pseudo-logarithmic gain function.