These devices combine four popular functions, power-on reset control, watchdog timer, supply voltage monitoring, and block lock to protect serial eeprom memory in one package. This combination reduces system cost, reduces board space requirements, and improves reliability.
Applying power to the device activates the power-on reset circuit, which keeps reset/reset active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code.
The watchdog timer provides an independent protection mechanism for the microcontroller. The device activates a reset/reset signal when the microcontroller fails to restart the timer within a selectable timeout interval. The user selects the interval from three preset values. Once selected, the interval does not change even after cycling power.
The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. Reset/Reset is asserted until VCC returns to the correct operating level and stabilizes. Four industry-standard vtrip thresholds are available, however, intersil's unique circuitry allows the thresholds to be reprogrammed to meet custom requirements or fine-tune thresholds for applications requiring greater accuracy.
The memory portion of the device is a cmos serial eeprom array with intersil block lock protection. The array is internally organized as 512 x 8. The device has a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil's proprietary Direct Write unit, offering a duration of at least 100,000 cycles and data retention of at least 100 years. Jie X5043 , X5045

Feature low VCC detection and reset assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Reprogram the low VCC reset threshold voltage using a special programming sequence.
- The reset signal is valid for VCC=1V
Selectable timeout watchdog timer for long battery life and low power consumption
-<50µA maximum standby current, watchdog on -<10µA maximum standby current, watchdog off
4-bit EEPROM – 1m write cycle to store critical data with Block Lock memory
- Protects 1/4, 1/2, all or no built-in accidental write protection of EEPROM array
- Write enable latch
- Write protect pin
SPI interface - 3.3MHz clock frequency minimizes programming time
- 16-byte page write mode
- 5ms write cycle time (typical)
Available packages
- 8 ld MSOP, 8 ld SOIC, 8 ld PDIP
- 14 Ld TSSOP
Lead-free plus annealed (RoHS compliant) available
application communication equipment
- Routers, hubs, switches
- STB Industrial System - Process Control
-Intelligent meter computer system
- desktop computer
- Network server battery powered equipment

typical application

block diagram

Pin Description Serial Output (SO)
The same goes for push/pull serial data output pins. During a read cycle, data is shifted on this pin. Data is clocked by the falling edge of the serial clock.
Serial Input (SI)
Si is the serial data input pin. All opcodes, byte addresses and data to be written to memory are input on this pin. Data is latched on the rising edge of the serial clock. Serial Clock (SCK)
The serial clock controls the serial bus timing of data input and output. The opcode, address or data on the si pin is latched on the rising edge of the clock input, while the data on the so pin changes after the falling edge of the clock input.
Chip Select (CS/WDI)
When CS is high, the x5043, x5045 are deselected, the SO output pins are in high impedance, and, unless an internal write operation is in progress, the x5043, x5045 will be in standby power mode. CS LOW enables X5043, X5045 to be in active power mode. It is important to note that after power up, a high-to-low transition on CS is required before any operation can begin.
Write Protect (wp)
Non-volatile writes to x5043, x5045 are disabled when wp is low, but the part works fine otherwise. When wp is held high, all functions (including non-volatile writes) work correctly. While cs is still low, wp going low will interrupt writes to x5043, x5045. If the internal write loop has started, wp going low has no effect on writes.
reset (reset, reset)
x5043, x5045, reset/reset is an active low/high, open drain output that activates whenever VCC falls below the minimum VCC detect level. It will remain active until VCC rises 200ms above the minimum VCC detection level. If the watchdog timer is enabled, the reset/reset will also activate and CS remains above or below the watchdog timeout period. A falling edge of CS will reset the watchdog timer.

Operating principle Power-on reset power on X5043, X5045, start power-on reset circuit. This circuit makes the reset/reset pin active. Reset/Reset prevents the system microprocessor from starting to operate until the voltage is insufficient or the oscillator is stable. When VCC exceeds the device
VTRIP V value 200 ms (nominal) circuit releases reset/reset, allowing the processor to begin executing code.
Low Voltage Monitoring During operation, the X5043, X5045 monitor the VCC level and assert a reset/reset if the supply voltage falls below a preset minimum VTRIP. The reset/reset signal prevents the microprocessor from operating in a power-down or power-down state. The reset/reset signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP by 200ms.
Watchdog Timer The watchdog timer circuit monitors the activity of the microprocessor by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent the reset/reset signal from being activated. The CS/WDI pin must be toggled from high to low before the watchdog timeout period expires. The state of two nonvolatile control bits in the status register determines the period of the watchdog timer. The microprocessor can change these watchdog bits. In the absence of microprocessor action, the watchdog timer control bits remain unchanged, even in the event of a complete power-down. X5043 and X5045 are shipped with standard VCC threshold (VTRIP) voltage. This value does not change under normal operating and storage conditions. However, in applications where the standard vtrips are not exactly correct, or if the vtrip values require more precision, the x5043, x5045 thresholds can be adjusted. The procedure is described below and uses the application of the high voltage control signal. V
Set the vtrip voltage This step is used to set the vtrip to a higher voltage value. For example, if the current vtrip is 4.4v and the new vtrip is 4.6v, this process will directly make the change. If the new setting is to be lower than the current setting, the trigger point needs to be reset before setting the new value.
To set the new vtrip voltage, apply the desired vtrip threshold voltage to the vcc pin and connect the wp pin to the programming voltage vp. Then send a wren command, then write data 00h to address 01h.cs
A write operation high initiates the vtrip programming sequence. Turn wp down to finish.
Note: This operation also writes 00h to the array address 01h.
Reset the vtrip voltage This step is used to set the vtrip to the "native" voltage level. For example, if the current vtrip is 4.4v and the new vtrip must be 4.0v, the vtrip must be reset. When VTRIP is reset, the new VTRIP is below 1.7V. This step must be used to set the voltage to a lower value.
To reset the VRIP voltage, apply at least 3V to the VCC pin and connect the WP pin to the programming voltage VP. Then send a wren command, then write data 00h to address 03h. cs goes high during a write operation, initiating the vtrip programming sequence. Turn wp down to finish.