Platform Features in System Programmable Configuration Proms In-system Programmable Proms for configuring Xilinx FPGAs Low-power advanced CMOS NOR flash process withstands 20,000 program/erase cycles Over full industrial temperature range (–40°C to +85°C °C) Supports programming, prototyping IEEE Std 1149.1 /1532 Boundary Scan (JTAG) and testing The jtag command enables standard fpga configurations Can be cascaded to store longer or multiple bitstreams Dedicated Boundary Scan (jtag) i /o power supply (vccj) i/o pin 8226 compatible with 1.5v to 3.3v voltage classes; design support using xilinx alliance ise and foundation ise series packages
XCF01S /XCF02S/XCF04S - 3.3V supply voltage - Serial FPGA configuration interface (up to 33 MHz) - Available in small VO20 and VOG20 packages. XCF08P/XCF16P/XCF32P - 1.8V supply voltage - Serial or parallel FPGA configuration interface (up to 33 MHz) - Available for small VO48, VOG48, FS48, fsg48 packages - Design revision technology to support storage and access to multiple Design revision to configure built-in data decompressor compatible with xilinx advanced compression technology

Introduced the in-system programmable configuration proms of xilinx platform flash series. Available in densities from 1 to 32 megabits (mbits), these proms provide an easy-to-use, cost-effective and reprogrammable method for storing large Xilinx-FPGA configuration bitstreams. Platform flash prom series includes 3.3v xcfxs prom and 1.8v xcfxxp prom. xcfxs version package 4-mbit, 2-mbit and 1-mbit prom
Master serial and slave serial fpga configuration modes are supported. The xcfxxp versions include 32mbit, 16mbit and 8mbit proms which support master serial, slave serial, master select mapped and slave select mapped fpga configuration modes

xcfxs platform flash prom block diagram

xcfxp platform flash prom block diagram

When the FPGA is in master serial mode, it generates a configuration clock that drives the prom. With CF high, a short access time after CE and OE are enabled, data is available on the PROM data (D0) pin, which is connected to the FPGA DIN pin. New data is available within a short access time after each rising clock edge. The fpga generates the appropriate number of clock pulses to complete the configuration. When the fpga is in slave serial mode, both the prom and the fpga are clocked by an external clock source, or alternatively, for the xcfxxp prom only, the prom can be used to drive the fpga's configuration clock. The xcfxxp version of the platform flash prom also supports master select map and slave select map (or slave parallel) FPGA configuration modes. When the fpga is in master selectmap mode, the fpga generates a configuration clock that drives the prom. When the fpga is in slave selectmap mode, the external oscillator generates the configuration clock that drives the prom and the fpga, or alternatively, the xcfxxp prom can be used to drive the fpga's configuration clock. Busy CF high, data available on PROMS data (D0-D7) pins after CE and OE are enabled. New data is available within a short access time after each rising clock edge. Data is clocked into the fpga on the next rising edge of cclk. A free-running oscillator can be used in slave parallel/slave selecmap mode. Additional advanced features are provided by the xcfxxp version of the platform flash prom. The built-in data decompressor supports the use of compressed prom files, while design revisions allow multiple design revisions to be stored on a single prom or across multiple proms. For design revisions, external pins or internal control bits are used to select the active design revision. Multiplatform flash prom devices can be cascaded to support larger profiles required when targeting larger FPGA devices or targeting multiple FPGAs chained together. When using advanced features of the xcfxxp platform flash prom (such as design modification), programming files spanning cascaded prom devices can only be created for cascaded chains that contain only the xcfxxp prom. If the advanced xcfxp feature is not enabled, the cascade chain can contain both xcfxxp and xcfxs prom. Platform Flash PROMs are compatible with all existing FPGA device families.

System programming in system programmable proms can be programmed individually, or two or more can be daisy-chained together and programmed in-system through the standard 4-pin jtag protocol, as shown in Figure 3. In-system programming provides fast and efficient design iteration and eliminates unnecessary packet processing or device plugging. This uses xilinx impact software and a xilinx download cable, a third-party jtag development system, a jtag compatible board tester, or a simple microprocessor interface that emulates a jtag instruction sequence to transfer the sequence of programming data to the device. The IMPACT software also outputs Serial Vector Format (SVF) files for use in any tool that accepts the SVF format, including automated test equipment. During system programming, the output of the ceo is driven high. During in-system programming, all other outputs remain in a high-impedance state or at clamped levels. In-system programming is fully supported within the recommended operating voltage and temperature ranges.

The 1/2/4 mbit xcfxs platform flash proms in the oe/reset system programming algorithm cause an internal device reset to be issued, causing the oe/reset pulse to be low.
Externally programmed xilinx reprogrammable proms can also be programmed by xilinx multiprocessor desktop tools or third-party device programmers. This provides the added flexibility of using pre-programmed devices and an in-system programmable option for future enhancements and design changes.
Reliability and Durability in System Programmable Products Xilinx offers a guaranteed durability level of 20,000 in system program/erase cycles with a minimum data retention period of 20 years. Each device complies with all functional, performance and data retention specifications within this duration limit.
Design security The xilinx in-system programmable platform flash prom device adopts advanced data security features to fully protect the fpga programming data from being illegally read by jtag. xcfxp proms can also be pro programmed to prevent accidental writes via jtag. Tables 4 and 5 show the security settings available for the xcfxxs prom and the xcfxxp prom, respectively.
Read Protection The user can set the read protection security bit to prevent the internal programming mode from being read or copied by the jtag. Read protection does not block write operations. For xcfxs prom, the read-protect security bit will be set for the entire device, and resetting the read-protect security bit requires erasing the entire device. For the xcfxxp prom, the read protection security bits can be set for individual design revisions, resetting the read protection bits requires removal of the specific design revision.
The write-protected xcfxp prom device also allows the user to write-protect (or lock) a specific design version to prevent accidental deletion or program manipulation. Once set, the write-protect security bit for a single design version must be reset (using the unlock command and the isc_erase command) before performing an erase or program operation. The IEEE 1149.1 Boundary Scan (JTAG) platform flash prom family is system programming compatible with IEEE Standard 1532 and fully compliant with IEEE Standard 1149.1 Boundary Scan (also known as JTAG), which is a subset of IEEE Standard 1532 Boundary Scan. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many optional instructions specified by the IEEE1149.1 standard. In addition, the jtag interface is used to implement in-system programming (ISP) to facilitate configure, erase and verify operations on the platform flash prom device. Table 6 lists the required and optional boundary scan instructions supported by the platform flash proms. Refer to the IEEE Standard 1149.1 specification for a complete description of the boundary scan architecture and required and optional specifications.
The instruction register (ir) of the instruction register platform flash prom is connected between tdi and tdo during the instruction scan sequence. In preparation for an instruction scan sequence, instruction registers are loaded in parallel in a fixed instruction capture mode. This mode moves to TDO (LSB) first, and the instruction moves from TDI to the instruction register.
xcfxs instruction register (8 bits wide) The instruction register (ir) of the xcfxs prom is 8 bits wide and is connected between tdi and tdo during the instruction scan sequence. The detailed composition of the instruction capture mode is shown in Figure 4. Instruction capture modes shifted out of the xcfxs device include ir[7:0]. ir[7:5] are reserved bits, set to logic "0". The ISC Status field ir[4] contains a logic "1" if the device is currently in System Configuration (ISC) mode; otherwise, it contains a logic "0". The security field ir[3] contains a logic "1" if the device has been programmed with the security option turned on; otherwise, it contains a logic "0". ir[2] is unused and set to "0". The remaining bits ir[1:0] are set to "01" as defined by IEEE Standard 1149.1. xcfxxp instruction register (16 bits wide) The instruction register (ir) of the xcfxxp prom is 16 bits wide and is connected between tdi and tdo during the instruction scan sequence. The detailed composition of the instruction capture mode is shown in Figure 5. Instruction capture modes shifted out of the xcfxp device include ir[15:0]. ir[15:9] are reserved bits, set to logic "0". The isc error field ir[8:7] contains "10" when the isc operation succeeds; otherwise it contains "01" when the in-system configuration (isc) operation fails. The Erase/Program (er/prog) error field ir[6:5] contains "10" when the Erase or Program operation is successful and "01" when the Erase or Program operation fails. The Erase/Program (ER/PROG) status field ir[4] contains a logic "1" when the device is busy performing an erase or program operation; otherwise, it contains a logic "0". The ISC Status field ir[3] contains a logic "1" if the device is currently in System Configuration (ISC) mode; otherwise, it contains a logic "0". The "Done" field ir[2] contains a logic "1" if the sample design version has been successfully programmed; otherwise, a logic "0" indicates that the programming was not completed. The remaining bits ir[1:0] are set to '01' as defined by IEEE Standard 1149.1.

Boundary Scan Registers Boundary scan registers are used to control and observe the state of device pins during extest, sample/preload, and clamp instructions. Each output pin on the platform flash prom has two register stages that constitute boundary scan registers, while each input pin has only one register stage. There are a total of three register levels for bidirectional pins, which form boundary scan registers. For each output pin, the register is closest to TDI's stage control and observes the output state, and the second stage closest to TDO controls and observes the output pin's high-Z enable state. For each input pin, a single register level controls and observes the input state of the pin. Bidirectional pins combine these three bits, first the input stage bit, then the output stage bit, and finally the output enable stage bit. The output enable level bits are closest to the time difference.

The user index register command gives a 32-bit programmable user index By using the user command, a user programmable identification code can be removed for inspection. This code is loaded into the user registers during the programming of the platform flash. If the device is blanked or not loaded during programming, the device registered by the user includes ffffffh. Together with the user module, a 32-byte user code is provided for each design review. User code is set during programming and is often used to provide information about the content of design revisions. Private JTAG instructions require reading client code. If the PROM is Blank, or during programming, or if the special design revision is a PROM, the user code will contain everything. Platform Flash PROM TAP Features: Platform Flash PROM Family Performs both in-system programming and IEEE 1149.1 boundary-scan This simplifies system design and alloy standard automatic test equipment to achieve two functions. The AC characteristics of the front cone of a platform flash are described below.

Additional features of the xcfxxp internal oscillator 8/16/32 mbit xcfxxp platform flash proms include an optional internal oscillator that can be used to drive the clkout and data pins on the FPGA configuration interface. The internal oscillator can be enabled during device programming and can be set to the default frequency or to a slower frequency (AC characteristic under operating conditions when cascaded). The clkout 8/16/32 mbit xcfxxp platform flash prom includes a programmable option to enable the clkout signal which allows the prom to provide a source synchronous clock aligned with the data on the configuration interface. The clkout signal comes from one of two clock sources: the clk input pin or the internal oscillator. The input clock source is selected during PROM programming. The output data is on the rising edge of clkout.
The CLKOUT signal is enabled during programming and is active when CE is low and OE/RESET is high. When disabled, the CLKOUT pin will enter a high impedance state and should be pulled high externally to provide a known state. When the clkout-enabled cascaded platform flash prom completes data transfer, the first prom disables clkout and releases the ceo pin to enable the next prom in the prom chain. Once the programmable read only memory (prom) is enabled and data is available for transfer, the next programmable read only memory (prom) will start driving the clkout signal. During uncompressed high-speed parallel configuration, the FPGA drives a busy signal on the configuration interface. When busy is asserted high, the proms internal address counter stops incrementing and the current data value remains on the data output. When busy is high, the prom will continue to drive the clkout signal to the fpga, clocking the fpga's configuration logic. When the field programmable gate array (FPGA) stops working, indicating that it is ready to receive additional configuration data, the programmable gate array (PROM) will start driving new data on the configuration interface.

Decompress 8/16/32mbit xcfxxp platform flash proms includes a built-in data decompressor compatible with xilinx advanced compression technology. Compressed platform flash prom files are created from the target fpga bitstream using the impact software. When using the xcfxxp prom programmed with the compressed bitstream, the fpga configuration only supports slave serial and slave selectmap (parallel) configuration modes. Compression ratio will depend on several factors, including target device family and target design content. The decompression option is enabled during PROM programming. The prom decompresses the stored data before driving the clock and data simultaneously to the FPGA's configuration interface. If decompression is enabled, the platform flash clock output pin (CLK
out) must be used as the clock signal of the configuration interface to drive the configuration clock input pin (cclk) of the target FPGA. Either the PROM's CLK input pin or the internal oscillator must be selected as the source for CLKOUT. Any target FPGA connected to the prom must operate as a slave in the configuration chain with the configuration mode set to slave serial mode or slave select mapped (parallel) mode. When decompression is enabled, the CLKOUT signal becomes the controlled clock output with maximum frequency reduction. When the decompressed data is not ready, the clkout pin will go to the high-z state and must be pulled high externally to provide a known state. When decompression is enabled, busy input is automatically disabled.
Design Modifications Design Modifications allow users to store up to four unique design modifications on a single prom or across multiple cascaded proms. The 8/16/32 mbit xcfxxp platform flash proms support design modifications in both serial and parallel modes. Design modifications can be used with compressed prom files or when the clkout feature is enabled. The prom programming files and revision information files (.cfi) are created using the impact software. The cfi file is required to enable design revision programming in impact. A single design revision consists of 1 to n 8 mbit memory blocks. If a single design revision contains less than 8mbits of data, the remaining space will be filled with all data. Larger design revisions can span multiple 8-mbit memory blocks, and any space left in the last 8-mbit memory block fills all of the space. • A single 32mbit prom contains four 8mbit memory blocks and thus can store up to four independent design revisions: one 32mbit design revision, two 16mbit design revisions, three 8mbit design revisions, four 8mbit design revisions, and so on. • Due to the minimum size requirement of 8-mbit per version, a single 16-mbit prom can only store up to two separate design versions: a 16-mbit design version, an 8-mbit design version, or two 8-mbit design versions Version. • A single 8-mbit prom can store only one 8-mbit design revision. Larger design modifications can be split across several cascading proms. For example, two 32mbit proms can store up to four separate design revisions: one 64mbit design revision, two 32mbit design revisions, three 16mbit design revisions, four 16mbit design revisions, and so on. When cas a 16mbit prom and an 8mbit prom have 24mbit free space, so up to three separate design revisions can be stored: one 24mbit design revision, two 8mbit design revisions, or three 8mbit design revisions. See Figure 7 for some basic examples of how to store multiple revisions. Design revision partitions are handled automatically during the file generation process in impact. During prom file creation, after programming the platform flash prom with a set of design revisions, each design revision is assigned a revision number: revision 0 = '00' revision 1 = '01' revision 2 = '10' revision 3='11'. A specific design revision can be selected using the external rev_sel[1:0] pins or using the internal programmable design revision control bits. The en_ext_sel pin determines whether an external pin or an internal bit is used to select the design version. When en_ext_sel is low, design revision selection is controlled by the external revision selection pins rev_sel[1:0]. When en_ext_sel is high, design revision selection is controlled by the internal programmable revision selection control bits. Design revision select inputs (pins or control bits) are sampled internally during power-up. After power-up, when CE is asserted (low) to enable the PROM input, the design modification select input is sampled again after the rising edge of the CF pulse. The data for the selected design version is then displayed on the FPGA configuration interface.

PROM to FPGA CONFIGURATION MODE AND CONNECTION SUMMARY: The FPGA's I/O, logic functions, and internal interconnects are established by configuration data contained in the FPGA bitstream. The bitstream is automatically loaded into the FPGA at power-up, or loaded into the FPGA on command, depending on the state of the FPGA's mode pin. The xilinx platform flash proms are designed to be downloaded directly to the fpga configuration interface. The fpga configuration methods supported by the flash proms of the xcfxs platform include: master serial and slave serial. The fpga configuration modes supported by the flash proms of the xcfxxp platform include: master serial, slave serial, master selection mapping and slave selection mapping. Below is a brief summary of the supported FPGA configuration modes. For device configuration details, including which configuration modes are supported by the target FPGA device, see the appropriate FPGA datasheet. FPGA Master Serial Mode In master serial mode, the configuration clock (cclk) generated by the FPGA synchronizes the external memory and automatically loads the configuration bit stream in bit serial form. The main serial configuration mode is selected using the FPGA's mode select pins at power up or reconfiguration. Master serial mode provides a simple configuration interface. Configuring an FPGA only requires a serial data line, a clock line, and two control lines (init and done). Data from the prom is read out sequentially on a single data line (din), accessed through the prom's internal address counter, which is incremented on every valid rising edge of cclk. The serial bit stream data must be set on the fpga's din input pin a short time before each rising edge of the cclk signal generated internally by the fpga.
In general, a wide range of frequencies can be chosen for the fpga's internally generated cclk, which always starts with a slow default frequency. The bitstream of the fpga contains configuration bits that can switch the cclk to a higher frequency for the remainder of the main serial configuration sequence. The desired cclk frequency is selected during bitstream generation. Connect the fpga device to the main serial configuration mode's configuration prom (Figure 8): • The data output of the prom drives the main fpga device's din input. • The main FPGA cclk output drives the prom's clk input; the prom's ceo output drives the ce input (if any) of the next prom in the daisy chain. • All prom's oe/reset pins are connected to all fpga devices' init_b pins. This connection ensures that the PROM address counter is reset before starting any (re)configuration. • The PROM CE input can be driven by the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided DONE is not permanently grounded. CE can also be clamped permanently low, but this will keep the data output active and cause unnecessary ICC active supply current (DC characteristic under operating conditions). • The prom cf pin is usually connected to the FPGA's prog-b (or program) input. For xcfxxp only, the cf pins are bidirectional pins. If the xcfxxp cf pin is not connected to the FPGA's prog_b (or program) input, the pin should be tied high. Slave-Serial Mode In slave-serial mode, the FPGA loads an externally-supplied clock-synchronized configuration bit stream from external memory in bit-serial form. At power up or reconfiguration, use the FPGA's mode select pins to select the slave serial configuration mode. Slave serial mode provides a simple configuration interface. Configuring an FPGA only requires a serial data line, a clock line, and two control lines (init and done). Data from the prom is read out sequentially on a single data line (din), accessed through the prom's internal address counter, which is incremented on every valid rising edge of cclk. The serial bit stream data must be set on the DIN input pin of the FPGA a short time before each rising edge of the externally supplied cclk. Connect the fpga device to the configuration prom in slave serial configuration mode: • The data output of the prom drives the din input of the master fpga device. • prom clkout (xcfxxp only) or an external clock source to drive the fpga's cclk input.
• The CEO output of a PROM drives the CE input (if any) of the next PROM in the daisy chain. • All prom's oe/reset pins are connected to all fpga devices' init_b (or init) pins. This connection ensures that the PROM address counter is reset before starting any (re)configuration. • The PROM CE input can be driven by the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided DONE is not permanently grounded. CE can also be clamped permanently low, but this will keep the data output active and cause unnecessary ICC active supply current (DC characteristic under operating conditions). • The prom cf pin is usually connected to the FPGA's prog-b (or program) input. For xcfxxp only, the cf pins are bidirectional pins. If the xcfxxp cf pin is not connected to the FPGA's prog_b (or program) input, the pin should be tied high. Serial Daisy Chaining Multiple FPGAs can be daisy-chained for serial configuration from a single source. After a specific fpga is configured, the data for the next device is internally routed to the fpga's dout pin. Typically, the data on the dout pin changes on the falling edge of cclk, although for some devices, the dout pin changes on the rising edge of cclk. For details on a specific FPGA device, see the appropriate device datasheet. For clocks in a daisy-chain configuration, you can set the first fpga in the chain as master serial, generate cclk, and the rest of the devices as slave serial, or set all fpga devices to slave serial and use an externally generated clock to drive the fpga configuration interface. FPGA Master Select Mapping (Parallel) Mode (1) In Master Select Mapping mode, byte-range data is written to the fpga, usually with a busy flag to control the data flow, synchronized by the configuration clock (cclk) generated by the fpga. At power up or reconfiguration, use the FPGA's mode select pins to select the main select map configuration mode. A configuration interface typically requires a parallel data bus, a clock line, and two control lines (init and done). Additionally, the chip select, write, and busy pins of the FPGA must be properly controlled to enable selectmap configuration. Configuration data is read byte by byte from the PROM a short time before each rising edge of the cclk signal generated inside the fpga. If the fpga asserts busy (high), it must hold the configuration data until busy goes low. The FPGA's active low chip select (cs or cs_b) and write (write or rdwr_b) signals must be enabled using an external data source or an external pull-down resistor to enable the FPGA's selectmap configuration process. The main selectmap configuration interface is clocked by the FPGA's internal oscillator. In general, a wide range of frequencies can be chosen for the internally generated cclk that always starts with a slow default frequency. The bitstream of the fpga contains configuration bits that can switch the cclk to a higher frequency for the remainder of the main selectmap configuration sequence. The desired cclk frequency is selected during bitstream generation. Once configured, the pins of the selectMap port can be used as other user I/O. Alternatively, the port can be reserved using the persist option. Connect the fpga device to the configuration prom of the main selectmap (parallel) configuration mode: • The data output of the prom drives the [d0..d7] inputs of the main fpga device. • The main FPGA cclk output drives the prom's clk input; the prom's ceo output drives the ce input (if any) of the next prom in the daisy chain. • All prom's oe/reset pins are connected to all fpga devices' init_b pins. This connection ensures that the PROM address counter is reset before starting any (re)configuration. • The PROM CE input can be driven by the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided DONE is not permanently grounded. CE can also be clamped permanently low, but this will keep the data output active and cause unnecessary ICC active supply current (DC characteristic under operating conditions). • For high frequency parallel configuration, all the busy pins of the prom are connected to the busy output of the FPGA. This connection ensures that the next data transition of the prom is delayed until the FPGA is ready for the next byte of configuration data. • The prom cf pin is usually connected to the FPGA's prog-b (or program) input. For xcfxxp only, the cf pins are bidirectional pins. If the xcfxxp cf pin is not connected to the FPGA's prog_b (or program) input, the pin should be tied high. fpga slave selectmap (parallel) mode (1) In slave selectmap mode, byte-range data is written to the fpga, and there is usually a busy flag to control the data synchronized by the externally provided configuration clock (CCLK). At power up or reconfiguration, use the FPGA's mode select pins to select the configuration mode from the selectmap. A configuration interface typically requires a parallel data bus, a clock line, and two control lines (init and done). Additionally, the chip select, write, and busy pins of the FPGA must be properly controlled to enable selectmap configuration. Configuration data is read from the prom byte by byte on pins [d0..d7], accessed through the prom's internal address counter, which is incremented on every valid rising edge of cclk. The bitstream data must be set at the FPGA's [D0..D7] input pins a short time before each rising edge of the supplied cclk. If the fpga asserts busy (high), it must hold the configuration data until busy goes low. The FPGA's active low chip select (cs or cs_b) and write (write or rdwr_b) signals must be enabled using an external data source or an external pull-down resistor to enable the FPGA's selectmap configuration process. Once configured, the pins of the selectMap port can be used as other user I/O. Alternatively, the port can be reserved using the persist option. Connect the fpga device to the configuration prom for slave selectmap (parallel) configuration mode: • The data output of the prom drives the [d0..d7] input of the master fpga device. • The prom clkout (xcfxp only) or an external clock source drives the fpga's cclk input • The prom's ceo output drives the ce input of the next prom in the daisy chain (if any). • All prom's oe/reset pins are connected to all fpga devices' init_b pins. This connection ensures that the PROM address counter is reset before starting any (re)configuration. • The PROM CE input can be driven by the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided DONE is not permanently grounded. CE can also be clamped permanently low, but this will keep the data output active and cause unnecessary ICC active supply current (DC characteristic under operating conditions). • For high frequency parallel configuration, all the busy pins of the prom are connected to the busy output of the FPGA. This connection ensures that the next data transfer from the PROM is delayed

fpga selectmap (parallel) device chain (1) Use selectmap mode to configure multiple virtex ii fpga and start them at the same time. To configure multiple devices this way, connect the individual cclk, done, init, data ([d0.d7]), write (write or rdwrwrwru-b), and busy pins of all devices in parallel. If all devices are configured to the same bitstream, no readback is used, and the selected cclk frequency does not require the use of a busy signal, the cs-b pin can be connected to a common line to configure all devices simultaneously (Figure 13). With additional control logic, each device can be loaded individually by asserting the cs.b pin of each device in turn, then enabling the appropriate configuration data. The prom can also store separate bitstreams for each FPGA for selectmap configuration in separate design revisions. When using design modifications, additional control logic can be used to select the appropriate bit stream by asserting that en:ext has sold the sel pin and using rev. For the clock of the parallel configuration chain, the first fpga in the chain can be set to master selectmap, generating cclk, and the rest of the devices can be set to slave selectmap, or all fpga devices can be set to slave selectmap, and can use externally generated clock to Driver configuration interface. Likewise, for details on a specific FPGA device, including which configuration modes are supported by the target FPGA device, the corresponding device datasheet should be consulted.
The cascade configuration prom provides ms additional memory when configuring multiple FPGAs in a serial daisy chain, multiple configuration FPGAs in a selectmap parallel chain, or when configuring a single FPGA that requires a larger configuration bitstream. The multi-platform flashprom can be connected via the ceo output driving the ec input of the downstream device. The clock signals and data outputs of all platform flash proms in the chain are connected to each other. After reading the last date of the first prom, the first prom asserts its ceo's output low and drives its output to a high impedance state. The second prom recognizes a low on its ec input and immediately enables its output. After configuration, if the prom oe/reset pin goes low or ce goes high, the address counters of all cascaded proms are reset. When using the advanced features of the xcfxxp platform flash prom, including clock out (clkout) options, decompression options, or design modifications, programming files across cascaded prom devices can only be created for cascaded chains that contain only the xcfxp prom. Cascading prom chains can contain both xcfxp and xcfxs proms if advanced features are not used.
Start fpga configuration Options to start fpga configuration through the platform flash prom include: 1. Automatic configuration when starting 2. Apply external program AB (or program) pulse 3. The jtag configuration instruction is applied following the power-on sequence of the FPGA or the assertion of the prog has been pinned to the b (or program) pin, the memory configuration of the FPGA is cleared, the configuration mode is selected, and the FPGA is ready to accept the new bitstream configuration. The fpga's prog has a b pin that can be controlled by an external source, or the platform flash prom contains a cf pin that can be bound to the fpga's prog or b pin. Execute the configuration command through the jtag, output the cf low pulse once for 300-500ns, reset the fpga and start the configuration. By setting the "load fpga" option, the impact software can issue the jtag config command to start the fpga configuration. When flashing a PROM using the XCFxxp platform with the modified design enabled, the CF pin should always be connected to the Prog B (or Program) pin on the FPGA to ensure that the current design modification selection is sampled when the FPGA is reset. xcfxxp samples the current design revision selection from an external rev sel pin or an internally programmable revision selection bit on the rising edge of cf. When the jtag config command is executed, xcfxxp will sample the new design version before starting the fpga configuration sequence. When using the xcfxxp platform flash prom without design modification, if the cf pin is not connected to the fpga prog, then it becomes a b (or program) pin, the xcfxxp cfpin should be tied high.

Configure the connection diagram of the prom to the fpga device interface

Configure in Slave Serial Mode

Configure multiple devices in master/slave serial mode

Configured in Slave SelectMap mode

Configure multiple devices with same mode in master/slave selectmap mode

Configure multiple devices with design modifications in slave serial mode

Configured in primary selection mapping mode

Reset and power-on reset activation At power-up, the device requires the VCCINT supply to rise monotonically to the nominal operating voltage within the specified VCCINT rise time. If the power supply fails to meet this requirement, the device may not perform a power-on reset properly. The Programmable Read Only Memory (PROM) holds Run Experience/Reset low during power up. Once the required power supplies have reached their respective POR (Power-On Reset) thresholds, the run experience/reset release will be delayed (to the minimum) to allow more margin for the power supplies to settle before starting the configuration. The oe/reset pin is connected to an external 4.7kΩ pull-up resistor and also to the init pin of the target FPGA. For systems using slowly rising power supplies, additional power supply monitoring circuitry can be used to delay the target configuration by holding the oe/reset pin low until the system power supply reaches the minimum operating voltage. When oe/reset is released, the FPGA's init pin is pulled high, allowing the FPGA's configuration sequence to begin. If the power drops to

Power down threshold (VCCPD), PROM reset, OE/RESET is held low again until the POR threshold is reached. OE/reset polarity is not programmable. These power-up requirements are shown in Figure 16. For the full power platform flash prom, a reset occurs whenever oe/reset is asserted (low) or ce is deasserted (high). The address counter is reset, the ceo is driven high, and the remaining outputs are in a high impedance state. Note: 1.xcfxs prom only requires vccint to be above its por threshold before releasing oe/reset. 2. The xcfxxp prom requires vccint to rise above its por threshold and vcco to the recommended operating voltage level before releasing oe/reset.
Input/Output Input Voltage Tolerance and Power Sequencing The input/output on each reprogrammable platform flash prom is fully 3.3v tolerant. This allows 3V CMOS signals to be connected directly to the input without damage. Core power (VCCINT), JTAG pin power (VCCJ), output power (VCCO), and external 3V CMOS I/O signals can be applied in any order. Also, for the xcfxs prom only, the i/o is 5v tolerant when vcco is powered at 2.5v or 3.3v and vccint is powered at 3.3v. This allows 5V CMOS signals to be connected directly to the input of the power supply xCFxS PROM without damage. Failure to properly power the PROM when a 5V input signal is provided may result in damage to the XCFXS device.
Standby Mode Whenever CE is deasserted (high), the PROM enters a low-power standby mode. In standby mode, the address counter is reset, ceo is driven high, and the remaining outputs are in a high-impedance state, regardless of the state of the oe/reset input. To keep the device in low power standby mode, the JTAG pins tms, tdi and tdo must not be pulled low and TCK must be stopped (high or low). After the configuration is complete, an external pull-up resistor should be used when driving the prom ce pin high with the FPGA done signal to reduce standby power. A 330Ω pull-up resistor is typically used, but see the appropriate FPGA datasheet for recommended pull-up values for done pins. If the done circuit is connected to the LED that indicates the FPGA is configured and is also connected to the PROM CE pin to enable low power standby mode, then an external buffer should be used to drive the LED circuit to ensure a valid transition on the CE pin of the PROM. If the PROM does not require a low power standby mode, the CE pin should be grounded