Features optimized for high performance 3.3V systems
- 5 ns end-to-end logic delay with internal system frequency up to 208 MHz
- Small packages including vqfps, tqfps and csp (chip scale package)
- Free PB for all packages
- low power operation
- 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS flash technology with advanced system capabilities
- Programmable within the system
- Superior pin locking and routability
FastConnect II Switch Matrix
- Extra wide 54 input function block
- Up to 90 product terms per macrocell with separate product term assignments: XC9500XL device family
- Local clock inversion with three global and one product term clock
- Individual output enable for each output pin (with local inversion)
- Input hysteresis on all user and boundary scan pin inputs
- Bus hold circuits on all user pin inputs
- Support hot plug function
- Full support for IEEE standard 1149.1 boundary scan (jtag) on all devices
Four-pin compatible device density
- 36 to 288 macrocells, 800 to 6400 usable gates Fast concurrent programming of individual outputs Slew rate control Enhanced data security features Superior quality and reliability
- 10000 program/erase cycle endurance rating
- 20-year data retention pin compatible with 5V core XC9500 series, packaged in a general-purpose package

family profile
The FastFlash XC9500XL series is a 3.3V CPLD family primarily intended for high-performance, low-voltage applications in high-end communications and computing systems where high device reliability and low power consumption are important. Each xc9500xl device supports in-system programming (ISP) and full IEEE std 1149.1 (jtag) boundary scan, providing superior debugging and design iteration capabilities for small form factor packages. The XC9500XL series is designed to work closely with the field programmable gate arrays of the XilinxVirtex series, Spartan series and XC4000XL series, enabling system designers to optimally divide logic between fast interface circuits and high-density general purpose logic. As shown in Table 1, the logic densities of the XC9500XL devices range from 800 to 6400 usable gates and 36 to 288 registers, respectively. The various package options and associated I/O capacity are shown in Table 2. The XC9500XL family members are fully pin-compatible, allowing easy design migration across multiple density options in a given package outline.
The XC9500XL architectural features meet the requirements of in-system programmability. Enhanced pin locking avoids costly board rework. System programming and high programming durability ratings throughout commercial operation provide hassle-free system field upgrades and reconfigurations. Extended data retention supports longer, more reliable system operating life.
Advanced system features include output slew rate control and a user-programmable ground pin to help reduce system noise. Each user pin is compatible with 5V, 3.3V, and 2.5V inputs, and the outputs can be configured for 3.3V or 2.5V operation. The XC9500XL device displays a symmetrical 3.3V full output voltage swing to allow for balanced rise and fall times.

Each XC9500XL device is a subsystem consisting of multiple function blocks (FBS) and I/O blocks (IOB), fully interconnected through the FastConnect II switch matrix. iob provides buffering for device input and output. Each FB provides programmable logic capability with an additional 54 inputs and 18 outputs. The FastConnect II switch matrix connects all FB output and input signals to the FB input. For each FB, up to 18 outputs (depending on package pin count) and associated output enable signals are driven directly to the IOB
Function block Each function block is composed of 18 independent macro units, and each macro unit can realize the function of combination or registration. The FB also receives global clock, output enable and set/reset signals. The FB produces 18 outputs that drive the FastConnect switch matrix. These 18 outputs and their corresponding output enable signals also drive the iob.
The logic in fb is implemented using the sum of product representations. 54 inputs provide 108 true and complementary signals to the programmable sum array, forming 90 product terms. Any number of these product terms (up to 90 available terms) can be assigned to each macrocell by the product term assigner.

Each xc9500xl macrocell can be configured individually for operation. Each register supports two asynchronous sets for combining functions or registering functions. Macro cells and reset operations. When powered on, all the FB logic related to user registration is shown in Figure 3. Initialized to a user-defined preload state (if not specified, defaults to 0 5 direct product terms from and array are available).
Used as primary data input (to OR and XOR gates) for combinational functions, or as control input including clock, clock enable, set/reset, and output enable. The Product Term Allocator associated with each macrocell chooses how to use the five direct terms.

All global control signals for XC9500XL macrocells within a function block are available for each macrocell, including clock, set/reset and output enable signals. The macrocell register clock is derived from three global clocks or a product term clock. Both true and complementary polarity of the selected clock source can be used in each macrocell. A gsr input is also provided to allow setting of user registers to user-defined states.

Product Term Allocator The Product Term Allocator controls how the five direct product terms are assigned to each macrocell. For example, all five direct terms can drive or function

Direct Product Term Macrocell Logical Product Term Allocator can reallocate other product terms in fb to increase the logical capacity of a macrocell beyond five direct terms. Any macrocell that requires additional product terms can access unsubmitted product terms in other macrocells within FB. A macrocell can use up to 15 product terms, while the incremental delay of TPTA is small. Note that the incremental delay only affects product terms in other macrocells. The timing of the direct product terms has not changed.

The input buffers are compatible with 5V CMOS, 5V TTL, 3.3V CMOS, and 2.5V CMOS signals. The input buffer uses an internal 3.3V voltage source (V) to ensure that the input threshold is constant and does not vary with the V voltage. Each input buffer provides input hysteresis (50 mV typical) to help reduce system noise on input signals with slow rising or falling edges. CCNTCIO
Each output driver is designed to provide fast switching and minimal power noise. All output drivers in the device can be configured to drive 3.3v cmos levels (also compatible with 5v ttl levels) or 2.5v cmos levels by connecting the device output voltage supply (v) to a 3.3v or 2.5v voltage supply. Figure 11 shows how the XC9500XL device can be used in systems with only 3.3V and mixed voltage systems, and any combination of 5V, 3.3V, and 2.5V supplies. CIO
Each output driver can also be configured for slew rate limited operation. Under user control, the output edge rate can be reduced to reduce system noise (additional time delay t).

The output enable can be generated from one of four options: product term signal from macrocell, any global output enable signal (gts), always '1' or always '0'. For devices with 72 or fewer macrocells, there are two global output enables, and for devices with 144 or more macrocells, there are four global output enables. Any selected output enable signal can be partially inverted at each pin output for maximum design flexibility.
Each IOB provides user programmable ground pin capability. This allows device I/O pins to be configured as additional ground pins, to force otherwise unused pins into a low voltage state, and to provide additional device ground capability. The grounding of the pin is achieved through internal logic that forces a logic low output regardless of the internal macrocell signal, so the internal macrocell logic is not affected by the programmable ground pin capability.
Each iob also provides a bus hold circuit (also called a "keeper") that is active during active user operation. The bus hold feature eliminates the need to connect unused pins, whether high or low, by holding the last known state of the input until the next input signal occurs. The bus hold circuit drives the same state through a nominal resistance (R) of 50 kΩ. Note: The bus hold output will be driven no higher than V to prevent signal overdriving when interfacing with 2.5V components. BHCIO

XC9500XL devices, only for (A) 3.3V and (B) mixed 5V/3.3V/2.5V systems When the device is not in active user operation, the bus hold circuit defaults to an equivalent 50 kΩ pull-up resistor to Provides a known repeatable device state. This happens when the device is in erased state, programming mode, JTAG INTEST mode, or initially powered up. A pull-down resistor (1kΩ) can be added externally to any pin to override the default R resistor to force a low state during power up or any other mode. BH
5V Fault Tolerant I/O
The I/Os on every XC9500XL device are fully 5V tolerant, even though the core power supply is 3.3V. This allows 5V CMOS signals to be connected directly to the XC9500XL inputs without damage. The 3.3V supply must be at least 1.5V before applying the 5V signal to the I/O. In a 3.3v/2.5v hybrid system, user pins, core power (v) and output power (v) can be powered in any order. CCNTCCNTCIO
Xilinx proprietary ESD circuitry and high-impedance initial states allow hot-swappable cards using these devices.
Pin Locking Ability The ability to lock user-defined pin assignments during design iterations depends on the architecture's ability to accommodate unexpected changes. The xc9500xl device incorporates architectural features that enhance the ability to accept design changes while maintaining the same pinout.
The xc9500xl architecture combines a large number of routing switches in the fastconnect ii switch matrix, a 54-wide input function block, and flexible bi-directional product term assignment within each macrocell to provide superior pin locking characteristics. These features address design changes that require adding or changing internal routing, including adding additional signals to existing equations, or increasing equation complexity, respectively.

In-System Programming One or more XC9500XL devices can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol, as shown in Figure 14. In-system programming provides fast and efficient design iteration and eliminates packet processing. The xilinx development system provides programming data sequences using xilinx download cables, third-party jtag development systems, jtag compatible board testers, or a simple microprocessor interface that emulates jtag instruction sequences.
During system programming, all I/Os are 3-state and pulled high by the bus hold circuit. If a particular signal must remain low during this time, a pull-down resistor can be added to the pin.
external programming
The XC9500XL device can also be programmed by Xilinx HW-130 device programmers and third-party programmers. This provides additional flexibility in using pre-programmed devices during manufacturing and provides in-system programmable options for future enhancements and design changes.
Reliability and Endurance All xc9500xl cplds offer an endurance level of at least 10000 and a data retention period of at least 20 years in system program/erase cycles. Each device complies with all functional, performance and data retention specifications within this duration limit.
IEEE Standard 1149.1 Boundary Scan (jtag)
The xc9500xl device fully supports the IEEE standard 1149.1 boundary scan (jtag). Each device supports extest, sample/preload, bypass, usercode, intest, idcode, highz and clamp instructions. Additional instructions are included in System Programming Operations.
security by design
The XC9500XL device includes advanced data security features that fully protect programming data from unauthorized reads or accidental device wipe/reprogramming. Table 3 shows the four different security settings available.
The user can set the read security bit to prevent reading or copying the internal programming mode. Once set, they also prohibit further program operations but allow device wipes. Erasing the entire device is the only way to reset the read security bit.
The write security bit provides additional protection against accidental device erasure or reprogramming when the jtag pins are affected by noise, such as during system power-up. Once set, write protection can be disabled when the device needs to be reprogrammed with a valid mode and a specific jtag command sequence.

Low Power Modes All XC9500XL devices offer low power modes for a single macrocell or across all macrocells. This feature can significantly reduce device power.
Each macrocell can be programmed by the user in a low power mode. Performance-critical parts of the application can remain in standard power mode, while other parts of the application can be programmed to operate at low power to reduce overall power consumption. Macrocells programmed for low-power modes incur additional delays (tlp) in pin-to-pin combined delays and register setup times. Product Item Clock Out and Product Item Output Enable Delay are not affected by the macrocell power setting. Signals switching at rates less than 50ns rise/fall time shall be assigned to macrocells configured in low power mode.
time series model
The consistency of the XC9500XL architecture allows for a simplified timing model of the entire device. The basic timing model applies only to macrocell functions that use direct product terms, with standard power settings and standard slew rate settings. Table 4 shows the effect of product term allocator (if required), low power setting and slew limit setting on each key timing parameter.
The product term allocation time depends on the logical span of the macrocell function, which is defined to be less than the maximum number of allocators in the product term path. If only direct product terms are used, the logical span is 0.

Power-Up Characteristics During power-up, the XC9500XL device I/O may be undefined until V rises above 1 volt. This period of time is called the subthreshold region because the transistor is not fully turned on yet. If v is energized before or at the same time as v, the i/o can be driven over this voltage transition range. If V is powered up after V has passed the subthreshold region, the I/O will be in 3-state with a weak pull-up until V reaches the threshold for the user's operating state (about 2.5V). When V reaches this point, the user registers are initialized (usually within 200µs), and then the I/O will adopt the behavior determined by user mode, as shown in Figure 17. If the device is in a wiped state (before any user-mode programming), the device output will remain disabled on weak pullups. The JTAG pins allow the device to be programmed at any time. All devices are shipped in a wiped state.
If the device is programmed, the device inputs and outputs will assume their normal operating configuration state. The jtag pin allows device erase or boundary scan testing at any time.
Development system support
The XC9500XL series and related in-system programming capabilities are fully supported in any of the software solutions offered by Xilinx.
The Foundation Series is an integrated development system with schematic entries, HDL (VHDL, Verilog).
Timing model parameters and simulation capabilities. It supports xc9500xl series and other cpld and fpga series.
The consortium series includes cpld and fpga implementation technologies, as well as all libraries and interfaces required for the consortium partner eda solution.
FastFlash technology uses an advanced 0.35-micron feature size CMOS flash process to manufacture all XC9500XL devices. The fastflash process provides high-performance logic capabilities, fast programming times, and excellent reliability and durability ratings.