Product Description

The AD9754 is the second generation broadband 14-bit resolution member of the TXDAC family of high-performance, low-power CMOS digital-to-analog converters (DACs). The txdac series consists of 8-bit, 10-bit, 12-bit and 14-bit pin-compatible DACs optimized for the transmission signal path of communication systems. All devices share the same interface options, small form factor package and pinout, providing an upward or downward component selection path based on performance, resolution and cost. The AD9754 offers excellent ac and dc performance while supporting update rates up to 125 msps.

The AD9754 has a flexible single-supply operating range of +4.5V to +5.5V, and its low power consumption is ideal for portable and low-power applications. Its power consumption can be further reduced to just 65 MW, with a slight drop in performance, by lowering the full-scale current output. In addition, the power-down mode reduces standby power consumption to approximately 20 mW.

The AD9754 is fabricated using an advanced CMOS process. The segmented current source structure is combined with proprietary switching technology to reduce spurious components and improve dynamic performance. An edge-triggered input latch and a 1.2v temperature compensated bandgap reference are integrated to provide a complete monolithic dac solution.

Digital inputs support +2.7V and +5V CMOS logic families.

TXDAC is a registered trademark of Analog Devices Corporation.

Protected by US Patent Nos. 5,450,084, 5,568,145, 5,689,257, 5,612,697 and 5,703,519.

The AD9754 is a current output DAC with a nominal full-scale output current of 20 mA and an output impedance greater than 100 kΩ.

Differential current outputs are available to support single-ended or differential applications. Matching between the two current outputs ensures enhanced dynamic performance in differential output configurations. The current output can be connected directly to an output resistor to provide two complementary single-ended voltage outputs or fed directly into a transformer. The output voltage conforms to a range of 1.25v.

The on-chip reference and control amplifiers are configured for maximum accuracy and flexibility. The AD9754 can be driven by an on-chip voltage reference or various external reference voltages. The internal control amplifier provides a wide (>10:1) adjustment range, allowing the AD9754 full-scale current to be adjusted from 2 mA to 20 mA while maintaining good dynamic performance. Therefore, the AD9754 can operate at reduced power levels, or can be adjusted within 20dB to provide additional gain ranging capability. The AD9754 is available in 28 lead SOIC and TSSOP packages. Specified for operation in the industrial temperature range.

Product Highlights

1. The AD9754 is a member of the wideband TXDAC high-performance product family that provides an upward or downward component selection path based on resolution (8 to 14 bits), performance, and cost. The full range of TXDACs feature industry standard pins.

2. The AD9754 is fabricated in a CMOS process and employs a special switching technique that improves dynamic performance over what was previously achievable with higher power/cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input cmos latches are easily interfaced with the +2.7v to +5v cmos logic family. The AD9754 can support update rates up to 125 msps.

4. The flexible single-supply operating range is +4.5 V to +5.5 V, and the wide full-scale current adjustment range is 2 mA to 20 mA, allowing the AD9754 to operate at lower power levels.

5. The current output of the AD9754 can be easily configured for various single-ended or differential circuit topologies.

canonical definition

Linearity Error (also known as Integral Nonlinearity or inl) Linearity error is defined as the maximum deviation of the actual analog output from the ideal, determined by a straight line from zero to full scale.

Differential nonlinearity (or dnl)

dnl is a measure of the change in analog value, normalized to full scale, relative to a 1lsb change in the digital input code.

offset error

The deviation of the output current from the ideal zero is called offset error. For iouta, when all inputs are 0, the expected output is 0 mA; for ioutb, when all inputs are set to 1, the expected output is 0 mA.

gain error

The difference between the actual output range and the ideal output range. The actual range is determined by the output value when all inputs are set to 1s minus the output value when all inputs are set to 0s.

Output conforms to range

The allowable voltage range at the output of the current output digital-to-analog converter. Operation beyond the maximum compliance limit can cause the output stage to saturate or collapse, resulting in nonlinear performance.

temperature drift

Temperature drift is specified as the maximum change from the ambient (+25°C) value to the tmin or tmax value. For offset and gain drift, the drift is reported in ppm per °C of full-scale range (fsr). For reference drift, the drift is reported in ppm per °C.

Power supply rejection

The maximum change in the full-scale output when the power supply changes within the specified range.

Settling time

Measured from the transition of the output, the time required for the output to reach and remain within the specified error band of its final value.

fault pulse

Asymmetric switching times in DACs can produce undesired output transients that can be quantified by fault pulses. It is designated as the net area of faults in PV-s.

Spurious free dynamic range

The difference, in decibels, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

total harmonic distortion

thd is the ratio of the sum of the rms values of the first six harmonic components to the rms value of the measured output signal. It is expressed in percent or decibels (db).

Multi-tone power ratio

The spurious-free dynamic range of an output containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of the carrier tone and the removal of peak spurs in the tone region.

Function description

Figure 16 shows a simplified block diagram of the AD9754. The AD9754 consists of a large array of PMOS current sources capable of delivering up to 20 mA total current. The array is divided into 31 equal currents that make up the 5 most significant bits (msb). The next four or middle bits consist of 15 equal current sources with a value of 1/16 the msb current source. The remaining lsb are binary weighted fractions of the median current source. Using a current source instead of an R-2R ladder for low-mids improves the dynamic performance of multi-tone or low-amplitude signals and helps maintain the high output impedance of the DAC (i.e., >100kΩ).

All of these current sources are switched to one or the other of the two output nodes (i.e. iouta or ioutb) via pmos differential current switches. These switches are based on a new architecture that greatly improves distortion performance. This new switch structure reduces various timing errors and provides matched complementary drive signals for the inputs of the differential current switches.

The analog and digital sections of the AD9754 have separate power supply inputs (ie, AVDD and DVD). The digital section consists of marginalized latches and segmented decode logic, capable of operating at a clock rate of 125 msps and an operating range of +2.7v to +5.5v. The analog section operates from +4.5v to +5.5v and includes a pmos current source, associated differential switches, a 1.20v bandgap reference, and a reference control amplifier.

The full-scale output current is regulated by the reference control amplifier and can be set from 2mA to 20mA by an external resistor rset. An external resistor, combined with the reference control amplifier and the voltage reference VREFIO, sets the reference current IREF, which is mirrored to a segmented current source with the appropriate scaling factor. The full-scale current ioutfs is 32 times the iref value.

The AD9754 provides complementary current outputs, IOUTA and IOUTB. iouta will provide a near full scale current output, ioutfs, when all bits are high (ie dac code = 16383), while ioutb, the complementary output, will supply no current. The current output appearing at iouta and ioutb is a function of the input code and ioutfs and can be expressed as:

IOUTA = (DAC CODE/16384) × IOUTFS (1)

IOUTB = (16383 – DAC CODE)/16384 × IOUTFS (2),

where DAC code = 0 to 16383 (i.e. decimal representation).

As mentioned earlier, ioutfs is a function of the reference current iref, which is nominally set by the reference voltage vrefio and the external resistor rset. It can be expressed as:

IOUTFS = 32 × IREF(3)

where IREF = VREFIO/RSET (4)

The two current outputs typically drive resistive loads directly or through transformers. If DC coupling is required, iouta and ioutb should be connected directly to a matched resistive load rload connected to the analog common line acom. Note that rload can represent the equivalent load resistance seen by iouta or ioutb, as in the case of a double terminated 50Ω or 75Ω cable. The single-ended voltage output appearing at the iouta and ioutb nodes is simply:

VOUTA = IOUTA × RLOAD(5)

VOUTB = IOUTB × RLOAD(6)

Please note: The full-scale values of vouta and voutb should not exceed the specified output compliance range to maintain the specified distortion and linearity performance.

The differential voltage Vdiff appearing on IOUTA and IOUTB is:

VDIFF = (IOUTA – IOUTB) × RLOAD (7)

Substitute the values of iouta, ioutb, and iref; vdiff can be represented as:

VDIFF = {(2 DAC CODE – 16383)/16384} × VDIFF = {(32 RLOAD/RSET) × VREFIO (8)

The last two equations highlight some of the advantages of the AD9754's differential operation. First, differential operation will help eliminate common-mode error sources such as noise, distortion, and DC offset associated with iouta and ioutb. Second, the differential code-related current and subsequent voltage vdiff is twice the value of the single-ended voltage output (ie, vouta or voutb), thereby delivering twice the signal power to the load.

Note: The gain drift temperature performance of the AD9754 for single-ended (VOUTA and VOUTB) or differential output (VDIFF) can be enhanced by selecting temperature tracking resistors for RLOAD and RSET, as their ratio relationship is shown in Equation 8.

Reference operation

The AD9754 includes an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external reference. refio is used as input or output, depending on whether internal or external references are selected. If reflo is connected to acom as shown in Figure 17, the internal reference is activated and refio provides 1.20 V output. In this case, the internal reference must be externally compensated from refio to reflo with a 0.1µF or larger ceramic chip capacitor. Also, if any additional load is required, the refio should be buffered with an external amplifier with less than 100nA of input bias current.

Internal refs can be disabled by connecting reflo to avdd. In this case, xrefs can be applied to refio, as shown in Figure 18. An external reference can provide a fixed reference voltage for improved accuracy and drift performance, or a variable reference voltage for gain control. Note that since the internal reference is disabled, no 0.1µf compensation capacitor is required, and the refio's high input impedance (i.e. 1 mΩ) minimizes any loading of the external reference.

Reference Control Amplifier

The AD9754 also contains an internal control amplifier that regulates the DAC's full-scale output current, IOUTF. The control amplifier is configured as a VI converter, as shown in Figure 18, whose current output, IREF, is determined by the ratio of VREFIO and an external resistor, RSET, as described in Equation 4. IREF is copied to the segmented current source and IOUTF is set using the appropriate scale factor, as described in Equation 3.

Control amplifier allows wide (10:1) adjustment range

By setting IREF between 62.5µA and 625µA, IOUTF is in the 2mA to 20mA range. The wide adjustment range of IOUTF provides several application advantages. The first benefit is directly related to the power consumption of the AD9754, which is proportional to IOUTF (see the Power Consumption section). The second benefit is the 20dB adjustment, which is useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is about 0.5mhz. The output of the control amplifier is internally compensated by a 150 pf capacitor, which limits the small-signal bandwidth of the control amplifier and reduces its output impedance. Since the -3db bandwidth corresponds to the dominant pole, the time constant, in this case the settling time of the control amplifier's response to the step reference input, can be approximated with a time constant of 320ns.

There are two ways to change the IREF of a fixed resource set. The first method is suitable for single-supply systems where the internal reference is disabled and the common-mode voltage of the refio varies within its compliance range of 1.25 v to 0.10 v. The refio can be driven by a single-supply amplifier or a DAC, allowing iref to be changed for a fixed rset. Since the input impedance of the refio is about 1 mΩ, the gain can be controlled using a simple, low-cost r-2r ladder DAC configured in a voltage-mode topology. This circuit, shown in Figure 19, uses the AD7524 and an external 1.2V reference, the AD1580.

The second method can be used in dual supply systems where the common mode voltage of refio is fixed and iref is changed by an external voltage vgc applied to rset via an amplifier. An example of this approach is shown in Figure 25, where an internal reference is used to set the common-mode voltage of the control amplifier to 1.20 V. The external voltage Vgc is referenced to ACOM and should not exceed 1.2 V.

rset is such that irefmax and irefmin do not exceed 62.5μa and 625μa, respectively. The correlation equation in Figure 20 can be used to determine the value of rset.

Analog output

The AD9754 produces two complementary current outputs, IOUTA and IOUTB, which can be configured for single-ended or differential operation. iouta and ioutb can be converted to complementary single-ended voltage outputs, vouta and

voutb, through the load resistor rload, as described by Equations 5 to 8 in the dac transfer function section. The differential voltage vdiff present between vouta and voutb can also be converted to a single-ended voltage by a transformer or differential amplifier configuration.

Figure 21 shows the equivalent analog output circuit of the AD9754, which consists of a parallel combination of PMOS differential current switches associated with each segmented current source. The output impedance of iouta and ioutb is determined by the equivalent parallel combination of pmos switches, typically 100kΩ in parallel with 5pf. Due to the nature of pmos devices, the output impedance is also slightly dependent on the output voltage (i.e. vouta and voutb), and to a lesser extent on the analog supply voltage, avdd and full-scale current ioutfs. While the signal dependence of the output impedance can be a source of DC nonlinearity and AC linearity (i.e. distortion), its effect may be limited if certain precautions are noted.

iouta and ioutb also have a negative and positive voltage compliance range. The negative output compliance range of -1.0V is set by the breakdown limit of the CMOS process. Operation beyond this maximum limit can cause output stage failure and affect the reliability of the AD9754. The positive output compliance range is slightly dependent on the full-scale output current ioutfs. When IOUTFs=20mA, its nominal voltage is slightly reduced from 1.25V to 1.00V (when IOUTFs=2mA). Operation beyond the positive compliance range will result in clipping of the output signal, severely degrading the linearity and distortion performance of the AD9754.

For applications that require the best DC linearity, iouta and/or ioutb should be held at virtual ground via an iv op amp configuration. Keeping iouta and/or ioutb at virtual ground keeps the output impedance of the AD9754 the same, significantly reducing its effect on linearity. However, due to the limitations of the iv op amp, it does not necessarily lead to the best distortion performance. Note that the INL/DNL specifications for the AD9754 are measured this way using IOUTA. Additionally, over the specified supply range of +4.5 V to +5.5 V, these DC linearity specifications are virtually unaffected.

Operating the AD9754 in a differential or single-ended output configuration with reduced voltage output swing at iouta and ioutb reduces the signal dependence of its output impedance for enhanced distortion performance. Although the voltage compliance range of IOUTA and IOUTB extends from -1.0V to +1.25V, the best distortion performance is obtained when the maximum full-scale signal of IOUTA and IOUTB does not exceed approximately 0.5V. Proper selection of a transformer with a grounded center tap will allow the AD9754 to provide the required power and voltage L at IOUTA and IOUTB while maintaining reduced voltage fluctuations at different loads. DC-coupled applications requiring a differential or single-ended output configuration should size the load accordingly. See the Applying the AD9754 section for examples of various output configurations.

The most significant improvement in the distortion and noise performance of the AD9754 is achieved using a differential output configuration. Common-mode error sources for both iouta and ioutb can be greatly reduced by common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement of distortion performance becomes more pronounced as the frequency content of the reconstructed waveform increases and/or the amplitude decreases.

The distortion and noise performance of the AD9754 is also slightly dependent on the analog and digital power supplies and the full-scale current setting, IOUTF. Operating the analog power supply at 5.0V ensures maximum headroom for its internal PMOS current source and differential switches for improved distortion performance. Although ioutfs can be set between 2mA and 20mA, choosing an ioutfs of 20mA will provide the best distortion and noise performance, as shown in Figure 13. The noise performance of the AD9754 is affected by the digital power supply (DVD), the output frequency, and increases with increasing clock frequency, as shown in Figure 8. Operating the AD9754 at low voltage logic levels between 3 V and 3.3 V will slightly reduce the amount of on-chip digital noise.

In conclusion, the ad9754 achieves the best distortion and noise performance under the following conditions:

(1), differential operation.

(2) The positive voltage swing at IOUTA and IOUTB is limited to +0.5V.

(3), IOUTF is set to 20 mA.

(4) Set the analog power supply (AVDD) to 5.0V.

(5) The digital power supply (DVD) is set to 3.0 V to 3.3 V with appropriate logic levels.

NOTE: The AC performance of the AD9754 is characterized under the operating conditions described above.

digital input

The digital input of the AD9754 consists of 14 data input pins and a clock input pin. The 14-bit parallel data input follows standard positive binary encoding, where db13 is the most significant bit (msb) and db0 is the least significant bit (lsb). When all data bits are at logic 1, the iouta produces a full-scale output current. ioutb produces a complementary output with a full-scale current split between the two outputs as a function of the input code.

The digital interface is implemented using edge-triggered master-slave latches. The DAC output is updated with the rising clock edge, as shown in Figure 1, and is designed to support clock rates up to 125 msps. The clock can operate at any duty cycle that meets the specified latch pulse width. Setup and hold times can also be changed within a clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feed and distortion performance. Best performance is usually obtained when the input data is transitioning on the falling edge of the 50% duty cycle clock.

The digital inputs are logic threshold compatible CMOS,

vThreshold, set to approximately half the digital positive supply (DVD) or vThreshold = dvdd/2 (±20%) The AD9754's internal digital circuitry is capable of operating from a digital supply range of 2.7 V to 5.5 V. So while the DVD is set to accommodate the maximum high level voltage of the TTL drive VOH (max), the digital input can also accommodate TTL levels. A 3V to 3.3V DVD will usually ensure proper compatibility with most TTL logic families. Figure 22 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar except that it includes an active pull-down circuit, thus ensuring that the AD9754 remains enabled if this input is left open.

Since the AD9754 can be updated to 125 msps, the quality of the clock and data input signals is very important to achieve optimum performance. Operating the AD9754 and corresponding digital power supply (DVD) with reduced logic swing results in the lowest data feedthrough and on-chip digital noise. The drivers for the digital data interface circuits should be specified to meet the AD9754's minimum setup and hold times and its required minimum/maximum input logic level thresholds.

Digital signal paths should be kept short and run-length matched to avoid propagation delay mismatch. Inserting a low value resistor network (ie, 20Ω to 100Ω) between the AD9754 digital input and the driver output may help reduce any overshoot and ringing at the digital input that causes data feedthrough. For longer run lengths and higher data update rates, stripline technology with appropriate termination resistors should be considered to maintain a "clean" digital input.

The external clock driver circuit should provide the AD9754 with a low jitter clock input that meets the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter, which will appear as phase noise in a reconstructed waveform. Therefore, the clock input should be driven by the fastest logic family suitable for the application.

Note that the clock input can also be driven by a sine wave centered around a digital threshold (i.e. dvdd/2) and meeting min/max logic thresholds. This usually results in a slight degradation of phase noise, which becomes more pronounced at higher sampling rates and output frequencies. Also, at higher sample rates, the 20% tolerance of digital logic thresholds should be considered, as it will affect the effective clock duty cycle and subsequently reduce the required data setup and hold times.

Input Clock and Data Timing Relationship

The signal-to-noise ratio in a DAC depends on the relationship between the position of the clock edge and the point in time at which the input data changes. The AD9754 is positive edge-triggered and therefore exhibits signal-to-noise sensitivity as data transmission approaches this edge. In general, the purpose of applying the AD9754 is to make data transitions close to the negative clock edge. This becomes more important as the sample rate increases. Figure 23 shows the signal-to-noise ratio versus clock position.

sleep mode operation

The AD9754 has a power-down feature that shuts down the output current and reduces the supply current to less than 8.5 mA over the specified supply range and temperature range of 2.7 V to 5.5 V. This mode is activated by applying a logic level '1' to the sleep pin. This digital input also contains an active pull-down circuit that ensures that the AD9754 remains enabled if this input is left open. The AD9754 takes less than 50 nanoseconds to power down and about 5 microseconds to restore power.

Power consumption

The power consumption PD of the AD9754 depends on several factors, including: (1) AVDD and DVD, supply voltage; (2) IOUTF, full-scale current output; (3) FClock, update rate; (4) reconstructed digital input waveform . Power dissipation is proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. iavdd is proportional to ioutfs, as shown in Figure 24, and is not sensitive to fclock.

Instead, the idvdd relies on the digital input waveform, fclock, and the digital power dvdd. Figures 25 and 26 show idvdd as a function of the full-scale sine wave output ratio (fout/fclock) for various update rates at dvdd=5v and dvdd=3v. Notice how the idvdd is reduced more than 2x when the dvdd is reduced from 5v to 3v.

AD9754 Application

output configuration

The following sections describe some typical output configurations of the AD9754. Unless otherwise specified, ioutfs is assumed to be set to nominally 20mA. For applications requiring the best dynamic performance, a differential output structure is recommended. Differential output configurations can include rf transformer or differential op amp configurations. The transformer configuration provides the best high frequency performance and is recommended for any application where AC coupling is allowed. The differential op amp structure is suitable for applications requiring DC coupling, bipolar output, signal gain and/or level shifting.

The single-ended output is suitable for applications requiring a unipolar voltage output. If iouta and/or ioutb are connected to an appropriately sized load resistor rload (acom for short), a positive unipolar output voltage results. This configuration may be more suitable for single-supply systems that require a DC-coupled, ground-referenced output voltage. Alternatively, the amplifier can be configured as an iv converter, converting either iouta or ioutb to a negative unipolar voltage. This configuration provides the best DC linearity since iouta or ioutb remains on virtual ground. Note that iouta provides slightly better performance than ioutb.

Transformer differential coupling

An RF transformer can be used to perform differential-to-single-ended signal conversion, as shown in Figure 27. The differentially coupled transformer output provides optimum distortion performance for output signals whose spectral content is within the transformer passband. rf transformers such as microcircuit t1-1t provide excellent rejection of common mode distortion (ie even harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios can also be used for impedance matching purposes. Note that the transformer only provides AC coupling.

The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary DC current paths for IOUTA and IOUTB. The complementary voltages present at iouta and ioutb (ie vouta and voutb) swing symmetrically around Acom and should remain within the output compliance range specified by the AD9754. The differential resistor rdiff can be plugged into applications where the output of the transformer is connected to the load rload through a passive reconstruction filter or cable. The rdiff is determined by the impedance ratio of the transformer and provides proper power termination, resulting in a low vswr. Note that about half of the signal power will be dissipated through the rdiff.

Differential using op amp

Op amps can also be used to perform differential-to-single-ended conversions, as shown in Figure 28. The AD9754 is configured with two 25Ω equal load resistors rload. The differential voltage developed on iouta and ioutb is converted to a single-ended signal by a differential op-amp configuration. Optional capacitors can be installed on iouta and ioutb to form a true pole in the low pass filter. The addition of this capacitor also improves the op amp's distortion performance by preventing the DAC's high spin output from overloading the op amp's input.

The common-mode rejection of this configuration is usually determined by resistor matching. In this circuit, the differential op-amp circuit is configured to provide some additional signal gain. The op amp must operate from dual supplies because its output is about ±1.0V. High-speed amplifiers, such as the AD8055 or AD9632, are capable of maintaining differential Figure 28. DC differential coupling that uses the performance of the AD9754 op amp should be chosen while meeting other system-level goals (ie, cost, power). When optimizing this circuit, consider the op amp's differential gain, gain-setting resistor value, and full-scale output swing capability.

The differential circuit shown in Figure 29 provides the necessary level shifting required for a single supply system. In this case, AVDD, which is the positive analog supply for the AD9754 and the opamp, is also used to level shift the AD9754's differential output to the mid-supply (ie AVDD/2). The AD8041 is an op amp suitable for this application.

Single-ended unbuffered voltage output

Figure 30 shows the AD9754 configured to provide a unipolar output range of approximately 0 V to +0.5 V for a double-terminated 50Ω cable because the nominal full-scale current IOUTF of 20mA flows through an equivalent load of 25Ω. In this case, rload represents the equivalent load resistance seen by iouta or ioutb. Unused outputs (iouta or ioutb) can be connected to acom directly or via a matching rload. Different ioutfs and rload values can be chosen as long as the positive compliance range is met. Another consideration in this mode is integral nonlinearity (inl), as described in the Analog Output section of this datasheet. For best inl performance, a single-ended buffered voltage output structure is recommended.

Single-ended buffered voltage output configuration

Figure 31 shows a buffered single-ended output configuration where op amp U1 performs an IV conversion on the AD9754 output current. U1 keeps iouta (or ioutb) at virtual ground, minimizing the effect of nonlinear output impedance discussed in the analog output section on the DAC's inl performance. While this single-ended configuration typically provides the best DC linearity performance, its AC distortion performance at higher DAC update rates may be limited by the u1's ability to spin. U1 provides a negative unipolar output voltage whose full-scale output voltage is simply the product of RFB and IOUTF. The full-scale output should be set within the voltage output swing capability of U1 by adjusting IOUTF and/or RFB. The improvement in AC distortion performance may result in a reduction in ioutfs because the signal current u1 that needs to be received will then be reduced.

Power and Grounding Considerations, Power Denial

Many applications require high speed and high performance under less than ideal operating conditions. In these circuits, the realization and structure of the printed circuit board design is as important as the circuit design. Appropriate RF techniques must be used for equipment selection, placement and wiring, as well as power bypassing and grounding to ensure optimum performance. Figure 39-44 illustrate the recommended printed circuit board ground, power, and signal plane layouts implemented on the AD9754 evaluation board.

One factor that measurably affects system performance is the ability of the DAC output to reject DC variations or AC noise superimposed on analog or digital DC distribution (ie AVDD, DVDD). This is called the Power Supply Rejection Ratio (PSRR). The resulting performance of the dac corresponds directly to the gain error associated with the dac's full-scale current, ioutfs, for DC changes in the supply. AC noise on DC power supplies is common in applications where power distribution is produced by switching power supplies. Typically, switching power supply noise occurs in the spectral range of tens of kHz to several MHz. Over this frequency range, the PSRR of the AD9754 AVDD supply versus frequency is shown in Figure 32.

NOTE: The units in Figure 32 are (Amps out)/(Volts in). Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. Therefore, the voltage noise on the DC supply will add to the desired output in a non-linear fashion. Due to the relative sizes of these switches, psrr is very code-dependent. This creates a mixing effect that modulates low frequency power supply noise to higher frequencies. Worst-case psrr occurs when full-scale current is directed to one of the differential DAC outputs. Therefore, the psrr measurement in Figure 32 represents the worst case where the digital input remains static and a full-scale output current of 20 mA is directed to the dac output being measured.

Give an example of the effect of power supply noise on an analog power supply. Assuming a switching regulator with a switching frequency of 250 kHz produces 10 mV rms of noise, all this noise is concentrated at 250 kHz for simplicity (i.e. ignoring harmonics). To calculate how much of this unwanted noise will appear as current noise imposed on the dac full-scale current ioutfs, psrr (units: db) must be determined at 250khz using Figure 32. Calculate the given psrrrload such that the units of psrr are converted from a/v to V/V, adjusting the curve in Figure 32 (RLoad) by a scaling factor of 20 × logarithm. For example, if the rload is 50Ω, the psrr decreases by 34 db (ie, the psrr of the DAC at 1 mhz, which is 74 db in Figure 32, becomes 40 db vout/vin).

In any high-speed, high-resolution system, proper grounding and decoupling should be the primary goal. The AD9754 has separate analog and digital power and ground pins to optimize the management of analog and digital ground currents in the system. In general, the analog power supply avdd should be separated from the analog common acom, as close as possible to the chip. Likewise, the digital power dvdd should be physically separated from the dcom as much as possible.

For those applications that require a single +5V or +3V supply for both analog and digital supplies, the circuit shown in Figure 33 can be used to generate a clean analog supply. The circuit consists of a differential lc filter with separate power and return lines. Lower noise can be achieved with low esr type electrolytic and tantalum capacitors.

application

Keeping power and ground noise low is the key to getting the best results from the AD9754. When implemented properly, ground planes can perform a range of functions on high-speed circuit boards: bypassing, shielding current transfer, and more. In a mixed-signal design, the analog and digital parts of the board should be distinct from each other, the analog ground plane should be limited to the area covering the analog signal traces, and the digital tal ground plane should be limited to the area covering the digital interconnects.

All analog ground pins for DACs, references, and other analog components should be connected directly to the analog ground plane. The two ground planes should be connected via a 1/8 to 1/4 inch wide path below the DAC or within 1/2 inch to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted on the critical signal path. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal and power feed.

It is also recommended to use wide rungs or planes in power line routing. This does double duty: providing low series impedance power to the part, and some "free" capacitive decoupling for the proper ground plane. Care must be taken in the layout of the signal and power-ground interconnects to avoid causing external voltage drops in the signal-ground path. It is recommended that all connections be short, direct, and as close to the package as possible to minimize the sharing of conduction paths between different currents. Stripline technology with appropriate terminating resistors should be considered when run lengths exceed one inch. The necessity and value of this resistor will depend on the logic family used.

For a more detailed discussion of the implementation and construction of high-speed, mixed-signal printed circuit boards, see Application Notes AN-280 and AN-333 for Analog Devices.

Multitone Performance Considerations and Characterization

The frequency-domain performance of high-speed DACs has traditionally been characterized by analyzing the reconstructed full-scale (i.e., 0 dbfs) spectral output, single-tone sine waves at specific output frequencies, and update rates. While this characteristic data is useful, it is often insufficient to reflect the performance of the DAC for reconstructed multi-tone or spread-spectrum waveforms. In fact, evaluating the spectral performance of a dac using a full-scale single tone at the highest specified frequency (ie, fh) of a band-limited waveform usually represents the "worst-case" performance of the dac for that given waveform. In the time domain, this full-scale sine wave represents the lowest peak rms ratio or crest factor (ie v peak/v rms ) that the band-limited signal will encounter.

Predistort the digital input signal of the DAC to compensate for nonlinearities associated with subsequent analog components in the signal chain. For example, signal compression associated with the power amplifier can be compensated by predistorting the digital input of the dac using the inverse nonlinear transfer function of the power amplifier. In both cases, the performance of the DAC at reduced signal levels should be carefully evaluated.

A full-scale monotone will cause all the dynamic and static nonlinearities present in the DAC that cause distortion in the DAC and thus the performance of the SFDR. Referring to Figure 3, the dynamic nonlinearity of any DAC (i.e., AD9754) tends to dominate as the frequency of the reconstructed full-scale single-tone waveform increases, contributing to the attenuation of its SFDR performance. However, unlike most DACs that employ an R-2R ladder for low-bit current segmentation, the AD9754 (and other TXDAC members) show improvements in distortion performance as the amplitude of the single tone is reduced from its full-scale level. If the sfdr performance is compared to frequencies at different amplitudes (i.e. 0 dbfs, -6 dbfs and -12 dbfs) and the sampling rates shown in Figures 4 to 7, this difference in distortion performance at reduced signal levels The improvement is obvious. Maintaining good "small-scale" linearity over the full range of the DAC transfer function is also critical to maintaining good multi-tone performance.

Although describing the multi-tone performance of a DAC is often application-specific, it is also possible to gain insight into a DAC by evaluating the swept power (i.e. amplitude) performance of a DAC for single, dual, and multi-tone test vectors at different clock rates and carrier frequencies. Learn more about potential performance. The DAC is evaluated at different clock rates when reconstructing a particular waveform whose amplitude is reduced in 3dB increments from full scale (i.e. 0 dbfs). For each specific waveform, graphs showing sfdr (over nyquist) performance versus amplitude can be generated at different test clock rates as shown in Figure 9-11. Note that the carrier-to-total locking ratio remains the same in each figure. In each case, an improvement in sfdr performance can be seen when the amplitude is reduced from 0 dbfs to approximately -9.0 dbfs.

A multi-tone test vector may consist of multiple equally-amplitude, spaced carriers, each representing a channel within the defined bandwidth shown in Figure 37a. In many cases, one or more tones are removed so that the intermodulation distortion performance of the DAC can be evaluated. The nonlinearity associated with the DAC will produce spurious tones, some of which may fall back into the "empty" channel, limiting the channel's carrier-to-noise ratio. Depending on the spectral mask and filtering requirements of the system, other spurious components that fall outside the band of interest may also be important.

This particular test vector is centered on the Nyquist bandwidth (i.e. fclock/4) with a passband of fclock/16. Concentrating the pitch in the lower region (i.e. fclock/10) will result in an increase in performance, while concentrating the pitch in the higher region (i.e. fclock/2.5) will result in a decrease in performance.

applications VDSL applications using the AD9754

Very high frequency digital subscriber line (vdsl) technology has developed rapidly in applications requiring short distance data transmission. Using qam modulation to transmit data in multiple discrete tones, higher data rates can be achieved.

As with other multi-tone applications, each vdsl tone is capable of sending a given number of bits according to the signal-to-noise ratio (SNR) in the narrow band surrounding that tone. The tones are evenly distributed in the range of a few kHz to 10 MHz. At the high frequency end of this range, performance is often limited by cable characteristics and environmental factors such as external interference. Performance at lower frequencies is more dependent on the performance of the components in the signal chain. In addition to in-band noise, intermodulation from other tones can also potentially interfere with data recovery for a given tone. The two plots in Figure 35 represent a 500-tone missing binary test vector with frequencies evenly distributed between 400 Hz and 10 MHz. This test is usually done to determine if distortion will limit the number of bits transmitted in a tone. The test vector has a series of missing tones around 750 kHz (shown in Figure 35A) and a series of missing tones around 5 MHz (shown in Figure 35B). In both cases, the pseudo-free range between the transmit tone and the empty box is greater than 60 dB.

CDMA

Carrier Division Multiple Access (cdma) is an over-the-air transmit/receive scheme in which the signal in the transmit path is modulated with a pseudorandom digital code (sometimes called a spreading code). The effect of this is to spread the transmitted signal over a wide spectrum. Similar to dmt waveforms, cdma waveforms containing multiple users can be described as having a high peak-to-average ratio (ie, crest factor), requiring a highly linear component in the transmit signal path. The bandwidth of the spectrum is defined by the cdma standard in use, and is achieved in operation by using spreading codes with specific characteristics.

Distortion in the transmission path can cause power to be transmitted out of the defined frequency band. The ratio of in-band transmit power to out-of-band transmit power is often referred to as adjacent channel power (acp). This is a regulatory issue because of the potential to interfere with other signals transmitted through the air. Regulators define a spectral shield outside the transmission band, and ACP must be below this shield. If distortions in the transmission path cause the acp to be higher than the spectral mask, filtering or different component selections are required to meet the mask requirements.

Figure 36 shows an example of the AD9754 used in a W-CDMA transmitter application using the AD6122 CDMA 3V transmitter IF subsystem. The AD6122 features features such as external gain control and low distortion features that are advanced adjacent channel power (ACP) requirements for WCDMA.

Figure 37 shows the AD9754 reconstructed wideband, or W-CDMA test vector, with a bandwidth of 5 MHz, a center frequency of 15.625 MHz, and a sampling rate of 62.5 msps. The acp for a given test vector is measured at 70db.

AD9754 Evaluation Board Overview

The AD9754-EB is an evaluation board for the AD9754 14-bit DAC converter. In any application requiring high-resolution, high-speed conversion, the user can easily and efficiently evaluate the AD9754 through careful attention to layout and circuit design, combined with the prototyping area.

This board allows the user the flexibility to operate the AD9754 in various configurations. Possible output configurations include transformer coupled, resistor terminated, inverting/non-inverting, and difference amplifier outputs. The digital inputs are designed to be driven directly from various word generators, with an on-board option to add a resistor network to terminate with an appropriate load. Provisions are also made to operate the AD9754's internal or external reference or to exercise the power-down function.