The Spartan-II 2.5V field programmable gate array family provides users with high performance, rich logic resources and a rich feature set at a very low price. This six-person family offers system door densities ranging from 15,000 to 200,000. System performance supports up to 200 MHz.
Spartan II devices offer more gates, I/Os and features per dollar than other FPGAs by combining advanced process technology with a streamlined Virtex-based architecture. Features include block RAM (up to 56K bits), distributed RAM (up to 75264 bits), 16 selectable I/O standards, and 4 DLLs. Fast, predictable interconnects mean successive design iterations continue to meet timing requirements.
The Spartan II family is a superior alternative to mask-programmed ASICs. FPGAs avoid the initial costs, lengthy development cycles and inherent risks of traditional ASICs. Additionally, FPGA programmability allows design upgrades in the field without hardware replacement (not possible with ASIC).
Features 2nd generation ASIC replacement technology - Density up to 5292 logic cells, up to 200,000 system gates - Streamlined functions based on Virtex architecture - Infinite reprogrammability - Very low cost system level functions - Selectram + Hierarchical memory: 16-bit/ lut distributed ram configurable 4k-bit block ram fast interface to external ram - fully pci compliant - low power segment routing architecture - proven full readability/observability - dedicated carry logic for high speed operations - Dedicated multiplier support - Cascaded chaining for wide input functions - Numerous registers/latches with enable, set and reset functions - Four dedicated dlls for advanced clock control - Four main low-skew globals Clock Distribution Net - IEEE 1149.1 Compliant Boundary Scan Logic Versatile I/Os and Packages - Low Cost Packages for All Densities - Footprint Compatibility in Family Common Packages - 16 High Performance Interface Standards - Hot Swap Compact PCI Friendly - Zero Retention Time Simplified System Timing Fully Supported by Powerful Xilinx Development System - Base ISE Series: Fully Integrated Software - Alliance Series: For 3rd Party Tools - Fully Automated Mapping, Placement and Routing Overview
The Spartan II family of FPGs features a regular, flexible, programmable Configurable Logic Block (CLB) architecture surrounded by programmable input/output blocks (IOBs). There are four Delay Locked Rings (DLLs), one at each corner of the die. Two columns of block RAM are located on opposite sides of the die, between the CLB and IOB columns. These functional elements are interconnected through a robust hierarchy of versatile routing channels.
Spartan II FPGAs are customized by loading configuration data into internal static memory cells. An infinite number of reprogramming is possible using this method. The stored values in these cells determine the logic function and interconnection implemented in the FPGA. Configuration data can be read from an external serial prom (master serial mode) or written to the FPGA in slave serial, slave parallel or boundary scan mode.
Spartan II FPGAs are typically used in high-volume applications, and the versatility of a fast programmable solution adds to the benefits. Spartan II FPGAs are ideal for shortening product development cycles while providing a cost-effective solution for high-volume production.
Spartan Type II FPGAs enable high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan II devices offer system clock rates up to 200 MHz. Spartan II FPGAs provide the most cost-effective solution while maintaining leading performance. In addition to the traditional advantages of high-density programmable logic solutions, Spartan II FPGAs provide on-chip synchronous single- and dual-port RAM (block and distributed forms), dynamic link library clock drivers, programmable settings on all flip-flops, and reset, fast carry logic and many other functions.
The Xilinx XC17S00A PROM family is recommended for serial configuration of Spartan II FPGAs. The In-System Programmable (ISP) XC18V00 PROM family is recommended for parallel or serial configuration.

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