Features: AD7776: single channel; AD7777: 4 channels; AD7778: 8 channels; fast 10-bit adc: 2.5ms worst case; +5V only; half-scale conversion option; fast interface port; power down mode.

Application: hard disk servo; instrument.

General Instructions

The AD7776, AD7777, and AD7778 are a family of high-speed, multi-channel, 10-bit ADCs primarily used for head positioning servos in r/w high-density hard disk drives. They feature unique input signal conditioning that makes them ideal for this single-supply application.

The input channels can be sampled independently, or any two selected channels can be sampled simultaneously, by setting a one-bit version of the AD7777 and the eight-channel version of the AD7778 in the control register within the four channels. For all versions, the specified input signal range is in vbias±vswing format. However, if the rtn pin is biased at 2v, say the analog input signal range for all inputs becomes the 0 V to +2 V channel. This section details this changing the analog input voltage range. The voltage Vbias is the offset of the ADC midpoint code from ground supplied by a user-available on-board reference (re-output) or applied to the Reffin via an external voltage reference. The full scale range (FSR) of the ADC is equal to 2 vertical wings, which are nominally equal to refin/2. Additionally, the value of refin is converted when placed in half-scale conversion mode. This allows the channel offset to be measured.

Control register loading and ADC register reading, channel selection and conversion initiation are controlled by the µP. The two complementary coded ADCs easily connect to standard 16-bit MPU bus microprocessor control lines through their 10-bit data ports and standard interface.

The AD7776/AD7777/AD7778 are fabricated in a Linear Compatible CMOS (LC2) process. An advanced hybrid process combines precision bipolar circuits and low power CMOS logic. The AD7776 is available in a 24-pin SOIC package; the AD7777 is available in 28-pin DIP and 28-pin SOIC packages; the AD7778 is available in a 44-pin PQFP package.

Circuit Description

ADC transfer function

An input signal of the form vbias±vswing is required for all versions. This VBIAS signal level operates as a pseudo ground and all input signals must be referenced. The vbias level is determined by the voltage applied to the refin pin. This can be driven by an external voltage source, or alternatively, an on-board 2 V reference can be used when re-outputting. The amplitude of the input signal swing is equal to vbias/2 (or refin/2) and is set internally. When refin is 2v, the analog input signal level changes from 1v to 3v, that is, 2±1v. Figure 5 shows the transfer function of the ADC and its relationship to vbias and vswing. The ADC's half-scale binary code, 000 hex (00 0000 0000 binary), appears at an input voltage equal to VBIAS. The ADC's input full-scale range is equal to 2vswing, so positive full-scale transitions (1fe to 1ff) occur at a voltage equal to vbias+vswing – 1.5 lsbs, and negative full-scale code transitions (200 to 201) occur at vbias –vswing +0.5 lsbs voltage.

control register

The control register is 10 bits wide and can only be written. At power-up, all locations in the control register are automatically loaded with 0s. For the single-channel AD7776, the CR0 to CR6 locations of the control registers are "don't care". For the quad AD7777, the CR2 and CR5 positions are "don't care".

CR0- CR2: Channel address location. Determines which channel will be selected and converted for single-channel operation. For simultaneous sampling operations, CR0–CR2 hold the address of one of the two channels to be sampled.

ADC conversion start timing

Figure 6 shows the working waveform for starting the con-version cycle. On the rising edge of WR, the conversion cycle begins with the capture and tracking of the selected ADC channels AIN1–8. The analog input voltage is held for 40ns (typically) after the first rising edge of clkin after four complete clkin cycles. If td in Figure 6 is greater than 12ns, the falling edge of clkin as shown will be considered the first falling clock edge. If td is less than 12ns, the first falling clock edge to be recognized does not occur until one cycle later.

After "hold" on the analog input, two full clkin loops are allowed to be used to solve the problem before making the msb decision. The actual decision point occurs about 40ns after the rising edge of clkin, as shown in Figure 6. The second msb decision also allows two clkin loops. Subsequent bit decisions are made approximately 40 ns after each rising edge of clkin until the conversion is complete. At the end of the conversion, if a conversion has been requested (cr6=0), the busy/int line changes state (programmed by cr9), and the sar content is transferred to the first register, adcreg1. The synthetic aperture radar is then reset, ready for a new conversion. If synchronous sampling has been requested (cr6=1), busy/int is output, and the ADC automatically starts the second conversion. At the end of the conversion, the busy/int line changes state (as programmed by cr9) and the sar content is transferred to the second register, adcreg2.

track and hold

A track-and-hold (T/H) amplifier on the analog input of the AD7776/AD7777/AD7778 allows the ADC to accurately convert an input sine wave of 2V peak amplitude to a frequency of 189 kHz, which is the rate when the ADC is operating at its maximum throughput rate of 378 kHz. Nyquist frequency. This maximum conversion rate includes conversion time and the time between conversions. Because the input bandwidth of trackand hold is much larger than 189khz, the input signal should be band limited to avoid folding unwanted signals into the band of interest.

power failure

The AD7776/AD7777/AD7778 can be placed into power-down mode by simply writing a logic high bit to the control register, location CR8. The following changes take effect immediately after writing a "1" to location CR8:

(1), any ongoing conversion will be terminated.

(2) If a conversion is in progress, the leading edge of wr imedi - sets the busy/int output to high.

(3), close all linear circuits.

(4) Re-output the output to stop driving, and pull it to the analog ground weakly (5 kΩ).

The control inputs CS, WR, and RD maintain their purpose when the AD7776/AD7777/AD7778 are powered down. If no conversion occurs when the AD7776/AD7777/AD7778 is placed in power-down mode, the contents of the ADC registers, ADCReg1 and ADCReg2, remain readable during power-down. When returning to normal operating mode, a new conversion (or conversion, depending on CR6) will be started automatically. On completion, the invalid conversion result is loaded into the ADC register, losing the previous valid result.

To achieve the lowest possible power consumption in power-down mode, special attention must be paid to the state of digital and analog inputs and outputs:

(1) Since each analog input channel has a resistor divider to ground, its input resistance does not change between normal mode and power-down mode, so drive the analog input signal to 0 V or as close to 0 V as possible will minimize the power dissipated in the input signal conditioning circuit.

(2) Similarly, the REFIN input sees a resistive divider to AGND whose input resistance does not change between normal mode and power-down mode. If using an external reference, driving the reference input to 0 V or as close to 0 V as possible will minimize the power dissipated in the input signal conditioning circuit.

(3) Since the re-output pin is usually pulled to agnd through an A5 kΩ resistor, any voltage that this output may be pulled above 0 V by an external circuit will consume unnecessary power.

(4) The digital inputs cs, wr and rd should all be kept at vcc or as close as possible. CLKIN should be placed as close to 0 V or VCC as possible.

(5) Since the busy/int output is actively driven to logic high, any 0 V load on this pin will dissipate power.

The AD7776/AD7777/AD7778 exits power-down mode when a logic '0' is written to location CR8 of the control register. Note that the contents of other locations in the control registers will be preserved when the device is powered down, and will be valid when power is restored. However, after power down, the full contents of the control registers can be reloaded without any additional instructions.

Microprocessor Interface Circuit

The AD7776/AD7777/AD7778 family of ADCs is designed to interface with digital signal processors (DSPs) such as the ADSP-2101, ADSP-2105, TMS320 family and 80C196 family of microcontrollers.

Figure 7 shows the AD7776/AD7777/AD7778 interfacing with the 20.5 MHz tms320c10 and 25 MHz tms320c14.

Figure 8 shows the interface to the tms320c25 at 40 MHz.

Note: This interface requires a wait state. The ADSP-2101-50 and ADSP-2105-40 interfaces are shown in Figure 9. Both machines require a wait state.

Figure 10 shows the interface to 80C196KB@12MHz and 80C196KC@16MHz. 16MHz machines require a wait state. The 80C196 is configured to operate using a 16-bit multiplexed address/data bus.

Note: While a session is in progress, a read command to any device will immediately stop the conversion and return unreliable data over the data bus.

design information

layout hints

Make sure that the layout of the printed circuit board separates the digital and analog grounds as much as possible. Be careful not to run any digital tracks next to the analog signal tracks. Analog input with rtn protection (screen).

Establish a single-point analog ground separate from the logic system ground as close to the AD7776/AD7777/AD7778 as possible. The RTN and AGND pins and all other signal grounds on the AD7776/AD7777/AD7778 should be connected to this single-point analog ground. In turn, this star ground should be connected to digital ground at only one point (preferably at the low impedance source itself).

Low impedance analog and digital power commons are important for proper operation of the device, so keep the foil width of these tracks as wide as possible.

To ensure a low impedance +5V supply at the actual VCC pin, it will be necessary to use a bypass capacitor from the pin itself to DGND. A 4.7µf tantalum capacitor in parallel with a 0.1µf ceramic capacitor is sufficient.

ADC damage

Executing a read command to the AD7776/AD7777/AD7778 during a conversion will immediately stop the Con-version and return invalid data over the data bus.

The INT output pins should be closely monitored and all read instructions to the AD7776/AD7777/AD7778 should be prevented when the output shows that a conversion is in progress.

Executing a write command to the AD7776/AD7777/AD7778 during a conversion immediately stops the converter-sion, and the falling edge of wr drives the busy/int output high. The analog input is sampled as normal and a new conversion sequence is initiated (depending on CR6).

A/D Converter Conversion Time

Although only 14 clkin cycles are required per conversion, it may take 4.5 to 5.5 clkin cycles to obtain an analog signal

Enter after the wr input goes high and before any transitions begin.

the term

Relative accuracy

For the AD7776, AD7777, and AD7778, relative accuracy, or endpoint nonlinearity, is the maximum deviation (LSB) of the ADC's actual code transition point relative to the straight line drawn between the ADC transfer function endpoints.

Differential nonlinearity

Differential nonlinearity is the difference between the measured variation and the ideal 1lsb variation of any two adjacent codes. The specified maximum differential nonlinearity is ±1 lsb, ensuring no missing codes.

offset error

For an ideal 10-bit ADC, the output code with an input voltage equal to vbias should be mid-scale. The offset error is the difference between the actual midpoint voltage of the mesoscale code and vbias, expressed in lsb.

Bias Error Matching

This is a measure of how well the offset offset errors of all channels track each other. Regardless of whether the channels are sampled independently or simultaneously, the offset offset error of any channel shall not match the offset offset error of any other channel by more than 10 lsb.

Positive and negative full-scale error

The ADC's input channels can be considered bipolar (positive, negative) input ranges, but refer to vbias (or refin) instead of agnd. The positive full-scale error of an ADC is the difference between the actual input voltage and the ideal input voltage (vbias+vswing-1.5lsb) required to produce a positive full-scale code conversion, expressed in lsb. Negative full-scale error also applies to negative full-scale code transitions, relative to the ideal input voltage for this transition (vbias – vswing + 0.5 lsb). Note that the full-scale error of the ADC input channels is measured after their respective offset offset errors are adjusted.

Positive and negative full-scale error matching

This is a measure of how well the full-scale errors of all channels track each other. Regardless of whether the channels are sampled independently or simultaneously, the full-scale error of any channel shall not be matched by more than 10 lsb from the corresponding full-scale error of any other channel.

short circuit current

This is defined as the maximum current that will flow into or out of the re-output pin if this pin is shorted to any potential between 0 V and VCC. This condition allows up to 10 seconds without exceeding the power consumption of the package.

Signal to Noise Ratio and Distortion Ratio, s/(n+d) Signal to Noise Ratio and Distortion Ratio s/(n+d) is the mean square value of the measured input signal and all other spectral components below the Nyquist frequency The ratio of the root sum, including harmonics, but excluding direct current. The value of s/(n+d) is in decibels.

total harmonic distortion

Total Harmonic Distortion is the ratio of the rms value of the first five harmonic components to the rms value of the full-scale input signal, expressed in decibels. For the AD7776/AD7777/AD7778, total harmonic distortion (THD) is defined as:

where v1 is the rms amplitude of the fundamental and v2, v3, v4, v5 and v6 are the rms amplitudes of the individual harmonics.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products of order (m+n) at the sum and difference frequencies of mfa+nfb, where m, n=0, 1, 2, 3. The intermodulation term refers to the intermodulation term for which m or n is not equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

Isolation between channels

Inter-channel isolation is a measure of the level of cross-talk between channels. It is measured by applying a full-scale 100 kHz sine wave signal to any one input channel and monitoring the remaining channels. The numbers given are the worst of all channels.

digital signal processing applications

In applications such as speech recognition, echo cancellation and adaptive filtering in digital signal processing (DSP), the dynamic characteristics of ADCs s/(n+d), thd and imd are crucial. The AD7776/AD7777/AD7778 are dynamically specified and have standard DC specifications. Since the track/hold amplifier has a wide frequency band, an antialiasing filter should be placed on the analog input to avoid aliasing of high frequency noise back into the band of interest.

The dynamic performance of the ADC is evaluated by applying a very low distortion sine wave signal to a single analog input sampled at 380.95khz. A Fast Fourier Transform (fft) plot or histogram is then generated from which the noise and distortion, harmonic distortion and dynamic differential nonlinearity data of the signal can be derived. Similarly, for intermodulation distortion, an input signal consisting of two pure sine waves of different frequencies is applied to the ad7776/ad7777/ad7778.

Figure 11 shows a single-channel 2048-point FFT plot of the AD7778 with an input signal of 99.88 kHz. The signal-to-noise ratio is 58.71db. It can be seen that most of the harmonics are buried in the noise floor. It should be noted that harmonics are taken into account when calculating s/(n+d).

The relationship between s/(n+d) and resolution (n) is expressed by the following formula:

This applies to ideal parts without differential or integral linearity errors. These errors will lead to the degradation of s/(n+d). By working backwards from the equation above, a measure of the ADC's performance in terms of the number of effective bits (n) can be obtained:

Figure 12 shows the effective number of bits versus frequency for a single channel of the AD7778. The effective number of bits is usually 9.5.

Changing the Analog Input Voltage Range The analog input voltage range can be changed from a Vbias ± vswing format to a more traditional 0v to Vref range by biasing the RTN pin on Agnd. The new input range can be described as:

If 0 V≤Voffset≤1 V. To generate this range, the RTN pins must be biased (Refin – 2 Voffset). For example, if RTN is connected to REFOUT, then the analog input range becomes 0 V to 2 V. The ADC's fixed 2 V analog input voltage range can vary from 1 V to 3 V (RTN=0 V) to 0 V to 2 V (RTN=2 V), i.e., with proper biasing, 0.3 V to 0.3 V can be covered 2.3 V input signal range. In this mode, relative accuracy and differential nonlinearity performance remain largely unchanged, while signal-to-noise ratio and thd performance are typically 2-3db off standard.