Benefit: Fully optimized system efficiency. Higher levels of efficiency compared to traditional discrete methods are achievable components. Save up to 50% of PCB space compared to discrete solutions. higher frequency of operation. Simplifies system design and board layout. Reduce time component selection and optimization.

Features: 12V Typical Input Voltage Output Current Up to 18A500kHz Switching Frequency Internal Adaptive Gate Driver Integrated Bootstrap Diode Peak Efficiency >85% Under-Voltage Lockout Out-of-Phase Shutdown Output Disabled Thin SMD Package RoHS Compliant

General Description: The FDMF8705 is a fully optimized integrated 12V Driver Plus high current synchronous mosfet power stage solution for buck dc-dc applications. The device integrates a driver chip and two power mosfets, 8mm x 8mm, 56-pin, space-saving POWER88 8482 ; components. Fairchild Semiconductor Integrated Circuits The method utilizes a holistic solution to the dynamic performance of the drive field effect transistor, system inductance and resistance. The traditional discrete solution of the package parasite and the problem layout associated with it is greatly reduced. This comprehensive approach results in significant board space savings, thus maximizing footprint power density. This solution is based on the Intel™ DRMOS specification.

Applications: Desktop and server non-V core Buck converters. Gaming consoles and high-end CPU/GPU powered desktop systems. High Current DC-DC Point of Load (POL) Converter Networks and Telecom Microprocessor Voltage Regulators Small Voltage Regulator Modules

Operation Description Circuit Description: is a driver plus fet module optimized for synchronous buck conversion topology A single PWM input signal is all that is required to pre-drive the high-side and The low-side mosfets. Each part can drive the speed Up to 500khz. Low-side driver Low-side driver (LDRV) designed to drive a ground referenced low RDS() n-channel mosfet than an internal connection between VCIN and CGND. When the driver is set, the output of the driver is a 180 degree phase output. The PWM input is low when the driver fails. High-side driver The high-side driver (HDRV) is designed to drive float. The biasing of the N-channel mosfet high-side driver is developed by a lifter supply circuit, which is started by built-in diodes and external capacitors Doolin, VSWH supports PGND, allowing CBoot to charge up to through the internal diodes. When the PWM input starts high, the HDRV will start filling The gate on the high side during this transition, loads from CBOOT and is transported to Q1' as Q1 turns around, VSWH rises, forcibly pushes wine+vc+boot, which provides enough boost to complete the switching cycle, and Q1 is switched to VSWH by HDRV. That's charging to VCIN when VSWH falls to PGND. High-definition output The high-side gate is low during the PWM input stage when the driver fails. Adaptive Gate Drive Circuit The advanced design of the driver trim minimizes dead time shot conduction current senses the friction of the gate drives and adjusts, adaptively, to ensure they don't drive at the same time. Refer to Figure 24 and 25For the relevant timing waveforms. Prevents excessive adaptive circuitry during low-to-high transitions. Monitors the voltage at the LDRV PIN. When the PWM signal is high, Q2 starts transitioning after some propagation delay. Once, the LDRV PIN is at Downstream ~1.2V, Q1 Off to the High-to-Low Transition, Q1 Off to the High-to-Low Transition, Adaptive Circuit Monitor Loose, Q1 Off to the High-to-Low Transition, Q1 Off to the High-to-Low Transition Starts to exit after some breeding delay once down ~2.2v, Q2 starts to shift to adaptive delay TPDH (Additionally, vgs of Q1 is monitored. When VGS(Q1) is downstream discharge ~1.2v, a quadratic adaptive The delay is activated, after TPDH (LDRV), what results in Q2 being drivenOf SW State. This feature implements a guaranteed charge every switching cycle, especially where the power converter is sinking current, and the switching voltage does not drop at 2.2 Quadratic delay under V adaptive threshold Is longer than TPDH (LDRV)

Application Information Power Supply Capacitor Selection: For the power supply input (vcin) of the fdmf8705, a local ceramic bypass capacitor is recommended to reduce noise and provide peak current. Use at least 1µF, X7R or X5R capacitors. Place the capacitor close to the FDMF8705 vcincgnd pin. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (cboot) as well as an internal diode as shown. Selecting these components should be done after the high-side mosfet has been selected. Use the following formula to determine the required capacitance: where qg is the total gate charge of the high-side MOSFET, and ∏vboot is the voltage drop allowed by the high-side MOSFET driver. For example, the QGmosfet on the internal high voltage side is about 21nc@12vgs. The allowable sag is about 300 mV, and the required bootstrap capacitance is greater than 100 mV. Good quality ceramic capacitors must be used. The average diode forward current can be estimated if(avg) where fsw is the switching frequency of the controller. The peak surge current rating of the internal diodes in the circuit should be checked, as this depends on the equivalent impedance of the entire boot circuit, including the pcb lines. For applications requiring higher intermediate frequencies, an external diode can be used in parallel with the internal diode. Module power loss measurement and calculation module power loss test method. The loss of power is calculated as follows: Printed circuit board layout guidelines diagram. The FDMF8705 and key parts are shown. All high current paths such as vin, vswh, VOUT and GND copper should be short and wide for better stable current flow, heat dissipation and system performance. The following are guidelines that pcb designers should follow: 1. The input bypass capacitor should be close to the VIN and ground pins of the FDMF8705 which help reduce the input current ripple component caused by switching operations. 2. The minimum area of VSWH copper reduces switching noise emissions. The VSWH copper traces should also be wide enough to accommodate high currents. Other signal routing should be considered such as the pwm input and the path of the pilot signal taking care to avoid noise pickup from the vswh copper area. 3. The output inductor should be placed as close to the FDMF8705 as possible to reduce power loss due to copper traces. 4. Place ceramic bypass capacitors and boot capacitors close to the VCIN and pilot pins of the FDMF8705 to stabilize the power supply. Trace width and length should also be considered. 5. Use multiple vias on each copper area to interconnect the top, inner and bottom of each via to help smooth current and heat conduction. Vias should be relatively large and reasonably inductive.