Function description

LM5021 Over -line pulse width modulation (PWM) ultra -low start current (maximum 25μA) controller contains all required function current mode control to achieve low -standing power of the low -standing power control of the current mode control. Anti -gravity and positive power converter's jump period mode. The characteristics of LM5021 include a low-single-resistance programmable oscillator start current (25μA), which minimize power

The synchronous oscillator loss in the high voltage start network. Jump

The adjustable soft start -up loop mode can reduce the power consumption of optical power

Integrate the 0.7A peak door driver load for energy -saving applications (Energy Star #174; CECP, etc.). The additional functions include the direct optocoupler interface under the voltage lock, the cycle current limit, the maximum duty cycle limit (HICCUP mode overload protection is 80%, the slope COM LM5021-1 or LM5021-2 is 50%) compensation, Soft start and oscillator synchronization slope compensation (only LM5021-1) capabilities. High -performance 8 -stitched merging circuit transmission delay is less than 100ns and 1MHz under voltage lock (UVLO). It has a lagging capacity oscillator and uses a single cycle overcurrent protection resistor. Continuous interrupt mode of white space protection Mode current influenza response at the front of the edge

signal

Packaging: vssop-8 or PDIP-8

Electrical characteristics (1)

Standard surface specifications are applicable to TJ u003d+25 ° C, and black body specifications are suitable for the entire working joint

The temperature range. Unless there are other regulations: vin u003d 15V, RT u003d 44.2K .

(1) The minimum and maximum limit is 100%production test under 25 ° C. The statistical quality control (SQC) method within the working temperature range is specified through the correlation. Restricted to calculate the average shipment quality level (AOQL).

(2) Equipment heat limit may limit the available range.

Electrical characteristics (1) (continued)

Standard surface specifications are applicable to TJ u003d+25 ° C, and black body specifications are suitable for the entire work joint

The temperature range. Unless there are other regulations: vin u003d 15V, RT u003d 44.2K

Typical performance features

Unless unless Another provision: TJ u003d 25 ° C.

The launch circuit

For Figure 9, the input capacitor CVIN is used to make a trickle charging by starting the resistor RSTART, and the input voltage HV is applied to the rectifier AC input voltage. The VIN current consumed by LM5021 is only 18 μA (nominal value), while the capacitor CVIN was originally charged to the startup threshold. When the input voltage reaches the upper limit, VIN reaches the upper limit VIN UVLO threshold to 20V, and the internal VCC linear regulator is enabled. The VCC regulator will be connected until VIN drops to a lower UVLO threshold (12.5V lag) of 7.25V. When the VCC regulator is opened, the external capacitors at the VCC pin start to charge. The PWM controller, soft startup circuit and door drive are enabled when the VCC voltage reaches the VCC UVLO upper limit of 7V. VCC UVLO is a stagnation between the up and down threshold of 1.2V to avoid jitter during the transient state of the VCC pin. VCC UVLO turns on the switching power supply, and the energy is transmitted from the main power to the auxiliary power transformer winding. The partial pressure winding, as shown in Figure 9, provides electricity to the VIN pin to maintain the VCC regulator. The voltage provided should be 11V (the maximum value of the VCC regulating voltage plus the VCC regulator down voltage) to 30V (maximum work VIN voltage). The partial pressure winding should always be connected to the Vin pin, as shown in Figure 9. Do not connect the offset wounds on the VCC pin. The start sequence is that when the voltage of the bias is enough to maintain the VCC, the normal operating level is higher than the VCC UVLO threshold (typical value is 5.8V). LM5021 Design is used to enter the ultra -low start current used to enter the VIN pin. In order to complete this very low start current, the VCC regulator of the LM5021 is unique to the VCC regulator in other controllers compared with the VCC regulator used in other controllers. LM5021 is a specially designed application connected to the VIN pin with a partial pressure winding group, as shown in Figure 9. It is not recommended to connect the offset winding to LM5021. The size of the starting resistor not only affects the start time of the power supply, but also the power supply that affects the power supply is high because the resistor consumes power during normal working. The ultra -low start current of LM5021 allows large value starting resistors (up to 3 m ) to improve efficiency and reasonable startup time.

The relationship between the input capacitor CIN and VCC capacitor CVCC When the vehicle recognition number (VIN) reaches 20V, the internal VCC linear regulator is enabled. Since the CVIN to CVCC from the regulator can be calculated based on the following status, the VIN 'is the voltage on the CVIN immediately after the VCC regulator is charged. Δvin x cvin u003d Δvcc x CVCC

(20V -vin ’) CVIN u003d 8.5V CVCC

19.15V. The value of VCC capacitors can be small (less than 1UF) because itOnly provide a current with a short duration of the transient door driver. The size of the CVIN capacitor must provide a gate -drive current and static current

LM5021 current, until the transformer bias winding provides sufficient voltage to VIN to maintain the VCC voltage. The value of the CVIN capacitor can calculate the VCC UVLO threshold according to the working current of the VCC load at its output voltage. For example, if the LM5021 uses a grid charge (QG) to drive the average grille drive current of the external MOSFET25NC is QG X FSW, the FSW is the switching frequency. Suppose the switching frequency is 150kHz, and the average grille driver current is 3.75mA. Because IC consumes about 2.5mA working current to remove the grid current, the total current of the CVIN capacitor is the working current plus the gate charging current, which is 6.25mA. The CVIN capacitor must provide this current so that the transformer bias winding time is taken over. During the startup process, the voltage shall not be lower than the CV8.5V order or cycle will be restarted. The maximum allowable start time can be used to use this value for CVIN, and voltage changes allow VIN (19.15V – 8.5V) and VCC regulator current (6.25mA). The maximum time of T's maximum allowable bias winding is:

If the calculation value of TMAX is too small, it should be further increased to leave more time to leave more time Before the transformer bias winding is taken over and transports the working current to the VCC regulator. Increasing CVIN will increase from application rectifier AC power (HV in Figure 9) to VIN reaches 20V startup threshold. The initial charging time of CVIN is:

PWM comparator/slope compensation

PWM comparator to the circuit error voltage from the compensation pin from the compensation pin Compare. This COMP pin voltage is reduced by 1.25V, and then attenuated by the 3: 1 resistor. The design of the PWM comparator input bias voltage should ensure that the compensation pin is less than 1.25V, which will cause the controller to output. When the duty cycle is greater than 50%, the current control circuit is affected by the secondary resonance oscillation. By adding an additional fixed slope voltage slope signal (slope compensation) to the current detection signal, this can avoid oscillation. LM5021-1 Integrate this slope compensation by the slope signal to be generated by the oscillator and current influenza signal. The slope compensation is driven by the internal 1.8 k the resistor is driven by the current slope. It can increase the additional slope compensation to increase the resistance between the current detection filter capacitor and the CS pin, thereby increasing the voltage slope generated by the oscillator current slope. Because LM5021-2 cannot withstand a larger duty cycle by more than 50%, this device has no slope compensation function.

current limit/current influenza response

LM5021 provides a cycle -by -current over -current protection function. The current limit is set to 500 millivolves by the internal current detection comparator threshold. If the CS pin voltage plus the slope compensation voltage exceeds 500mV, the output pin pulse will be terminated immediately. It is recommended to install an RC filter for CS pin near LM5021 to attenuation from the door to the source of the transistor of the power field effect. CS pin capacitors are switched by internal switch at the end of each PWM clock cycle. The discharge switch is kept on, and the anterior edge of the 90 nS front edge is continued to attenuate the current influenza response transients that occur when the external power field effect tube is turned on. In addition to providing cutting -edge consumption, the circuit also detects the filter capacitance at the end of each cycle by discharging dynamic performance.

LM5021 CS comparator is very fast and can respond to short -time noise pulse. Points for layout are essential for current detection filters and detection resistors. The capacitors related to CS filter must be placed in a very close device and directly connected to the IC pin (CS and GND). If you now feel that the transformer is used, the two leads on the secondary side of the transformer should be connected to the sensor near IC. If the current fluid response resistor in the transistor source of the power field is used for current influenza, a low -induced resistor is required. In this case, all small -current -sensitive small current is connected to the IC, and then connected to the power ground (inductive resistance location) separately.

Synchronous and off the oscillator

A single external resistor connected between RT and GND pins sets the frequency of LM5021 oscillator. This LM5021-2 device has a maximum duty ratio of 50%, including an internal trigger to separate the oscillator frequency of 2. This method generates accurate 50%of the maximum work cycle limit. Because of this frequency division, the frequency of the oscillator of LM5021-2 is actually twice the frequency of the gate drive output (OUT). For the LM5021-1 device, the frequency of the oscillator and the working output frequency are the same. Set the expected output switch frequency (FSW). The RT resistance can be calculated based on the following formulas:

LM5021 can also be synchronized with the external clock. The frequency of the external clock must be higher than the self -excitement frequency of the RT resistance settings. The clock signal should be inserted into the RT pin with a 100PF capacitor with a capacitor coupling. The peak voltage level at the RT pin is required to detect the detection of the peak voltage level greater than the 3.8 volt synchronization pulse. The DC voltage of the RT resistor is adjusted to 2 volts internally. Therefore, the AC pulse superimposed on the RT resistor must have 1.8V or larger amplitude to successfully synchronize the oscillator. Synchronous pulse width is set between 15ns and 150ns from external components. Regardless of whether the oscillator runs freely or external synchronization, RT always needs a resistor. The RT resistor should be located very close to the device and directly connect to the pins of the LM5021 (RT and GND)Essence The door drive and maximum duty cycle limit LM5021 provides a door drive (OUT), which can generate two working cycle restrictions for 0.3A peak current and 0.7A current. The maximum output ratio of LM5021-1 is usually 80%option, which is accurate equal to 50%of the LM5021-2 option. The maximum duty cycle function of LM5021-2 is completed by an internal trigger to ensure the accurate duty cycle limit. Therefore, the frequency of LM5021-2 is twice the frequency of the PWM controller (OUT pin) switch. 80%of the LM5021-1 maximum duty cycle function is determined by the internal oscillator. The frequency of the internal oscillator of the LM5021-1 PWM controller is the same as the switching frequency.

Soft starting

Soft startup function allows power converters to gradually reach the initial steady -state working point, thereby reducing the boot pressure and current surge. Internal 22 μA current source is connected to the SS pin charging external capacitors. The capacitor voltage will rise slowly, limiting the period of compensation pins and duty -occupying ratio output pulse. Soft -boot capacitors are also used to generate continuous overload as the output of switching power.

The HICCUP mode overload current limit HICCUP mode is a method of overloading the power supply to prevent overheating and damage within the extension of the extension time. When the output failure is eliminated, the power supply will be automatically restarted.

Figure 10, Figure 11, and 12 illustrate LM5021 and related waveforms. During the start and normal operation, the external soft startup capacitor CSS provides a 22μA current source from the SS pin capacitor. When running normally, the soft startup capacitor continues to charge and eventually reaches the saturation voltage of the current source (nominal, VSS_OCV5.2 il). During the startup period, the COMP PIN voltage follows the SS capacitor voltage and gradually increases the current provided by the peak power supply. When the output of the switching power supply reaches the expected value, the voltage feedback amplifier controls the COMP signal (via optocoupler). Under normal circumstances, the operation of the COMP level is maintained in the intermediate voltage between 1.25V and 2.75V, and the circuit is adjusted by voltage control. When the compensation pin voltage is lower than 1.25V, the duty ratio is zero. When the salary level is higher than 2.75V, the duty cycle will be subject to the 0.5V threshold limit of the periodic current limit comparator. If the power supply output is overload, the regulating circuit needs to increase the current compensation pin control voltage. When the compensation pin exceeds the voltage detection threshold (VOVLD, nominal 4.6V), the SS capacitor CSS will be discharged by 10μA overloaded timer current source, IOVCS. If the COMP is kept above VOVLD, the SS capacitor discharge to the HICCUP mode threshold (VHIC, which is 4.6V), and the controller enters the interrupt mode. Then, the OUT pin is locked at the low SS capacitor discharge current from 10 μA to 0.25 μA, that is, the current current source of the dead area, IDCSEssence SS pin voltage slowly decreases until it reaches the restart threshold (VRST, nominal 0.3V). A new startup program is then charged to the capacitor CSS from the current source of 22 μA. Slow discharge from the interrupt threshold to the SS capacitor with a restarting threshold provides an extended shutdown time, thereby reducing continuous overload and components, including diode and MOSFET. The rest time mode can be calculated through the following formulas:

Example: TOFF u003d 808 ms, assuming that the CSS capacitance value is 0.047μF short -time intermittent overload is not It will trigger the HICCUP mode. The required overload duration interrupt response is set between the capacitor CSS, the 10μA mounting current source and the voltage difference between the SS pins and the HICCUP mode threshold. Figure 12 shows that the waveform of SS has a pins with a short -term overload condition. The overload time required to enter the HICCUP mode can be calculated based on the following formulas:

Example: T overload u003d 2.82 ms, assuming that the CSS capacitance value is 0.047 μF

]

Skip the cycle operation

Under the condition of light load, the efficiency of the switching power supply usually decreases with the relevant losses. The switch and work of the converter, the bias current becomes an important percentage of power to deliver the goods. The biggest part of the power loss is the switch loss driver -related switch loss drive and the external MOSFET grid charging. Each pulse width adjustment cycle consumes limited energy as MOSFET first and then close. These switching loss is proportional to the operating frequency. The circulation function of a springboard integration in the LM5021 controller reduces the efficiency of the average switching frequency switching and improves the efficiency of the average switching frequency switch. When the light load occurs, the compensation pin voltage decreases through the voltage feedback circuit to reduce the peak current provided by the controller. Refer to FIG. 13, PWM comparator input tracking COMP pins voltage through 1.25V levels and 3: 1 resistor division. When the COMP pin voltage drops, the input to the PWM comparator decreases proportionally. When the PWM comparator input drops to 125MV, the period of the period comparator detects the light load and disables the output pulse of the controller. The controller continues to skip the switching cycle until the output of the power supply decreases, and the COMP pin voltage increases to more output current. The number of jumping cycles depends on the frequency compensation network. In the end, when the voltage circuit is required, the compensation voltage will increase a larger current to maintain a stable output voltage. When the PWM comparator inputs more than 130mv (5mV lags), it will resume normal fixed frequency switching. A typical power design will generate a long jumping weekly interval of a short pulse output pulse. The average switching frequency in the jump cycle mode can be normalA small part of working frequency.By adding a offset voltage to the CS pin, you can disable the cycle operation mode (see Figure 14).The resistance division connected to the voltage voltage power supply is injected with 125mv displacement (minimum value) into the CS pin. The voltage on the compulsory PWM comparator will be greater than 125 millivolves, so as to disable the jump cycle comparator.