Features: Industry Standard Pinout 4.5-V to 18-V Operating Range at VDD=12V, 3-A Peak Sink/Source 2.4-A Sink/1.6-A Power Supply, 6 V Inverted Configuration (FAN3216) and Non- Inverted configuration (FAN3217); if no input, internal resistor shuts down driver 12 ns/9 ns typical rise/fall time (1 nf load) 20 ns typical propagation delay time matched to another channel with 1ns TTL input threshold MillerDrive 8482 ; technology Dual Current Capability of Parallel Channels Standard SOIC-8 Package Ambient Temperature -40°C to +125°C AEC-Q100 (F085 Version) Qualified Automotive

Application: Software Itch Mode Power Supply High Efficiency mosfet Switch Itch Synchronous Rectifier Circuit DC-DC Converter Motor Control Automotive Qualification System (Version F085)

Description: The FAN3216 and FAN3217 dual 2 A gate drivers are designed to drive N-channel enhancement mode mosfet applications in low side sw itch applications to provide high peak current pulses in short sw intervals. They both have TTL input thresholds. Internal circuitry works by keeping the output low until the supply voltage is within the operating range. In addition, the propagation delay between the driver function and the internal A and B channels requires application timing of dual gate drivers, such as synchronous rectifiers. This also supports twice the current capacity of connecting TWO drivers in parallel to efficiently drive a single mosfet. The FA N3216/17 driver contains the architecture of the MillerDrive™ final output stage. This bipolar mosfet combination minimizes switching losses at the miller platform level of the mosfet switch while providing rail-to-rail voltage switching and reverse current capability. The FAN3216 provides two inverting drivers and the fan3217 provides two non-inverting drivers. Both are offered in a standard 8-pin SOIC package.

Application Information: Input Threshold The FAN3216 and FAN3217 drivers consist of TWO of the same channel rated current that can be used independently or in parallel with a single current capacity. Input thresholds conform to industry standard ttl logic thresholds independent of VDD voltage, and have a hysteresis voltage of approximately 0.4V. Levels allow input from a range of voltages in excess of 2V. Input logic signal levels are considered logically high. The drive signal input for TTL should have fast rising and falling edges with a slew rate of 6 V/µs or faster, so the rise time from 0 to 3.3 V should be less than or equal to 550 ns. As the slew rate decreases, circuit noise can cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, resulting in unstable operation. The quiescent supply current is shown in the figure n in the IDD (static) typical performance characteristics, each curve is produced with two inputs floating and two outputs resulting in low EST quiescent IDD current low. For other states, an additional current through the 100K resistors on the input and output is shown in the block as N parts schematic. In these cases, the actual quiescent IDD current is derived from the curve plus this additional current. MillerDrive™ Door Drive Technology The FA N3216 and FA N3217 door drives incorporate the MillerDrive™ architecture shown in Figure 31. For the output stage, a combination of bipolar and mos devices provides large current voltage and temperature variations over the supply range. Bipolar devices do most of the current output between 1/3 of the vdd and mos devices pull the output to the high or low rail. The MillerDrive™ architecture is designed to act as an on/off process through the gate-to-drain capacitance mosfet in the miller plateau region. For zero-voltage switching applications with MOSFET switching intervals, the driver delivers high peak current even if the Miller plateau does not exist. This often happens in synchronous rectifier applications because the diodes are usually switched on when the mosfet is switched on. The output pin slew rate is determined by the V dd voltage and the load of the output. It's not user adjustable, but if the current gets slower rise or fall times, you can increase the series resistance needed at the mosfet gate.

Undervoltage Lockout The FAN321X startup logic is optimized to drive the ground referenced N-channel MOSFET lockout (UVLO) function at low voltages, ensuring that the IC starts up in an orderly manner. When VDD rises, but falls below the 3.9V operating level, the circuit keeps the output low regardless of the state of the input pins. After the part is activated, the supply voltage must drop by 0.2 V for the part to shut down. This hysteresis helps prevent the low VDD supply voltage from having to come from the power switch. This configuration is not suitable for driving a high-side p-channel mosfet because a low driver output voltage will turn the p-channel mosfet on a W with VDD below 3.9 V. VDD Bypass Capacitor Guidelines To make this IC turn on the device quickly, the local high frequency bypass capacitor, CBYP, with low ESR and ESL should be connected between VDD and GND pins with minimum trace length. This capacitor is commonly used in driver and controller bias circuits with the addition of 10 to 47µF bulk electrolytic capacitors. A typical criterion for choosing the value of cbyp is to keep the ripple voltage on the VDD supply less than or equal to 5%. This usually reaches the load capacitance ceqv at a value greater than or equal to 20 times, defined here as qgate/vdd. Common choices for 0.1µf to 1µf or larger ceramic capacitors, such as X5R and X7R, have good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, CBYP can be increased to 50-100 times CEQV, or cbyp can be divided into tw-o capacitors. One should be a larger value based on the equivalent load capacitance, and another smaller value such as 1-10nf mounted closest to the VDD and GND pins that carry the high frequency components of the current pulse. This bypass capacitor must be supplied from both driver channels, if the driver sw is issued at the same time, the composite peak current from the CBYP ice should be as large as the W-hen one channel in sw-itching layout and connections refer to the FA N3216 and FAN3217 gate drivers Contains fast-reacting input circuitry, short propagation delays, and power stages capable of outputting current peaks in excess of 2 A to facilitate voltage transition times from below 10 ns to over 150 ns.

The following layout and connection guidelines are strongly recommended: Keep high-current output and power ground paths separate from logic input signal and signal ground paths. This is especially important for TTL level logic to drive the input pin thresholds. Keeping the driver as close to the load as possible minimizes the length of the high current trace. This reduces series inductance to improve high-speed switching itch while reducing EMI that can radiate to the driver input and surrounding circuitry. If the input of the channel is not externally connected, the internal 100k resistor is shown on the block diagram to command a low output. In noisy environments, it may be necessary to switch an unused channel to a short output switch to prevent noise from causing spurious traces. Many high-speed power circuits can be affected from their outputs or other external sources, possibly causing the output to retrigger. Test layouts with long input or output leads if the circuit is on a breadboard or non-optimal circuit. For best results, keep all pin connections as short and direct as possible. FA N3216 and FA N3217 with many other industry standard drivers. On and off current paths should be minimized, as described in the next section. The diagram shows the pulsed gate drive current path when the gate driver provides the gate charge to turn the mosfet on. Current is provided locally by the bypass capacitor, CBYP, and S current through the driver mosfet gate and ground. To reach the peak possible peak current, resistive and inductive paths should be minimized. The localized cbyp behavior contains peak current pulses in the driver bank circuit, preventing them from interfering with sensitive analog circuits in the pwm controller.

Fig. The current path for the mosfet to power up, the diagram shows the current path of the gate driver to turn off the mosfet. Ideally, the driver shuns the current loop loop directly to the mosfet source. For fast turn-off times, resistance and inductance in this path are minimized

Operating Waveform At power-up, the driver output remains low until the VDD voltage reaches the turn-on threshold. The amplitude of this output pulse increases as VDD increases until steady state VDD is reached. The operation shown in the irreversible diagram shows that the value remains low until the uvlo threshold is reached, then the output is in phase with the input. The inversion of the startup waveform is configured to show N in the graph. in+ is tied to vdd and the input signal is applied to the input -, the output pulse is tied to the on input. At power up, the inverting output remains low until the VDD voltage reaches the turn-on threshold, then it follows the input w with inversion.